Methods, apparatus, computer equipment, and storage media for implementing PCIe functional level reset

Abstract

This application relates to a method, apparatus, computer device, and storage medium for implementing PCIe functional level reset. The method includes: the SSD receiving an FLR interrupt signal from the SSD controller; the firmware jumping to an interrupt handler function to process the FLR event; the SSD returning to the main state machine and entering a reset state, terminating ongoing commands; after all commands have terminated normally, the firmware sending an NVMe core reset request to the SSD controller; the SSD initializing NVMe; the firmware writing FLR completion to the SSD controller and waiting for a hardware report of FLR completion; and the SSD reconfiguring its PCIe registers. This invention can solve the problem of FLR test failure on the Sanblaze test platform and can effectively improve test efficiency.

Description

Technical Field

[0001] This invention relates to the field of solid-state drive technology, and in particular to a method, apparatus, computer device, and storage medium for implementing PCIe functional level reset. Background Technology

[0002] Currently, PCIe function level reset (FLR) is triggered by the host software writing bit 15 (init flr) of the PCIe Device control register. The FLR must be completed within 100ms. The FLR only resets the internal state and registers of the corresponding function and does not affect the link-specific registers.

[0003] However, the existing FLR solution failed the FLR test on the sanblaze (an SSD testing software) test platform. Because the SSD was in the process of reading and writing commands, the host issued an FLR request before the read and write commands were completed. When the device received the FLR interrupt, it reset the NVMe Core in the interrupt, causing the unfinished node to get stuck and unable to complete smoothly, ultimately resulting in the test failure. Summary of the Invention

[0004] Therefore, it is necessary to provide a method, apparatus, computer device, and storage medium for implementing PCIe functional level reset in order to address the above-mentioned technical problems.

[0005] A method for implementing PCIe functional level reset, the method comprising:

[0006] When the SSD receives the FLR interrupt signal from the SSD controller, the firmware jumps to the interrupt handler function to process the FLR event.

[0007] The SSD returns to the main state machine, enters the reset state, and terminates the ongoing commands.

[0008] After all commands have terminated normally, the firmware sends an NVMe core reset request to the SSD controller;

[0009] The SSD performs NVMe initialization;

[0010] The firmware writes the FLR to the SSD controller and waits for the hardware to report that the FLR is complete. The SSD then reconfigures the PCIe registers.

[0011] In one embodiment, the step of the SSD receiving the FLR interrupt signal from the SSD controller and the firmware jumping to the interrupt handler function to process the FLR event further includes:

[0012] In the FLR interrupt event, only the FLR event is marked and no reset-related operations are performed.

[0013] In one embodiment, the step of obtaining the FLR interrupt signal from the SSD controller before the SSD acquires the SSD's input is further included:

[0014] After the SSD powers on, it processes commands normally and executes the FLR test script.

[0015] The host sends an FLR reset request to the SSD.

[0016] In one embodiment, after the step of the firmware writing the FLR to the SSD controller completes and waiting for the hardware to report the FLR completion, and the SSD reconfigures the PCIe registers, the following is further included:

[0017] Wait for the host to send the controller configuration register enable command, then restart command processing.

[0018] An apparatus for implementing PCIe functional level reset, the apparatus comprising:

[0019] The jump module is used for the SSD to obtain the FLR interrupt signal sent by the SSD controller, and the firmware jumps to the interrupt handling function to handle the FLR event.

[0020] The termination module is used to return the SSD to the main state machine, enter the reset state, and terminate the ongoing commands.

[0021] The sending module is used to send an NVMe core reset request to the SSD controller after all commands have terminated normally;

[0022] An initialization module, which is used to initialize the SSD for NVMe;

[0023] The write completion module is used by the firmware to write FLR completion to the SSD controller and wait for the hardware to report FLR completion, and then reconfigure the PCIe registers of the SSD.

[0024] In one embodiment, the jump module is further configured to:

[0025] In the FLR interrupt event, only the FLR event is marked and no reset-related operations are performed.

[0026] In one embodiment, the apparatus further includes a request module, the request module being configured to:

[0027] After the SSD powers on, it normally processes commands and executes the FLR test script.

[0028] The host sends an FLR reset request to the SSD.

[0029] In one embodiment, the device further includes a waiting module, the waiting module being used for:

[0030] Wait for the host to send the controller configuration register enable command, then restart command processing.

[0031] A computer device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of any of the methods described above.

[0032] A computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of any of the above methods.

[0033] The aforementioned PCIe functional level reset implementation method, apparatus, computer equipment, and storage medium obtain the FLR interrupt signal from the SSD controller via the SSD. The firmware jumps to the interrupt handling function to process the FLR event; the SSD returns to the main state machine, enters the reset state, and terminates the ongoing commands; after all commands have terminated normally, the firmware sends an NVMe core reset request to the SSD controller; the SSD initializes NVMe; the firmware writes the FLR completion to the SSD controller and waits for the hardware to report FLR completion; the SSD reconfigures the PCIe registers. This invention can solve the problem of FLR test failure on the Sanblaze test platform and can effectively improve test efficiency. Attached Figure Description

[0034] Figure 1 A flowchart illustrating the implementation of FLR in traditional technologies;

[0035] Figure 2 This is a flowchart illustrating a method for implementing PCIe functional level reset in one embodiment;

[0036] Figure 3 This is a flowchart illustrating the implementation method of PCIe functional level reset in another embodiment;

[0037] Figure 4 This is a flowchart illustrating the implementation of FLR in one embodiment;

[0038] Figure 5 This is a structural block diagram of a device for implementing PCIe functional level reset in one embodiment;

[0039] Figure 6 This is a structural block diagram of a device for implementing PCIe functional level reset in another embodiment;

[0040] Figure 7 This is a structural block diagram of the device for implementing PCIe functional level reset in another embodiment;

[0041] Figure 8 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0042] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0043] Currently, reference Figure 1 The process of FLR implementation in traditional technology is shown. The existing FLR solution failed the FLR test on the Sanblaze test platform. Because the SSD was in the process of reading and writing commands, the host issued the FLR request before the read and write commands were completed. When the device received the FLR interrupt, it reset the NVMe Core in the interrupt, which caused the node that had not yet finished processing to get stuck and unable to complete smoothly, and the test failed.

[0044] Based on this, the present invention proposes a method for implementing PCIe functional level reset, which aims to solve the problem of FLR test failure on the Sanblaze test platform.

[0045] In one embodiment, such as Figure 2 As shown, a method for implementing PCIe functional level reset is provided, the method including:

[0046] Step 202: The SSD receives the FLR interrupt signal from the SSD controller, and the firmware jumps to the interrupt handling function to process the FLR event.

[0047] Step 204: The SSD returns to the main state machine, enters the reset state, and terminates the ongoing commands.

[0048] Step 206: After all commands have terminated normally, the firmware sends an NVMe core reset request to the SSD controller.

[0049] Step 208: The SSD initializes NVMe;

[0050] Step 210: The firmware writes the FLR to the SSD controller and waits for the hardware to report the FLR completion. The SSD then reconfigures the PCIe registers.

[0051] This embodiment provides a method for implementing PCIe functional level reset, which can be used on the SanBlaze test platform. SanBlaze's simulation and verification products provide scalable, high-performance, and configurable simulation test environments for testing initiators (hosts) and targets (storage systems or SSDs) involved in technologies such as FC, FCoE, iSCSI, SAS / SATA, NVMe, NVMe over Fabric (NVMoF), and NVMe over FC (FC-NVMe). SanBlaze's simulation products are widely deployed by the vast majority of mainstream storage hardware and software vendors worldwide.

[0052] This method can handle the SSD reset correctly when the host sends an FLR request while the SSD is performing a read / write command. The specific implementation process is as follows: First, the SSD obtains the FLR interrupt signal sent by the SSD controller, and the firmware jumps to the interrupt handling function to handle the FLR event.

[0053] In one embodiment, the step of the SSD receiving an FLR interrupt signal from the SSD controller and the firmware jumping to the interrupt handler to process the FLR event further includes: simply marking the FLR event in the FLR interrupt event without performing any reset-related operations. In this embodiment, when jumping to the interrupt handler to process the FLR event, only the event is marked, and no reset-related operations are performed.

[0054] Next, the SSD returns to the master state machine, enters the reset state, and terminates the ongoing commands. After all commands have been terminated normally, the firmware sends an NVMe core reset request to the SSD controller.

[0055] Then, the SSD performs NVMe initialization, the firmware writes the FLR to the SSD controller and waits for the hardware to report the FLR completion, and the SSD reconfigures the PCIe registers.

[0056] In this embodiment, the firmware receives the FLR interrupt signal from the SSD controller via the SSD, jumps to the interrupt handler function to process the FLR event, the SSD returns to the main state machine, enters the reset state, and terminates any ongoing commands, and after all commands have terminated normally, the firmware sends an NVMe core reset request to the SSD controller, the SSD initializes NVMe, the firmware writes the FLR completion to the SSD controller and waits for the hardware to report FLR completion, and the SSD reconfigures the PCIe registers. This solution can solve the problem of FLR test failure on the Sanblaze test platform and can effectively improve test efficiency.

[0057] In one embodiment, such as Figure 3As shown, a method for implementing PCIe functional level reset is provided, the method including:

[0058] Step 302: After the SSD powers on, it normally processes commands and executes the FLR test script;

[0059] Step 304: The host sends an FLR reset request to the SSD;

[0060] Step 306: The SSD receives the FLR interrupt signal from the SSD controller, and the firmware jumps to the interrupt handling function to process the FLR event.

[0061] Step 308: The SSD returns to the main state machine, enters the reset state, and terminates the ongoing commands.

[0062] Step 310: After all commands have terminated normally, the firmware sends an NVMe core reset request to the SSD controller.

[0063] Step 312: The SSD initializes NVMe;

[0064] Step 314: The firmware writes the FLR to the SSD controller and waits for the hardware to report that the FLR is complete. The SSD then reconfigures the PCIe registers.

[0065] Step 316: Wait for the host to send the controller configuration register enable command, and restart command processing.

[0066] In this embodiment, reference can be made to Figure 4 The flowchart shown below illustrates the implementation process of FLR.

[0067] 1. After normal power-on, the SSD processes commands normally and executes the FLR test script.

[0068] 2. The host sends an FLR reset request, which can be triggered by writing bit 15 (init flr) of the PICe Device control register.

[0069] 3. The SSD receives an FLR interrupt signal from the SSD Controller.

[0070] 4. The firmware jumps to the interrupt handler function to process the FLR event. At this time, the event is only marked and no reset-related operations are performed.

[0071] 5. The SSD returns to the main state machine and enters the reset state, first aborting (terminating) the ongoing command.

[0072] 6. Wait for all commands to terminate normally.

[0073] 7. The firewall sends an NVMe core reset request to the SSD controller.

[0074] 8. Perform NVMe initialization on the SSD.

[0075] 9. The firmware writes "FLR done" to the SSD controller and waits for the hardware to report that the FLR is complete.

[0076] 10. Reconfigure the PCIe registers of the SSD.

[0077] 11. Wait for the host to send CC EN (controller configuration register enable) to restart command processing.

[0078] It should be understood that, although Figure 1-4 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 1-4 At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0079] In one embodiment, such as Figure 5 As shown, a PCIe functional level reset implementation device 500 is provided, the device comprising:

[0080] Jump module 501, the jump module is used for the SSD to obtain the FLR interrupt signal sent by the SSD controller, and the firmware jumps to the interrupt handling function to handle the FLR event;

[0081] Termination module 502, the termination module is used for the SSD to return to the main state machine to enter the reset state and terminate the ongoing command;

[0082] Sending module 503, the sending module is used to send an NVMe core reset request to the SSD controller after all commands have been terminated normally;

[0083] Initialization module 504, the initialization module is used for SSD NVMe initialization;

[0084] Write completion module 505 is used by the firmware to write FLR completion to the SSD controller and wait for the hardware to report FLR completion, and the SSD reconfigures the PCIe registers.

[0085] In one embodiment, the jump module 501 is further configured to:

[0086] In the FLR interrupt event, only the FLR event is marked and no reset-related operations are performed.

[0087] In one embodiment, such as Figure 6 As shown, a PCIe functional level reset implementation device 500 is provided. This device further includes a request module 506, which is used for:

[0088] After the SSD powers on, it normally processes commands and executes the FLR test script.

[0089] The host sends an FLR reset request to the SSD.

[0090] In one embodiment, such as Figure 7 As shown, a PCIe functional level reset implementation device 500 is provided. This device further includes a wait module 507, which is used for:

[0091] Wait for the host to send the controller configuration register enable command, then restart command processing.

[0092] For specific limitations on the implementation device of PCIe functional level reset, please refer to the limitations on the implementation method of PCIe functional level reset mentioned above, which will not be repeated here.

[0093] In one embodiment, a computer device is provided, the internal structure of which can be shown as follows: Figure 8 As shown, the computer device includes a processor, memory, and a network interface connected via a device bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores operating devices, computer programs, and databases. The internal memory provides an environment for the operation of the operating devices and computer programs stored in the non-volatile storage media. The network interface is used for communication with external terminals via a network connection. When the computer program is executed by the processor, it implements a method for PCIe functional level reset.

[0094] Those skilled in the art will understand that Figure 8The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0095] In one embodiment, a computer device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps in the various method embodiments described above.

[0096] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the steps in the various method embodiments described above.

[0097] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0098] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0099] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for implementing PCIe functional level reset, characterized in that, The method includes: After the SSD powers on, it normally processes commands and executes the FLR test script; the host sends an FLR reset request to the SSD. When the SSD receives the FLR interrupt signal from the SSD controller, the firmware jumps to the interrupt handler function to process the FLR event. In the FLR interrupt event, the FLR event is only marked and no reset-related operations are performed. The SSD returns to the main state machine, enters the reset state, and terminates the ongoing commands. After all commands have terminated normally, the firmware sends an NVMe core reset request to the SSD controller; The SSD performs NVMe initialization; The firmware writes the FLR to the SSD controller and waits for the hardware to report that the FLR is complete. The SSD then reconfigures the PCIe registers.

2. The method for implementing PCIe functional level reset according to claim 1, characterized in that, After the firmware completes writing the FLR to the SSD controller and waits for the hardware to report the FLR completion, and the SSD reconfigures the PCIe registers, the following steps are also included: Wait for the host to send the controller configuration register enable command, then restart command processing.

3. A device for implementing PCIe functional level reset, characterized in that, The device includes: The request module is used for normal processing commands after the SSD powers on, executing the FLR test script; the host sends an FLR reset request to the SSD; The jump module is used for the SSD to obtain the FLR interrupt signal sent by the SSD controller, and the firmware jumps to the interrupt handling function to handle the FLR event. In the FLR interrupt event, the FLR event is only marked and no reset-related operation is performed. The termination module is used to return the SSD to the main state machine, enter the reset state, and terminate the ongoing commands. The sending module is used to send an NVMe core reset request to the SSD controller after all commands have terminated normally; An initialization module, which is used to initialize the SSD for NVMe; The write completion module is used by the firmware to write FLR completion to the SSD controller and wait for the hardware to report FLR completion, and then reconfigure the PCIe registers of the SSD.

4. The apparatus for implementing PCIe functional level reset according to any one of claims 3, characterized in that, The device further includes a waiting module, the waiting module being used for: Wait for the host to send the controller configuration register enable command, then restart command processing.

5. A computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 2.

6. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 2.

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