A PCIe data link recovery method and a PCIe system

Abstract

The application provides a PCIe data link recovery method and a PCIe system, and relates to the technical field of PCIe communication technology.When it is determined that the current board card is an EP end, a MODprel signal is acquired, and it is determined whether the MODprel signal is a low level; wherein the MODprel signal is used to indicate whether an optical module is in place; if the MODprel signal is a low level, a first RXLOS signal is acquired, and it is determined whether the first RXLOS signal is a low level; wherein the first RXLOS signal is used to indicate whether an optical signal is in place; if yes, an RSSI signal is acquired, and the PCIe data link is reset according to the value of the RSSI signal, so that the data link is recovered; wherein the RSSI signal is used to represent the size of optical power. The application has the effect that the PCIe system can automatically re-establish a chain after the optical module or the optical fiber line is plugged in or unplugged.

Description

Technical Field

[0001] This application relates to the field of PCIe communication technology, and more specifically, to a PCIe data link recovery method and a PCIe system. Background Technology

[0002] PCIe (Pripheral Component Interconnect express, a high-speed serial computer expansion bus standard) is a standard interface for connecting components to a computer. Upstream PCIe interfaces are used for communication with the motherboard's CPU (Central Processing Unit), while downstream interfaces are used for communication with PCIe peripherals; dynamic configuration is also possible through PCIe pseudo-ports. PCIe applications generally include the following:

[0003] 1. In high-performance computing platforms, the motherboard may integrate multiple CPUs, GPUs (Graphics Processing Units) or other accelerators and connect them via the PCIe bus.

[0004] 2. In high-performance storage solutions, NVMe SSDs (Non-Volatile Memory Express SolidState Drives) occupy a key position, and multiple NVMe SSDs need to be connected to the motherboard via the PCIe bus.

[0005] 3. In various AICs (Add-In Cards), including AI (Artificial Intelligence) accelerators, NICs (Network Interface Controllers), and storage expansion cards, they are also generally interconnected with server devices through PCIe interfaces.

[0006] In the aforementioned PCIe application scenarios, it is necessary to address the issue of long PCIe signal line paths caused by large-scale integration or size and structural problems. Currently, a fiber optic transmission solution combining retimer technology and optical modules can be adopted. This combination can support transmission distances of up to tens of meters. When using fiber optics for high-speed data transmission, the retimer chip helps with the conversion and recovery of electrical signals, effectively overcoming signal attenuation and distortion problems caused by fiber length and medium differences. Therefore, this solution not only ensures data transmission rate and stability over long distances but also provides a flexible and reliable interconnection method for large-scale data centers.

[0007] However, because optical modules are hot-swappable and fiber optic cables are also pluggable, once a stable link is established, if a situation arises (such as replacing an optical module or fiber), hot-swapping the optical module or plugging / unplugging the fiber will interrupt the data link. Even after the optical path is restored, the PCIe system cannot automatically re-establish the link. Manual intervention is required to reset the RC (Root Complex) or EP (Endpoint) before the entire PCIe system can resume link establishment. This results in poor flexibility and inconvenience for users.

[0008] In summary, existing technologies have the problem that PCIe systems cannot automatically rebuild the link after the optical module is hot-plugged or the optical fiber is plugged in or unplugged. Summary of the Invention

[0009] The purpose of this application is to provide a PCIe data link recovery method and PCIe system to solve the problem in the prior art that the PCIe system cannot automatically rebuild the link after the optical module is hot-plugged or the optical fiber is plugged in or unplugged.

[0010] To achieve the above objectives, the technical solutions adopted in the embodiments of this application are as follows:

[0011] On one hand, this application provides a PCIe data link recovery method, which is applied to the MCU at the EP end of a PCIe system. The EP end further includes a retimer chip and an optical module, and the MCU is connected to the retimer chip and the optical module respectively. The method includes:

[0012] When it is determined that the current board is the EP end, the MODprel signal is acquired, and it is determined whether the MODprel signal is low; the MODprel signal is used to indicate whether the optical module is in place;

[0013] If the MODprel signal is low, the first RXLOS signal is acquired, and it is determined whether the first RXLOS signal is low; wherein, the first RXLOS signal is used to indicate whether the optical signal is in place;

[0014] If so, the RSSI signal is acquired, and the PCIe data link is reset according to the value of the RSSI signal to restore the data link; wherein, the RSSI signal is used to characterize the magnitude of optical power.

[0015] Optionally, the step of resetting the PCIe data link based on the value of the RSSI signal to restore the data link includes:

[0016] When the value of the RSSI signal is greater than the threshold, the PCIe data link is reset;

[0017] Acquire the second RXLOS signal and determine whether the second RXLOS signal is low.

[0018] If not, then confirm that the data link has been restored;

[0019] If so, the decision on whether to continue resetting the PCIe data link is based on the number of times the PCIe data link has been reset.

[0020] Optionally, the step of determining whether to continue resetting the PCIe data link based on the number of times the PCIe data link has been reset includes:

[0021] Determine if the number of times the PCIe data link is reset exceeds a set value;

[0022] If so, a fault signal is generated, and resetting the PCIe data link is stopped;

[0023] If not, the PCIe data link is reset again, and the control counter is incremented.

[0024] Optionally, the EP terminal further includes a power supply unit, which is used to supply power to the retimer chip, and the power supply unit is connected to the MCU. The step of resetting the PCIe data link includes:

[0025] The power supply unit is controlled to perform a power-down and power-on operation, or the retimer chip is controlled to reset.

[0026] Optionally, after acquiring the RSSI signal, the method further includes:

[0027] Determine if the RSSI signal has a return value;

[0028] If so, then perform the step of resetting the PCIe data link based on the value of the RSSI signal;

[0029] If not, return to the step of obtaining the MODprel signal and determining whether the MODprel signal is low.

[0030] Optionally, before determining that the current board is an EP terminal, the method further includes:

[0031] When the MCU's end device selection pin is a high-level signal, the current board is determined to be the EP end;

[0032] When the MCU's end device selection pin is a low-level signal, the current board is determined to be an RC terminal.

[0033] Optionally, after determining that the current board is an RC terminal, the method further includes:

[0034] Provides normal power-on conditions for the RC terminal and continuously acquires signals from the optical module.

[0035] Optionally, after determining whether the MODprel signal is low, the method further includes:

[0036] When the MODprel signal is high, continuously acquire the MODprel signal, and when the MODprel signal transitions from high to low, execute the step of acquiring the RSSI signal.

[0037] Optionally, after determining whether the first RXLOS signal is low, the method further includes:

[0038] If the first RXLOS signal is high, it is determined that the data link is working normally.

[0039] On the other hand, this application embodiment also provides a PCIe system, which includes an RC end and an EP end. Both the RC end and the EP end include a retimer chip and an optical module. The RC end and the EP end are connected through the optical module. The EP end also includes an MCU, which is used to execute the above-mentioned PCIe data link recovery method.

[0040] Compared with the prior art, this application has the following advantages:

[0041] This application provides a PCIe data link recovery method and PCIe system. The method is applied to the MCU at the EP end of the PCIe system. The EP end also includes a retimer chip and an optical module. The MCU is connected to the retimer chip and the optical module respectively. When it is determined that the current board is the EP end, the MODprel signal is acquired, and it is determined whether the MODprel signal is low. The MODprel signal is used to indicate whether the optical module is present. If the MODprel signal is low, the first RXLOS signal is acquired, and it is determined whether the first RXLOS signal is low. The first RXLOS signal is used to indicate whether the optical signal is present. If so, the RSSI signal is acquired, and the PCIe data link is reset according to the value of the RSSI signal to restore the data link. The RSSI signal is used to characterize the magnitude of the optical power. In the PCIe data link recovery method provided in this application, the MCU comprehensively judges the current optical path status by monitoring the MODprel signal, RXLOS signal and RSSI signal of the optical module pins, and determines to reset the PCIe data link based on the signal status, thereby realizing data link recovery. This achieves the effect of automatically re-establishing the link and restoring data communication function when optical modules or optical fibers are plugged in or unplugged on the EC or EP side.

[0042] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0043] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0044] Figure 1 This is a schematic diagram of the PCIe system provided in this application.

[0045] Figure 2 An exemplary flowchart of the PCIe data link recovery method provided in this application.

[0046] Figure 3 A schematic diagram of the EP module provided in this application.

[0047] Figure 4 A schematic diagram of the overall process of the PCIe data link recovery method provided in this application.

[0048] In the picture:

[0049] 110 - MCU; 120 - retimer chip; 130 - optical module; 140 - power supply unit. Detailed Implementation

[0050] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0051] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0052] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this application, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0053] It should be noted that in this paper, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0054] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0055] As described in the background section, current PCIe applications often face the challenge of long signal path lengths due to large-scale integration or size limitations. To address this, a PCIe retimer chip is typically added to the signal path to maintain signal integrity. Utilizing a PCIe retimer chip effectively overcomes signal attenuation caused by long-distance transmission, ensuring data transmission stability and efficiency. This supports complex computing needs and high-performance operating environments, enabling reliable high-speed data transmission even on large, complex motherboards.

[0056] However, in practical applications, even with PCIe retimer support, the maximum insertion loss is only 36dB, and the maximum supported transmission cable length cannot exceed 1 meter. With continuous technological advancements, increased signal bandwidth, the emergence of larger-scale integrated computing platforms and server platforms, and new application environments (such as automotive), the traditional method of expanding PCIe routing paths using retimer chips is increasingly showing its limitations. For example, a PCIe 5.0 retimer chip can only support a maximum of 1000mil board-level traces and two connects (independent physical connection points or connectors) with limited insertion loss. Facing higher PCIe transmission rates (PCIe 6.0 / 7.0) and more complex integrated environments, the routing capabilities supported by PCIe retimer chips cannot meet the demands.

[0057] Therefore, to meet the demands of high-speed data transmission over longer distances, such as high-speed interconnection within data centers or between data center server rooms, a fiber optic transmission solution combining retimer technology and optical modules is required. This combination can support transmission distances of tens of meters. When using fiber optics for high-speed data transmission, the retimer chip facilitates the conversion and recovery of electrical signals, effectively overcoming signal attenuation and distortion problems caused by fiber length and medium differences. Therefore, this solution not only ensures data transmission rates and stability over long distances but also provides a flexible and reliable interconnection method for large-scale data centers.

[0058] However, in solutions combining retimer technology and optical modules, the hot-swappable nature of both the optical modules and the fiber optic cables means that after a stable connection is established, if any situation arises (such as replacing the optical module or fiber), hot-swapping the optical module or plugging / unplugging the fiber will interrupt the data link. Furthermore, even after the optical path is restored, the PCIe system cannot automatically re-establish the connection; manual intervention is required to reset the RC or EP ends before the entire PCIe system can re-establish the connection. This lack of flexibility and inconvenience for users is significant.

[0059] In view of this, in order to solve the above problems, this application provides a PCIe data link recovery method to automatically re-establish the data link after the optical module or fiber is plugged in or unplugged, thereby restoring the data communication function.

[0060] It should be noted that the PCIe data link recovery method provided in this application is applied to the MCU at the EP end of the PCIe system. Please refer to [link / reference needed]. Figure 1 This is a schematic diagram of the PCIe system provided in this application.

[0061] like Figure 1As shown, the PCIe system includes an RC end (left side of the diagram) and an EP end (right side of the diagram). The RC end and EP end have basically the same structure, both including a PCIe board (CEM board in the diagram), a retimer chip 120, and an optical module 130 (QSFP_DD in the diagram). For the RC end, the retimer chip 120 is located on the PCIe board and is inserted into the gold finger slot on the server side via gold fingers. The server side contains a CPU. Data is transmitted through the retimer chip 120, and after passing through two QSFP-DD packaged LPOs (Linear-drive Pluggable Optics), 16 PCIe electrical signals are converted into optical signals, which are then connected to the PCIe board on the EP end via optical fiber.

[0062] For the EP end, the retimer chip 120 is also located on the PCIe board. The optical module 130 on the EP end converts the optical signal into an electrical signal and connects it to the retimer chip 120. Then, it connects to the corresponding EP device through the slot on the PCIe board (slot in the figure) to realize signal transmission. Once the optical module 130 or fiber optic cable is plugged in or unplugged, the PCIe data link needs to be rebuilt to enable data transmission between the RC end and the EP end. It should be noted that the plugging and unplugging mentioned in this application refers to the operation of first unplugging the optical module 130 or fiber optic cable and then inserting it. For example, taking the optical module 130 as an example, the optical module 130 is connected to the PCIe board by plugging in, and the plug interface is connected to the retimer chip 120. Thus, after the optical module 130 is plugged into the PCIe board, communication can be realized between the optical module 130 and the retimer chip 120. When under certain operating conditions, such as when the optical module 130 needs to be repaired, the optical module 130 needs to be removed from the interface. After the repair is completed, the optical module 130 is then inserted back into the interface. This operation completes the insertion and removal of the optical module 130.

[0063] After the optical module 130 is plugged in or unplugged, in the prior art, the optical module 130 at the RC end and the optical module 130 at the EP end cannot automatically re-establish a link to achieve communication. Therefore, this application utilizes the MCU 110 on the EP end PCIe board ( Figure 1 (Not shown in the image) By combining the PCIe data link recovery method, the data link can be automatically re-established, thereby restoring data communication.

[0064] The PCIe data link recovery method provided in this application is illustrated below:

[0065] As one implementation method, please refer to Figure 2 The method includes:

[0066] S102, when it is determined that the current board is the EP end, the MODprel signal is obtained and it is determined whether the MODprel signal is low; wherein, the MODprel signal is used to indicate whether the optical module is in place; if yes, then S104 is executed, if no, then S105 is executed.

[0067] S104: Obtain the first RXLOS signal and determine whether the first RXLOS signal is low; wherein, the first RXLOS signal is used to indicate whether the optical signal is in place; if yes, then execute S106, if no, then execute S107.

[0068] S105, continuously acquire the MODprel signal, and execute S106 when the MODprel signal transitions from high level to low level.

[0069] S106, acquire the RSSI signal, and reset the PCIe data link according to the value of the RSSI signal to restore the data link; wherein, the RSSI signal is used to characterize the magnitude of optical power.

[0070] S107, confirm that the data link is working properly.

[0071] In this application, the MCU110 on the EP side controls the data link reconstruction; therefore, it is necessary to first determine whether the current PCIe board is an EP side. For one implementation method, please refer to... Figure 3 This is a schematic diagram of the EP module in this application, as shown below. Figure 3 As shown, the PCIe system includes a DIP switch connected to the MCU110. This DIP switch is used to indicate whether the current PCIe board is an EP (Electronic Power Supply) device. For example, after a worker plugs or unplugs the optical module 130, they can toggle the DIP switch to the EP position, thus enabling the MCU110 to determine that the current board is an EP device.

[0072] In another implementation, the MCU110 can also be connected to external processors or other devices to receive corresponding signals and determine whether the current PCIe board is an EP terminal.

[0073] It should be noted that since MCU110 is present on both the EP and RC terminals, each MCU110 has a terminal device selection pin. When the terminal device selection pin of MCU110 is high, the current board is identified as the EP terminal; when it is low, the current board is identified as the RC terminal. Of course, it can also be configured so that a high signal on the MCU110 terminal device selection pin identifies the current board as the RC terminal, and a low signal identifies the current board as the EP terminal; this is not a limitation.

[0074] Furthermore, when it is determined that the current PCIe board is the RC terminal, the MCU110 controls the PCIe system to operate normally, provides normal power-on conditions for the RC terminal, and continuously acquires the signal from the optical module 130, thereby determining from the acquired signal whether a communication failure or other situation has occurred.

[0075] When it is determined that the current PCIe card is on the EP side, the MODprel signal is acquired, and it is determined whether the MODprel signal is low. For example... Figure 3 As shown, during the operation of the optical module 130, its internal sensors continuously collect relevant operating data, such as voltage, temperature, output optical power, and input optical power. Therefore, during operation, the optical module 130 needs to send signals back to the MCU 110 in real time. These signals include the MODprel signal, RXLOS, and RSSI signal.

[0076] It should be noted that, Figure 3 In order to construct 16 communication links in the PCIe system, two optical modules 130 are used at both the EP and RC ends. The two optical modules 130 are powered by a power supply; for example, both optical modules 130 are powered by a 3.3V power supply. Furthermore, one optical module 130 provides N / 2 communication links, and the other optical module 130 provides another N / 2 communication links, so that the retimer chip 120 constructs a total of N communication links. Figure 3 As shown, one optical module 130 provides N / 2 communication links (lan0-(n / 2-1)) and the other optical module 130 provides N / 2 communication links (lan(n / 2)-(n-1)). Optical modules 130 are connected to the retimer chip 120 via lan0-(n / 2-1) and lan(n / 2)-(n-1), and the N communication links (lan0-(n-1)) of the retimer chip 120 are connected to the gold fingers, and then connected to the backend EP device via the gold fingers. Therefore, when the MCU 110 acquires signals, it simultaneously acquires signals from both optical modules 130. This application does not specifically limit the value of N. For example, N can be 16 or 32. When N is 16, one optical module 130 is used to provide 8 communication links from lan0 to 7, and the other optical module 130 is used to provide 8 communication links from lan8 to 15. The optical module 130 is connected to the retimer chip 120 through lan0 to 7 and lan8 to 15, and the N communication links of the retimer chip 120, lan0 to 15, are connected to the gold finger.

[0077] The MODprel signal is used to indicate whether the optical module 130 is in place, that is, whether the operator has inserted the optical module 130. If the operator has inserted the optical module 130, the MODprel signal is low; if the optical module 130 is not inserted, the MODprel signal is high.

[0078] As can be seen, if the MODprel signal is low, we can continue to determine the next signal, namely the RXLOS signal; if the MODprel signal is high, then... Figure 2 As shown, MCU110 continuously acquires the MODprel signal and monitors its status. Once it detects the MODprel signal transitioning from high to low, it indicates that the optical module 130 has been plugged in. At this point, MCU110 directly performs RSSI signal determination. It should be noted that when the MODprel signal transitions from high to low, the determination of the first RXLOS signal is skipped, and the RSSI signal is determined directly to improve the efficiency of data link recovery.

[0079] The first RXLOS signal is used to indicate whether the optical signal is present, that is, whether the peer board has an optical signal, or whether the PCIe board at the RC end has an optical signal. When the first RXLOS signal is high, it means that the peer board has an optical signal; when the first RXLOS signal is low, it means that the peer board has no optical signal. For example, the optical module 130 at the RC end is not plugged in, or the optical module 130 is plugged in but does not send a signal, or the optical module 130 is plugged in and has sent a signal, but due to the link failure, the EP end cannot receive the optical signal and convert it into an electrical signal.

[0080] It should be noted that when the first RXLOS signal is high, it indicates that the RC end board has normally emitted an optical signal and it has been recognized by the EP end. Therefore, the MCU110 can directly determine that the data link is normal and end the entire process. Furthermore, in some implementations, the MCU110 automatically initiates data link recovery. In this case, after determining that the first RXLOS signal is high, the MCU110 will immediately or after a delay return to step S102. If the first RXLOS signal is low, the data link recovery process continues. In other implementations, the initiation of data link recovery can also be customized by the operator. For example, a data link self-recovery button can be set. When the operator inserts the optical module 130, they can press the data link self-recovery button, and the MCU110 will begin the data link recovery action. In this method, the entire data link recovery process ends after the first RXLOS signal is determined to be high.

[0081] When the first RXLOS signal is detected to be low, it indicates that the optical signal is not in place, which may be caused by various factors. Therefore, the MCU110 continues to acquire the RSSI signal and resets the PCIe data link based on the value of the RSSI signal. The RSSI signal is used to characterize the optical power, specifically, the value of the optical power received by the EP end through the optical module 130.

[0082] After acquiring the RSSI signal, the method further includes:

[0083] S081, determine if the RSSI signal has a return value. If yes, proceed to S1082; otherwise, return to S102.

[0084] S1082, execute the step of resetting the PCIe data link based on the value of the RSSI signal.

[0085] Understandably, when the first RXLOS signal is low, the reason for the optical signal not being present could be a fault in the optical signal at the RC end, a link fault, or a fault in the optical module 130 itself. Specifically, if the fault is in the optical signal at the RC end, for example, if the optical module 130 is not inserted at the RC end, or if the optical module 130 is inserted but does not emit an optical signal, then the RSSI signal at the EP end will not return a value; if the optical signal at the RC end is normal, then the RSSI signal at the EP end will return a value.

[0086] If the RSSI signal at the EP end has no return value, the process returns to the step of checking if the MODprel signal is low, until the RSSI signal at the EP end returns a value. If the RSSI signal at the EP end has a return value, the PCIe data link needs to be reset based on the value of the RSSI signal.

[0087] S106 includes:

[0088] S1061: When the value of the RSSI signal is greater than the threshold, the PCIe data link is reset.

[0089] S1062, acquire the second RXLOS signal and determine whether the second RXLOS signal is low; if not, execute S1063, if yes, execute S1064.

[0090] S1063 confirms that the data link has been restored.

[0091] S1064, determine whether to continue resetting the PCIe data link based on the number of times the PCIe data link has been reset.

[0092] When the RSSI signal returns a value, there may also be a link failure, such as optical power attenuation caused by a link failure. Therefore, it is necessary to further determine whether the value of the RSSI signal is greater than the threshold. If the value of the RSSI signal is less than the threshold, the steps of re-acquiring the value of the RSSI signal and determining whether the RSSI signal returns a value are executed.

[0093] If the RSSI signal value is greater than the threshold, the PCIe data link is reset, thereby resetting the data link. Furthermore, after the data link is reset, the MCU110 continues to acquire the second RXLOS signal and determines whether the second RXLOS signal is low. It is understood that in this application, the first RXLOS signal is the signal acquired by the MCU110 before the data link reset, and the second RXLOS signal is the signal acquired by the MCU110 after the data link reset.

[0094] If the second RXLOS signal is high, it indicates that the data link is normal after the reset and the PCIe data link has been restored; if the second RXLOS signal is low, a fault may have occurred after the data link was reset, and the data link needs to be reset again until the number of resets exceeds the set value.

[0095] Specifically, resetting the data link actually resets the retimer chip 120. Please refer to [link / reference]. Figure 3 In one implementation, the EP terminal also includes a power supply unit 140. The retimer chip 120 is reset by resetting the power supply unit 140. Specifically, the MCU 110 first sets Power_en low, causing the power supply unit 140 to stop supplying power to the retimer chip 120, and then sets Power_en high, allowing the power supply unit 140 to supply power to the retimer chip 120. For the retimer chip 120, this completes the power-down and power-on process, thus achieving a reset of the retimer chip 120. In another implementation, the MCU 110 can also directly reset the retimer chip 120 by setting reset high.

[0096] Furthermore, when determining whether to continue resetting the PCIe data link based on the number of times it has been reset, it can be determined whether the number of resets exceeds a set value. If the number of resets exceeds the set value, it indicates a possible fault in the optical module 130 itself. In this case, the MCU 110 will generate a fault signal and stop resetting the PCIe data link. Please continue reading. Figure 2The EP terminal also includes indicator lights connected to the MCU110. When the MCU110 generates a fault signal, it will indicate this via the indicator lights, prompting personnel to inspect the optical module 130. If the number of resets does not exceed a set value, the PCIe data link will be reset again, and the counter will be incremented. This application does not limit the set value; for example, the set value can be set to 2, so that when the number of resets reaches 3, the MCU110 will generate a fault signal and control the indicator lights to illuminate.

[0097] Please see Figure 4 The above is a flowchart of the PCIe data link recovery method provided in this application. First, it is determined whether the current board is an EP terminal. Then, it is determined in sequence whether the MODprel signal is low, whether the first RXLOS signal is low, whether the RSSI signal has a return value, and whether the RSSI signal is greater than the threshold. After that, the PCIe data link is reset. Then, it is determined whether the second RXLOS signal is low. If so, the PCIe data link is reset again. If not, the process ends.

[0098] Understandably, a PCIe board with a retimer chip and optical module enables link establishment and long-distance transmission between the RC and EP sides. When the optical module or fiber optic cable is plugged in or unplugged on either the RC or EP side, the MCU on the EP side board can determine the current optical path status by reading the MODprel and RXLOS signals and the RSSI value of the optical module. Based on the MCU control logic, the PCIe data link can be automatically restored from the newly established link by resetting the EP side retimer chip.

[0099] In summary, this application provides a PCIe data link recovery method and a PCIe system. This method is applied to the MCU at the EP end of the PCIe system. The EP end also includes a retimer chip and an optical module. The MCU is connected to the retimer chip and the optical module respectively. When it is determined that the current board is the EP end, the MODprel signal is acquired, and it is determined whether the MODprel signal is low. The MODprel signal is used to indicate whether the optical module is present. If the MODprel signal is low, the first RXLOS signal is acquired, and it is determined whether the first RXLOS signal is low. The first RXLOS signal is used to indicate whether the optical signal is present. If so, the RSSI signal is acquired, and the PCIe data link is reset according to the value of the RSSI signal to restore the data link. The RSSI signal is used to characterize the magnitude of the optical power. In the PCIe data link recovery method provided in this application, the MCU comprehensively judges the current optical path status by monitoring the MODprel signal, RXLOS signal and RSSI signal of the optical module pins, and determines to reset the PCIe data link based on the signal status, thereby realizing data link recovery. This achieves the effect of automatically re-establishing the link and restoring data communication function when optical modules or optical fibers are plugged in or unplugged on the EC or EP side.

[0100] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

[0101] It will be apparent to those skilled in the art that this application is not limited to the details of the exemplary embodiments described above, and that this application can be implemented in other specific forms without departing from the spirit or essential characteristics of this application. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of this application is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this application. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. A PCIe data link recovery method, characterized in that, The method is applied to the MCU at the EP end of a PCIe system. The EP end also includes a retimer chip and an optical module. The MCU is connected to the retimer chip and the optical module respectively. The method includes: When it is determined that the current board is the EP end, the MODprel signal is acquired, and it is determined whether the MODprel signal is low; the MODprel signal is used to indicate whether the optical module is in place; If the MODprel signal is low, the first RXLOS signal is acquired, and it is determined whether the first RXLOS signal is low; wherein, the first RXLOS signal is used to indicate whether the optical signal is in place; If so, the RSSI signal is acquired, and the PCIe data link is reset according to the value of the RSSI signal to restore the data link; wherein, the RSSI signal is used to characterize the magnitude of optical power.

2. The PCIe data link recovery method as described in claim 1, characterized in that, The steps of resetting the PCIe data link based on the RSSI signal value to restore the data link include: When the value of the RSSI signal is greater than the threshold, the PCIe data link is reset; Acquire the second RXLOS signal and determine whether the second RXLOS signal is low. If not, then confirm that the data link has been restored; If so, the decision on whether to continue resetting the PCIe data link is based on the number of times the PCIe data link has been reset.

3. The PCIe data link recovery method as described in claim 2, characterized in that, The steps for determining whether to continue resetting the PCIe data link based on the number of times the PCIe data link has been reset include: Determine if the number of times the PCIe data link is reset exceeds a set value; If so, a fault signal is generated, and resetting the PCIe data link is stopped; If not, the PCIe data link is reset again, and the control counter is incremented.

4. The PCIe data link recovery method as described in claim 2, characterized in that, The EP terminal also includes a power supply unit, which is used to supply power to the retimer chip and is connected to the MCU. The step of resetting the PCIe data link includes: The power supply unit is controlled to perform a power-down and power-on operation, or the retimer chip is controlled to reset.

5. The PCIe data link recovery method as described in claim 1, characterized in that, After acquiring the RSSI signal, the method further includes: Determine if the RSSI signal has a return value; If so, then perform the step of resetting the PCIe data link based on the value of the RSSI signal; If not, return to the step of obtaining the MODprel signal and determining whether the MODprel signal is low.

6. The PCIe data link recovery method as described in claim 1, characterized in that, Before determining that the current board is an EP terminal, the method further includes: When the MCU's end device selection pin is a high-level signal, the current board is determined to be the EP end; When the MCU's end device selection pin is a low-level signal, the current board is determined to be an RC terminal.

7. The PCIe data link recovery method as described in claim 6, characterized in that, After determining that the current board is an RC terminal, the method further includes: Provides normal power-on conditions for the RC terminal and continuously acquires signals from the optical module.

8. The PCIe data link recovery method as described in claim 1, characterized in that, After determining whether the MODprel signal is low, the method further includes: When the MODprel signal is high, continuously acquire the MODprel signal, and when the MODprel signal transitions from high to low, execute the step of acquiring the RSSI signal.

9. The PCIe data link recovery method as described in claim 1, characterized in that, After determining whether the first RXLOS signal is low, the method further includes: If the first RXLOS signal is high, it is determined that the data link is working normally.

10. A PCIe system, characterized in that, The PCIe system includes an RC end and an EP end, both of which include a retimer chip and an optical module. The RC end and the EP end are connected through the optical module. The EP end also includes an MCU, which is used to execute the PCIe data link recovery method as described in any one of claims 1 to 9.

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