Hardware operation verification method, device and storage medium based on random network topology

Abstract

The present invention discloses a method, device and storage medium for verifying hardware operation based on random network topology, the method comprising: calling an interface in a random network topology system to obtain target input data, the target input data being the data to be verified of the hardware; processing the target input data based on the algorithm graph structure and the simulation algorithm graph structure of the random network topology system to output the simulation algorithm graph structure of the target input data; compiling and running the simulation algorithm graph structure to obtain the simulation operation result of the hardware; comparing the simulation operation result with the actual operation result of the hardware based on the target input data to verify the operation result of the hardware. The present invention first obtains the data to be verified of the hardware through an interface, inputs the obtained data into the graph structure to compile and run to obtain the operation result, and finally compares to obtain the final verification result, thereby realizing the verification of the correctness of the hardware operation result.

Description

Technical Field

[0001] The present invention relates to the field of network technology, and in particular to a hardware operation verification method based on random network topology, a hardware operation verification device based on random network topology, and a computer-readable storage medium. Background Art

[0002] With the rapid development of deep learning, network simulation based on real networks has become increasingly important. However, due to the complexity and diversity of networks, networks simulated from real networks have certain defects, such as low stability. Among them, the most important factor affecting network stability is the network topology.

[0003] Although there are methods for generating network topology structures in the current related technologies, such as: manually specifying data to generate network topology, and randomly generating network topology, the generated network topology only objectively reflects the real network structure, and the operation results of the hardware cannot be verified.

[0004] It should be noted that the above contents are only used to assist in understanding the technical problems solved by the present invention, and do not constitute an admission that the above contents are related technologies. Summary of the invention

[0005] The main purpose of the present invention is to provide a random network topology verification method, device and computer-readable storage medium, which solves the problem that the network topology in the related art cannot verify the operation results of the hardware, and realizes the use of network topology to verify the correctness of the hardware.

[0006] To achieve the above object, the present invention proposes a hardware operation verification method based on random network topology, and the steps of the hardware operation verification method based on random network topology include:

[0007] Calling an interface in the random network topology system to obtain target input data, where the target input data is data to be verified of the hardware;

[0008] Processing the target input data based on the algorithm graph structure and the simulated algorithm graph structure of the random network topology system to output the simulated algorithm graph structure of the target input data;

[0009] Compiling and running the simulation algorithm graph structure to obtain the simulation running result of the hardware;

[0010] The simulation operation result is compared with the actual operation result of the hardware based on the target input data to verify the operation result of the hardware.

[0011] Optionally, the step of processing the target input data based on the algorithm graph structure and the simulated algorithm graph structure of the random network topology system to output the simulated algorithm graph structure of the target input data includes:

[0012] Based on the algorithm graph structure and the target input data, obtaining corresponding algorithm data;

[0013] Based on the algorithm data, converting into digital data;

[0014] Based on the digital data, it is input into the algorithm graph structure to obtain a simulated algorithm graph structure.

[0015] Optionally, the step of compiling and running the simulation algorithm graph structure to obtain the simulation running result of the hardware includes:

[0016] Compiling the simulation algorithm graph structure to obtain a corresponding machine language;

[0017] Based on the machine language, a base conversion method is used to obtain simulation operation results.

[0018] Optionally, after the step of compiling and running the simulation algorithm graph structure to obtain the simulation running result of the hardware, the method further includes:

[0019] Comparing the simulation operation result and the algorithm data to obtain a difference between the simulation operation result and the algorithm data;

[0020] When the difference is less than or equal to a preset threshold, the comparison between the simulation operation result and the actual operation result of the hardware based on the target input data is performed to verify the operation result of the hardware.

[0021] Optionally, the step of obtaining corresponding algorithm data based on the algorithm graph structure and the target input data includes:

[0022] Obtain the size, convolution kernel size, padding value size and step size corresponding to the target input data;

[0023] Based on the algorithm graph structure, size, convolution kernel size, padding value size and step size, algorithm data is obtained.

[0024] Optionally, before the step of obtaining the algorithm data based on the algorithm graph structure and the target input data, the step further includes:

[0025] Acquire data types, topological structures, and neural network computing basic unit operators, and determine connection relationships between neural network computing basic unit operators based on the neural network computing basic unit operators;

[0026] Based on the connection relationship, topological structure and data type, an algorithm graph structure is generated.

[0027] Optionally, the step of determining the connection relationship between the neural network calculation basic unit operators based on the neural network calculation basic unit operators includes:

[0028] Based on the topological structure, mark the in-degree of each basic unit node of the neural network calculation and store it in an in-degree array;

[0029] Determine the size of the initial node data based on the neural network calculation basic unit operator;

[0030] Based on the in-degree array and the size of the initial node data, the connection relationship between the neural network calculation basic units is determined.

[0031] Optionally, the step of determining the size of the initial node data volume based on the neural network calculation basic unit operator includes:

[0032] Calculate the basic unit operator based on the neural network to obtain the corresponding parameter data size;

[0033] Based on the size of the parameter data, the corresponding size, convolution kernel size, padding value size and step size are obtained to calculate the initial node size.

[0034] In addition, to achieve the above-mentioned purpose, the present invention also provides a hardware operation verification device based on random network topology, and the hardware operation verification device based on random network topology includes: a memory, a processor, and a random network topology verification program stored in the memory and executable on the processor, and when the hardware operation verification program based on random network topology is executed by the processor, the steps of the hardware operation verification method based on random network topology as described above are implemented.

[0035] In addition, to achieve the above-mentioned purpose, the present invention also provides a computer-readable storage medium, on which a hardware operation verification program based on random network topology is stored. When the hardware operation verification program based on random network topology is executed by a processor, the steps of the hardware operation verification method based on random network topology as described above are implemented.

[0036] The present invention discloses a hardware operation verification method, device and medium based on random network topology. The steps of the hardware operation verification method based on random network topology include: calling an interface in a random network topology system to obtain target input data, wherein the target input data is the data to be verified of the hardware; processing the target input data based on the algorithm graph structure and the simulation algorithm graph structure of the random network topology system to output the simulation algorithm graph structure of the target input data; compiling and running the simulation algorithm graph structure to obtain the simulation operation result of the hardware; comparing the simulation operation result with the actual operation result of the hardware based on the target input data to verify the operation result of the hardware. The present invention first obtains the data required for hardware detection by calling an external interface, and then inputs the acquired data to be detected into an already constructed algorithm graph structure, obtains algorithm data after the algorithm graph structure processes the data to be detected, and then quantifies the algorithm data into digital data, and then inputs it into the algorithm graph structure to obtain a simulation algorithm graph structure. After compiling and running the simulation algorithm graph structure, a simulation operation result will be obtained, and the simulation operation result and the algorithm data are subtracted. When the difference is less than or equal to a preset threshold, the simulation algorithm and the actual hardware operation result are compared, that is, the two results are subtracted. If the difference is equal to 0, it means that the two operation results are consistent, which proves that there is no problem with the hardware operation result, thereby realizing the verification of the correctness of the hardware operation result. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 It is a schematic diagram of the device structure of the hardware operating environment involved in the embodiment of the present invention;

[0038] Figure 2 It is a flowchart of a first embodiment of a hardware operation verification method based on random network topology of the present invention;

[0039] Figure 3 It is a flow chart of a second embodiment of a hardware operation verification method based on random network topology of the present invention;

[0040] Figure 4 It is a flowchart of a third embodiment of a hardware operation verification method based on random network topology of the present invention;

[0041] Figure 5 A detailed flow chart of step S110 of the third embodiment of the hardware operation verification method based on random network topology of the present invention;

[0042] Figure 6 It is a flowchart of the fourth embodiment of the hardware operation verification method based on random network topology of the present invention.

[0043] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0044] It should be understood that the specific embodiments described herein are only used to explain the present invention, and are not used to limit the present invention.

[0045] The main technical problem solved by the present invention is to use a random network topology structure to verify the correctness of the hardware operation result. The technical means used are to first randomly generate a data type, then randomly generate a topology structure, and then randomly generate an OP operator (operator neural network calculation basic unit operator), determine the connection relationship between OPs according to the OP operator, that is, the shape (connection) relationship, input the shape relationship and the data type into the topology structure, generate an ALGO graph structure (algorithm graph structure), obtain the hardware to be tested data by calling an interface, and input the obtained data into the ALGO graph structure for calculation to obtain output data corresponding to an ALGO graph structure, and then quantize the ALGO output data and then perform composition to generate a SIM graph structure, output the SIM output result, compare the two output results of ALGO and SIM, if the output results of ALGO and SIM are less than 16, it is proved that there is no problem with the two comparison results, during which the SIM graph structure generates a test.model file, and test.model is run on systemC (C language system) to obtain simulated hardware results, and the output results of SIM and simulated hardware are compared. If the two are consistent, it can be considered that there is no problem with the hardware operation.

[0046] In order to better understand the above technical solution, exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.

[0047] In order to better understand the above technical solution, the above technical solution will be described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0048] like Figure 1 As shown, Figure 1 It is a schematic diagram of the device structure of the hardware operating environment involved in the embodiment of the present invention.

[0049] The device in the embodiment of the present invention may be a server device.

[0050] like Figure 1As shown, the device may include: a processor 1001, such as a CPU, a network interface 1004, a user interface 1003, a memory 1005, and a communication bus 1002. Among them, the communication bus 1002 is used to realize the connection and communication between these components. The user interface 1003 may include a display screen (Display), an input unit such as a keyboard (Keyboard), and the optional user interface 1003 may also include a standard wired interface and a wireless interface. The network interface 1004 may optionally include a standard wired interface and a wireless interface (such as a WI-FI interface). The memory 1005 may be a high-speed RAM memory, or a stable memory (non-volatile memory), such as a disk memory. The memory 1005 may also be a storage device independent of the aforementioned processor 1001.

[0051] Those skilled in the art will understand that Figure 1 The device structure shown in the figure does not constitute a limitation of the device, and may include more or less components than shown in the figure, or combine certain components, or arrange the components differently.

[0052] like Figure 1 As shown, the memory 1005 as a computer storage medium may include an operating system, a network communication module, a user interface module, and a network topology hardware verification program.

[0053] exist Figure 1 In the terminal device shown, the network interface 1004 is mainly used for data communication with the background server; the user interface 1003 is mainly used for data communication with the client (user end); the processor 1001 can be used to call the hardware operation verification program of the network topology in the memory 1005, and perform the following operations:

[0054] Calling an interface in the random network topology system to obtain target input data, where the target input data is data to be verified of the hardware;

[0055] Processing the target input data based on the algorithm graph structure and the simulated algorithm graph structure of the random network topology system to output the simulated algorithm graph structure of the target input data;

[0056] Compiling and running the simulation algorithm graph structure to obtain the simulation running result of the hardware;

[0057] The simulation operation result is compared with the actual operation result of the hardware based on the target input data to verify the operation result of the hardware.

[0058] Reference Figure 2 , Figure 2This is a flow chart of the first embodiment of the hardware operation verification method based on random network topology of the present application.

[0059] An embodiment of the present application provides a hardware operation verification method based on a random network topology. It should be noted that although the logical order is shown in the flow chart, in some cases, the steps shown or described may be performed in an order different from that shown here.

[0060] The hardware operation verification method based on random network topology of this embodiment includes the following steps:

[0061] Step S100, calling an interface in the random network topology system to obtain target input data, wherein the target input data is data to be verified of the hardware;

[0062] It should be noted that before verifying the correctness of the hardware operation results, it is necessary to know the relevant operating parameters of the hardware, input the parameters into the already constructed structure, and after a series of operations, obtain the final verification result. The operating parameters of the hardware to be tested can be external input, or they can be randomly generated based on some hardware data, such as hardware memory data.

[0063] In this embodiment, the data to be tested of the hardware is obtained by calling the interface. The interface means that the required data can be obtained from other places, and no additional calculation or input is required, or it is randomly generated. For example: in an addition operation program, if you want to implement the addition operation and get the result, you need to obtain two data to perform it, but these two data need to be obtained through the interface. In another program, which mainly generates addition data, you only need to give the interface path. In the addition program, you can call this interface path to obtain the data and perform the addition operation.

[0064] Step S200, processing the target input data based on the algorithm graph structure and the simulation algorithm graph structure of the random network topology system to output the simulation algorithm graph structure of the target input data;

[0065] It should be noted that after obtaining the hardware operating parameters, the hardware operating parameters need to be input into the constructed graph structure for calculation and processing, and the simulation algorithm graph structure corresponding to the hardware operating parameters is output.

[0066] In this embodiment, after the hardware data to be detected has been obtained by calling the interface, it is necessary to input the data to be detected into the previously constructed algorithm graph structure (ALGO graph structure) for operation processing. The operation processing is calculated according to a specific formula. After the calculation is completed, the result is obtained. After processing according to the calculated result, it is input into the constructed topological structure to obtain a simulation algorithm graph structure. For example, the hardware data to be detected has been obtained, and the data to be detected is input into the constructed topological structure. The result is calculated by the formula (W-F+2P) / S+1, where W refers to the input size of the data to be detected, F refers to the convolution kernel size of the data to be detected, P refers to the padding value size of the data to be detected, and S refers to the step size of the data to be detected. After the result is processed, it is input into the topological structure to obtain a simulation algorithm graph structure. For example, the data to be detected is conv2d (3, 12, 4, 2), where 3 is the input size W, 12 is the convolution kernel size F, 4 is the step size S, and 2 is the padding value size P. It can be calculated according to the given formula (W-F+2P) / S+1.

[0067] Step S300, compiling and running the simulation algorithm graph structure to obtain the simulation running result of the hardware;

[0068] In this embodiment, a simulation algorithm graph structure (SIM, simulation algorithm) is obtained, and the simulation algorithm graph structure needs to be compiled and run to convert the graph structure into a data form. The compilation and running is to convert a high-level language or a non-machine language into a machine language. The machine language is only divided into 0 and 1, and then the machine language is converted into a data form to output the final running result of the simulation algorithm.

[0069] Step S400, comparing the simulation operation result with the actual operation result of the hardware based on the target input data to verify the operation result of the hardware.

[0070] In this embodiment, in the process of obtaining the SIM graph structure, it is divided into two steps to execute. The first step is to directly compile and run to obtain the SIM running result, and the other step is to serialize and deserialize the SIM graph structure to obtain the test.model file, and put the test.model file on the systemC (C language system) hardware to execute, to obtain the running result of the simulated hardware, and compare the SIM running result with the simulated hardware running result. If the two results are consistent, it can be proved that there is no problem with the hardware running result. Serialization refers to converting objects into byte sequences and permanently saving them to disk. Objects must also be serialized when transmitted in the network, and deserialization refers to reading byte sequences from disk and deserializing them into objects to read out. Simply put, converting objects into byte sequences is serialization, and the process of restoring byte sequences to objects is deserialization.

[0071] The present application obtains target input data by calling an interface in a random network topology system, wherein the target input data is data to be verified for the hardware; processes the target input data based on the algorithm graph structure and the simulation algorithm graph structure of the random network topology system to output a simulation algorithm graph structure of the target input data; compiles and runs the simulation algorithm graph structure to obtain a simulation operation result of the hardware; and compares the simulation operation result with the actual operation result of the hardware based on the target input data to verify the operation result of the hardware. The present invention first obtains the data to be verified for the hardware through an interface, inputs the obtained data into the graph structure for pairwise comparison, obtains the final verification result, and realizes the verification of the correctness of the hardware operation result.

[0072] Further, refer to Figure 3 Based on the above first embodiment, a second example of the hardware operation verification method based on random network topology of the present application is proposed.

[0073] The difference between the second example of the hardware operation verification method based on random network topology of the present application and the first example is that step S200 includes:

[0074] Step S210, obtaining corresponding algorithm data based on the algorithm graph structure and the target input data;

[0075] In this embodiment, the target input data, that is, the data to be tested of the hardware, is input into the ALGO graph structure according to the constructed ALGO graph structure. The ALGO graph structure processes the data to be tested of the hardware. The output result of ALGO can be calculated based on the graph structure through the corresponding calculation formula, or the result to be tested of the hardware can be filled into the ALGO graph structure and obtained according to the connection relationship of the graph structure.

[0076] Optionally, step S210 includes:

[0077] Obtain the size, convolution kernel size, padding value size and step size corresponding to the target input data;

[0078] The algorithm data is obtained based on the algorithm graph structure, size, convolution kernel size, padding value size and step size.

[0079] It should be noted that the target input data obtained through the interface is calculated according to the formula (W-F+2P) / S+1, where W refers to the size of the target input data, F refers to the convolution kernel size of the target input data, P refers to the padding value size of the target input data, S refers to the step size of the target input data, and the connection relationship, layer relationship, topological relationship, etc. between the operators in the ALGO graph structure to calculate the output result of ALGO.

[0080] Step S220, converting the algorithm data into digital data;

[0081] In this embodiment, after obtaining the ALGO output data, the obtained ALGO output data is a continuous signal, and the ALGO output data needs to be quantized and converted into a digital signal to obtain the quantized data, wherein quantization refers to converting high-precision operations into low-precision operations, for example: converting 32-bit floating-point data into 8-bit unsigned integer data.

[0082] Step S230, based on the digital data, input it into the algorithm graph structure to obtain a simulation algorithm graph structure.

[0083] In this embodiment, according to the data obtained after quantization, the quantized data is input into the topological structure as the original input data, and the graphParameters structure (graphParameters, graph parameters) is used to store all the relevant information of the composition, such as: all the data related to the composition, the topological relationship, the OP hierarchical relationship, the input and output layers, the index and other information. The graphParameters structure records the information of each layer in the composition process, the intermediate layer information and the output layer information. The information of each layer will record the processed layer index. When the operator is switched, the layer of the next operator will be superimposed on each layer information and still record the layer. The original input data is the input data of the first layer, and the input data of the next layer is the output data of the previous layer. The calculation is carried out in sequence, and the SIM graph structure is finally constructed. The structure refers to a data collection similar to the form of a business card. We understand it as a special composite "data type" defined by the user. This composite "data type" can contain multiple basic data types and can be operated as a whole.

[0084] In this embodiment, firstly, according to the constructed ALGO graph structure and the hardware data to be tested obtained through the interface, the data to be tested is processed to obtain ALGO data, and then the SIM graph structure is obtained after quantifying the ALGO data. When comparing the hardware operation results later, it can be ensured that there is no problem with the SIM.

[0085] Further, refer to Figure 4 Based on the above-mentioned first and second embodiments, a third example of the hardware operation verification method based on random network topology of the present application is proposed.

[0086] The third example of the hardware operation verification method based on random network topology of the present application is different from the first and second embodiments in that, before step S210, it further includes:

[0087] Step S110, obtaining data types, topological structures and neural network calculation basic unit operators, and determining connection relationships between neural network calculation basic unit operators based on the neural network calculation basic unit operators;

[0088] In this embodiment, firstly, a data structure is randomly obtained. There are mainly two types of data structures here: FP and Q8. FP refers to 32-bit floating point data, and Q8 refers to 8-bit unsigned integer data. Then, a topological structure is randomly selected. The topological structures here are divided into three types: linear structure, that is, single-input single-output structure, double-input single-output structure, and single-input double-output structure. Then, three OP operators are randomly selected. The three OP operators are selected because only three types are currently supported, but they will be increased later. The size of the parameter data is randomly obtained according to the OP operator, and the size of each parameter data is determined according to the size of the randomly obtained parameter data. After selecting the OP operator, there is another step to verify the selected topological structure with the selected OP operator. If the verification passes, the OP operator is determined. If the verification fails, it is continuously selected until the selected topological structure can be filled. The parameter data size refers to the ih, iw and ic required for randomly generating OP, that is, the length, width and height of the data, or the size of the data, where ih refers to the height of the input OP, iw refers to the width of the input OP, and ic refers to the pipeline required for the input OP. It also determines the connection relationship between the OP operators.

[0089] Optionally, refer to Figure 5 , step S110 includes:

[0090] Step S111, based on the topological structure, marking the in-degree of each neural network calculation basic unit node, and storing it in the in-degree array;

[0091] According to the selected topology, mark the in-degree of each OP node, and store this in-degree in an array. Mark the three topologies to distinguish which topology it is. This will facilitate the determination of the shape size relationship later. Different algorithms are used to calculate the size of the node data, thereby determining the shape size relationship. In the process of marking the topology, the topology is regarded as a directed acyclic graph, which is distinguished according to the dependency relationship between the three OP nodes in the topology. An array is used to store the in-degree of each node, where the in-degree only considers the connection relationship between the three OPs, and does not consider input data, parameter data, etc. For example: in a single-input single-output topology, if the in-degree of node 1 is 0, the in-degree of nodes 2 and 3 is 1.

[0092] Step S112, determining the size of the initial node data based on the neural network calculation basic unit operator;

[0093] According to the obtained parameter data size, the initial node data size is determined. The initial node data size is calculated according to the formula N=(W-F+2P) / S+1. When the parameter data size is randomly generated, the height and width are required to be within 2 to the 16th power, that is, within 128. Because the larger the data, the slower the running speed, the pipeline c is required to be a multiple of 64. For example: in a single-input and single-output topology, the parameter data size of node 1 is: h=4, w=5, c=6. The input parameter data size refers to the size of the input data, that is, the width w, height h, and pipeline c of the input data. The node data size of node 1 is obtained, which is also the input data of node 2. According to the parameter data size, that is, the input data is obtained by multiplying the input h, w, and c randomly generated by the first OP operator.

[0094] Optionally, step S112 includes:

[0095] Calculate the basic unit operator based on the neural network to obtain the corresponding parameter data size;

[0096] Based on the size of the parameter data, the corresponding size, convolution kernel size, padding value size and step size are obtained to calculate the initial node size.

[0097] In this embodiment, after the OP operator is randomly selected, the parameter data size is randomly generated according to the selected OP operator, wherein the parameter data size includes the size, the convolution kernel size, the padding value size and the step size. The size is obtained by multiplying h (height), w (width) and c (pipeline). The initial node size is calculated according to the formula (W-F+2P) / S+1.

[0098] Step S113, based on the in-degree array and the size of the initial node data, determining the connection relationship between the neural network calculation basic units.

[0099] In determining the shape size relationship, the data scale is calculated based on the in-degree array of the topological relationship. The data scale here is the size of the node data. That is, first determine the data of the randomly generated node 1 and calculate its output data size. Then, according to different topological structures, different calculation methods are used to obtain the input data of node 2, and then the input data of node 3 is obtained. When calculating the input data of node 2, if the topological structure is double-input and single-output, the input data of node 2 needs to be reversely calculated from the output data of node 1. For example: in a single-input and single-output topological structure, the operator is a pooling operator, the input data of node 1 is h=4, w=5, c=6, and the pooling algorithm is used to obtain the output data of node 1, that is, the data size of node 1. There are three data sizes: oh (output height), ow (output width), and oc (output pipe). These three data are also the input data of node 2. By calculating in this way, the shape relationship is obtained. Here, the shape relationship refers to the connection relationship between each OP operator node.

[0100] The in-degree of the topological relationship is recorded. First, the topological relationship is regarded as a directed acyclic graph. According to the dependency relationship between OP nodes in the topological relationship, the in-degree of each node is recorded in an array. Here, only the connection relationship between OPs is considered. For example, in a single-input single-output structure, the in-degree of node 1 is 0, and the in-degree of nodes 2 and 3 is 1.

[0101] Step S120, generating an algorithm graph structure based on the connection relationship, topological structure and data type.

[0102] In this embodiment, the selected data structure and topological structure are used to initialize the index of the graphParameters structure (graphParameters, graph parameters), that is, the OP being processed, the input flag, and the output flag. There are two types of data structures: FP (32-bit floating-point data) and Q8 (8-bit unsigned integer), and there are three types of topological structures: single input and single output, double input and single output, and single input and double output. The graphParameters structure is initialized because there will be various kinds of information in the graphParameters structure. Initialization is performed to ensure that when calculating the composition data, the data stored in the graphParameters structure is not mixed with other data.

[0103] After initializing the graphParameters structure, combine the connection relationship with the graphParameters structure to generate the ALGO graph structure. The graphParameters structure is needed because the number of layers between OPs is inconsistent, the layers in the topology are in ascending order, and the input of the next OP node needs to use the output of the previous OP node. Therefore, the graphParameters structure is needed to record each layer information and intermediate layer output information in the calculation process. Therefore, no matter which topology structure is used, each layer information will record all processed layer indexes. When switching OP, the next OP's layer will be accumulated based on each layer information. Each layer information will continue to record the layer, and the intermediate layer output information will record the output of each OP.

[0104] This embodiment randomly obtains the topological structure, data type and OP operator, determines the connection relationship between each OP according to the selected OP operator, inputs the determined connection relationship and data type between the OPs into the selected topological structure and generates the ALGO graph structure therefrom, selects the topological structure and inputs data into it to generate the graph structure, realizes the universality of the topological structure, does not need to manually construct the topological structure, and saves time and effort.

[0105] Further, refer to Figure 6 Based on the above-mentioned first embodiment, second embodiment and third embodiment, a fourth example of the hardware operation verification method based on random network topology of the present application is proposed.

[0106] The fourth embodiment of the hardware operation verification method based on random network topology of the present application is different from the first embodiment, the second embodiment and the third embodiment in that step S300 includes:

[0107] Step S310, compiling the simulation algorithm graph structure to obtain a corresponding machine language;

[0108] In this embodiment, the constructed SIM graph structure is compiled and run. The so-called compilation and running is a process of converting a high-level language or a program language into a language that it can recognize, that is, a machine language.

[0109] Step S320, based on the machine language, a base conversion method is used to obtain a simulation operation result;

[0110] In this embodiment, after conversion into machine language, the machine language is composed of 0 and 1, which is binary after conversion, and then converted into decimal to become the corresponding operation result, and the SIM operation result is obtained and compared with the ALGO data. If the difference between the SIM operation result and the ALGO data is less than 16, it can be guaranteed that the SIM is correct and the SIM operation result is obtained.

[0111] Optionally, after step S300, the following steps are included:

[0112] Comparing the simulation operation result and the algorithm data to obtain a difference between the simulation operation result and the algorithm data;

[0113] When the difference is less than or equal to a preset threshold, the comparison between the simulation operation result and the actual operation result of the hardware based on the target input data is performed to verify the operation result of the hardware.

[0114] In this embodiment, after obtaining the SIM operation result and ALGO data, the two data are compared by difference. If the result is less than the preset value, it can be guaranteed that there is no problem with the SIM. Under the condition that there is no problem with the SIM, and after the SIM graph structure is constructed by the contractor, the SIM graph structure is serialized and deserialized to obtain a test.model file obtained from the SIM graph structure. The obtained file is run on the systemC hardware, wherein systemC refers to the C language system, which is a hardware operation program, to obtain the operation result of the simulated hardware, and compare the SIM operation result with the operation result of the simulated hardware. If the difference result between the two is equal to 0, that is, the operation results of the two are consistent, it can be verified that the hardware operation result is correct. If they are inconsistent, it means that the hardware operation result is inconsistent.

[0115] In this embodiment, the output results are composed of two parts, a single network topology output result and a summary of multiple random network topology output results. First, check whether the configuration in the configuration file is correct, ensure that data download is turned on, and data loading is turned off (to ensure that the random network functions normally and the data can be saved). If it is incorrect, the script will automatically modify it to the correct configuration. Start the random network process, and check whether the process exists in real time. If it does not exist, it means that the random network processing is completed. Collect relevant information from the single network topology output result file and output it to the summary file. If the output file cannot be detected, it means that the program exits abnormally, record the abnormal information, and repeat the above steps until the specified number of times is completed.

[0116] In this embodiment, after ensuring that there is no problem with the SIM through ALGO data and SIM operation results, the SIM operation results are compared with the comparison results of the simulated hardware to obtain the final verification results of the hardware operation results. First, it is determined that there is no error in the SIM operation results, and then the simulated hardware operation results are compared to ensure the accuracy of the hardware operation results.

[0117] In addition, an embodiment of the present invention further provides a computer-readable storage medium having a random network topology verification program stored thereon, which implements the steps of the random network topology verification method in any of the above embodiments when executed by a processor.

[0118] The specific implementation of the computer-readable storage medium of the present invention is basically the same as the above-mentioned embodiments of the random network topology verification method, and will not be repeated here.

[0119] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) as described above, and includes a number of instructions for a terminal device (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods described in each embodiment of the present invention.

[0120] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0121] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0122] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0123] It should be noted that in the claims, any reference signs placed between brackets shall not be construed as limiting the claims. The word "comprising" does not exclude the presence of components or steps not listed in the claim. The word "a" or "an" preceding a component does not exclude the presence of a plurality of such components. The invention may be implemented by means of hardware comprising several different components and by means of a suitably programmed computer. In a unit claim enumerating several means, several of these means may be embodied by the same item of hardware. The use of the words first, second, and third etc. does not indicate any order. These words may be interpreted as names.

[0124] Although the preferred embodiments of the present invention have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0125] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A hardware operation verification method based on random network topology, characterized in that: The steps of the hardware operation verification method based on random network topology include: Calling an interface in the random network topology system to obtain target input data, where the target input data is data to be verified of the hardware; Obtain the size, convolution kernel size, padding value size and step size corresponding to the target input data; Based on the algorithm graph structure, size, convolution kernel size, padding value size and step size of the random network topology system, the algorithm data is obtained, wherein the algorithm data is the output result of the algorithm graph structure; Converting the algorithm data into digital data, wherein the algorithm data is high-precision data and the digital data is low-precision data; Inputting the digital data into the algorithm graph structure to obtain a simulation algorithm graph structure of the target input data; Compiling and running the simulation algorithm graph structure of the target input data to obtain the simulation running result of the hardware; The simulation operation result is compared with the actual operation result of the hardware based on the target input data to verify the operation result of the hardware.

2. The hardware operation verification method based on random network topology as claimed in claim 1, characterized in that: The step of compiling and running the simulation algorithm graph structure to obtain the simulation running result of the hardware includes: Compiling the simulation algorithm graph structure to obtain a corresponding machine language; Based on the machine language, a base conversion method is used to obtain simulation operation results.

3. The hardware operation verification method based on random network topology as claimed in claim 1, characterized in that: After the step of compiling and running the simulation algorithm graph structure to obtain the simulation running result of the hardware, the method further includes: Comparing the simulation operation result and the algorithm data to obtain a difference between the simulation operation result and the algorithm data; When the difference is less than or equal to a preset threshold, the comparison between the simulation operation result and the actual operation result of the hardware based on the target input data is performed to verify the operation result of the hardware.

4. The hardware operation verification method based on random network topology as claimed in claim 1, characterized in that: Before the step of obtaining the algorithm data based on the algorithm graph structure and the target input data, the step further includes: Acquire data types, topological structures, and neural network computing basic unit operators, and determine connection relationships between neural network computing basic unit operators based on the neural network computing basic unit operators; Based on the connection relationship, topological structure and data type, an algorithm graph structure is generated.

5. According to the hardware operation verification method based on random network topology as claimed in claim 4, the step of determining the connection relationship between the neural network calculation basic unit operators based on the neural network calculation basic unit operators comprises: Based on the topological structure, mark the in-degree of each basic unit node of the neural network calculation and store it in an in-degree array; Determine the size of the initial node data based on the neural network calculation basic unit operator; Based on the in-degree array and the size of the initial node data, the connection relationship between the neural network calculation basic units is determined.

6. The hardware operation verification method based on random network topology as claimed in claim 5, characterized in that: The step of determining the size of the initial node data volume based on the neural network calculation basic unit operator comprises: Calculate the basic unit operator based on the neural network to obtain the corresponding parameter data size; Based on the size of the parameter data, the corresponding size, convolution kernel size, padding value size and step size are obtained to calculate the initial node size.

7. A hardware operation verification device based on random network topology, characterized in that: The hardware operation verification device based on random network topology includes: a memory, a processor, and a hardware operation verification program based on random network topology stored in the memory and running on the processor. When the hardware operation verification program based on random network topology is executed by the processor, the steps of the hardware operation verification method based on random network topology as described in any one of claims 1 to 6 are implemented.

8. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a hardware operation verification program based on random network topology, and when the hardware operation verification program based on random network topology is executed by a processor, the steps of hardware operation verification based on random network topology as described in any one of claims 1 to 6 are implemented.

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