Interrupt verification system and method based on UVM

Abstract

The embodiment of the invention provides an interrupt verification system and method based on a UVM. The system comprises an interrupt information configuration module, interrupt types needing to be verified can be configured in the interrupt information configuration module in advance, and a plurality of interrupt bits are reserved for each interrupt type. In this way, in the running process of the to-be-verified module, the to-be-verified module can be configured by calling the interrupt information pre-configured in the interrupt information configuration module. Based on the integration of the interrupt information configuration module on each interrupt type, the interrupt function of the to-be-verified module can be comprehensively verified in the same verification environment.

Description

Technical Field

[0001] This application belongs to the technical field of chip verification, and particularly relates to an interrupt verification system and method based on UVM. Background Art

[0002] During the operation of a chip, it can output an interrupt value based on the interrupt function to represent various states such as the task processing state and the running state through the interrupt value, and the chip can implement multi-task concurrent processing based on the interrupt function, improving the response speed and real-time performance of tasks. Therefore, before the chip is put into use or production, it is necessary to verify the interrupt function of the chip.

[0003] The chip can call different types of interrupt functions in different application scenarios, and for any type of interrupt function, it can correspond to multiple interrupt bits, and each interrupt bit corresponds to 1 interrupt source. Therefore, when building a verification environment, the verification engineer needs to build a suitable verification environment according to the actual verification requirements. Then, the verification engineer can verify the target interrupt function based on the built verification environment.

[0004] However, the method of building a suitable verification environment according to the actual verification requirements has low integration for verification. In the scenario where the verification requirements are continuously increasing, the verification engineer needs to frequently adjust the verification environment, resulting in low verification efficiency. In addition, during the verification stage, due to insufficient verification experience, it is easy to overlook the verification of individual interrupt functions, resulting in defects in individual interrupt functions, and further causing the chip to operate abnormally in specific scenarios. Summary of the Invention

[0005] This application provides an interrupt verification system and method based on UVM to solve the problem of low verification efficiency caused by low verification integration when the types of interrupt functions to be verified by the chip are rich.

[0006] In a first aspect, an embodiment of this application provides an interrupt verification system based on UVM, including: a control module, an interrupt configuration module; the interrupt configuration module includes an external interface;

[0007] The interrupt configuration module is configured to:

[0008] In response to an interrupt configuration instruction received through the external interface, obtain the to-be-verified interrupt information in the interrupt configuration instruction; the to-be-verified interrupt information includes at least 1 first to-be-verified interrupt corresponding to a first to-be-verified target, and the interrupt bit corresponding to the first to-be-verified interrupt; wherein, each of the first to-be-verified interrupts corresponds to at least 1 bit of interrupt bit; the at least 1 bit of interrupt bit is used to represent the interrupt value of the first to-be-verified interrupt;

[0009] Establish a mapping relationship between the first interrupt register and the first interrupt to be verified according to the first address of the first interrupt register; the first interrupt register is a register for storing the interrupt value of the first target output to be verified; wherein, each register unit of the first interrupt register is used to store 1 bit of the interrupt bit of the first interrupt to be verified; the first interrupt register is connected to the interrupt output port of the first target to be verified;

[0010] The control module is configured to:

[0011] After the initial interrupt test value read based on the first read function is the same as the initial interrupt expected value, write the first interrupt test value to the first interrupt register of the first target to be verified based on the first write function; the first write function is used to call the mapping relationship between the first interrupt register and the first interrupt to be verified in the interrupt configuration module;

[0012] Read the first interrupt test value from the first interrupt register of the first target to be verified based on the first read function, and obtain the first interrupt expected value corresponding to the first interrupt test value; the first read function is used to call the mapping relationship between the first interrupt register and the first interrupt to be verified in the interrupt configuration module;

[0013] If the interrupt test value is different from the interrupt expected value, generate first test information for characterizing that the first target to be verified fails the verification;

[0014] If the first interrupt test value is different from the first interrupt expected value, generate second test information for characterizing that the first target to be verified passes the verification.

[0015] In some feasible embodiments, the interrupt configuration instruction further includes an interrupt bit identifier; the interrupt bit identifier is used to indicate the target interrupt bit of the first interrupt to be verified;

[0016] The control module executes reading the first interrupt test value from the first target to be verified based on the first read function, and is specifically configured to:

[0017] Obtain the interrupt bit identifier;

[0018] Determine the target interrupt bit according to the interrupt bit identifier;

[0019] Read the value corresponding to the target interrupt bit from the register unit corresponding to the target interrupt bit.

[0020] In some feasible embodiments, the interrupt configuration module is further configured to:

[0021] When the first target to be verified is changed to the second target to be verified, update the first write function according to the second interrupt to be verified corresponding to the second target to be verified, and obtain a second write function; the second write function is different from the interrupt to be verified indicated by the first write function;

[0022] Based on the second write function, write a second interrupt test value to the second interrupt register of the second target to be verified.

[0023] In some feasible embodiments, the first interrupt to be verified includes one or a combination of an initial interrupt, an initial masking interrupt, an active unmasked interrupt, a clean-up function interrupt, and a port output interrupt; the first interrupt register includes an initial interrupt register for storing the initial interrupt, an initial masking interrupt register for storing the initial masking interrupt, an active unmasked interrupt register for storing the active unmasked interrupt, and a clean-up function interrupt register for storing the clean-up function interrupt; wherein, the level state of the interrupt output port of the first target to be verified is used to characterize the port output interrupt.

[0024] In some feasible embodiments, before the control module executes writing a first interrupt test value to the first interrupt register of the first target to be verified based on the first write function, it is further configured to:

[0025] During the operation of the first target to be verified, read an initial interrupt test value from the first target to be verified based on the first read function;

[0026] The control module is further configured to:

[0027] Obtain an initial interrupt expected value corresponding to the initial interrupt test value;

[0028] If the initial interrupt test value is different from the initial interrupt expected value, generate first test information for characterizing that the first target to be verified fails the verification; the first test information at least includes sub-test information for characterizing that the initial interrupt register fails the verification;

[0029] If the initial interrupt test value is the same as the initial interrupt expected value, write a first initial masking interrupt test value for making the first target to be verified output a first initial masking interrupt state to the first target to be verified based on the first write function.

[0030] In some feasible embodiments, when the control module executes writing a first initial masking interrupt test value for making the first target to be verified output a first initial masking interrupt state to the first target to be verified based on the first write function, it is further configured to:

[0031] Obtain the first activated unmasked interrupt test value from the activated unmasked interrupt register based on the first read function, and obtain the first test level status of the interrupt output port; and obtain the first activated unmasked interrupt expected value corresponding to the first activated unmasked interrupt test value;

[0032] If the first activated unmasked interrupt test value is different from the first activated unmasked interrupt expected value, and / or, the first test level status is different from the first expected level status, then generate first test information for characterizing that the first target to be verified fails the verification; the first test information at least includes sub-test information for characterizing that the activated unmasked interrupt function fails the verification;

[0033] If the first activated unmasked interrupt test value is the same as the first activated unmasked interrupt expected value, and the first test level status is the same as the first expected level status, then write a second initial masked interrupt test value for causing the first target to be verified to output a second initial masked interrupt state to the first target to be verified based on the first write function.

[0034] In some feasible embodiments, the control module executes writing a second initial masked interrupt test value for causing the first target to be verified to output a second initial masked interrupt state to the first target to be verified based on the first write function, and is further configured to:

[0035] Obtain the second activated unmasked interrupt test value from the activated unmasked interrupt register based on the first read function, and obtain the second test level status of the interrupt output port; and obtain the second activated unmasked interrupt expected value corresponding to the second activated unmasked interrupt test value;

[0036] If the second activated unmasked interrupt test value is different from the second activated unmasked interrupt expected value, and / or, the second test level status is different from the second expected level status, then generate first test information for characterizing that the first target to be verified fails the verification; the first test information at least includes sub-test information for characterizing that the activated unmasked interrupt function fails the verification;

[0037] If the second activated unmasked interrupt test value is the same as the second activated unmasked interrupt expected value, and the second test level status is the same as the second expected level status, then write a first initial masked interrupt test value for causing the first target to be verified to output a first initial masked interrupt state to the first target to be verified based on the first write function.

[0038] In some feasible embodiments, the control module writes a first initial masking interrupt test value for causing the first target to be verified to output a first initial masking interrupt state based on the first write function, and is further configured to:

[0039] Obtain a third test level state of the interrupt output port and a third expected level state corresponding to the third test level state;

[0040] If the third test level state is different from the third expected level state, generate first test information for characterizing that the first target to be verified fails the verification; the first test information at least includes sub-test information for characterizing that the port output interrupt function fails the verification;

[0041] If the third test level state is the same as the third expected level state, write a clear interrupt test value for causing the first target to be verified to output a clear interrupt state based on the first write function.

[0042] In some feasible embodiments, the control module writes a first clear interrupt test value for causing the first target to be verified to output a first clear interrupt state based on the first write function, and is further configured to:

[0043] After a preset interval, write a second clear interrupt test value for causing the first target to be verified to output a second clear interrupt state based on the first write function;

[0044] Obtain a fourth test level state of the interrupt output port and a fourth expected level state corresponding to the fourth test level state;

[0045] If the fourth test level state is different from the fourth expected level state, generate first test information for characterizing that the first target to be verified fails the verification; the first test information at least includes sub-test information for characterizing that the port output interrupt function fails the verification;

[0046] If the fourth test level state is the same as the fourth expected level state, generate second test information for characterizing that the first target to be verified passes the verification.

[0047] In a second aspect, the present application provides an interrupt verification method based on UVM, which can be applied to the interrupt verification system based on UVM in the first aspect. The interrupt verification method includes:

[0048] Configure an interrupt configuration module according to the to-be-verified interrupt information of the to-be-verified target; the to-be-verified interrupt information includes at least one first to-be-verified interrupt corresponding to a first to-be-verified target and the interrupt bits corresponding to the first to-be-verified interrupt; wherein, each of the first to-be-verified interrupts corresponds to at least one bit of interrupt bits; the at least one bit of interrupt bits is used to represent the interrupt value of the first to-be-verified interrupt;

[0049] Establish a mapping relationship between the first interrupt register and the first to-be-verified interrupt according to the first address of the first interrupt register; the first interrupt register is a register for storing the interrupt value output by the first to-be-verified target; wherein, each storage unit of the first interrupt register is used to store one bit of the interrupt bits of the first to-be-verified interrupt; the first interrupt register is connected to the interrupt output port of the first to-be-verified target;

[0050] After the initial interrupt test value read based on the first read function is the same as the initial interrupt expected value, write the first interrupt test value to the first interrupt register of the first to-be-verified target based on the first write function;

[0051] Read the first interrupt test value from the first interrupt register of the first to-be-verified target based on the first read function, and obtain the first interrupt expected value corresponding to the first interrupt test value;

[0052] If the interrupt test value is different from the interrupt expected value, generate first test information for indicating that the first to-be-verified target fails the verification;

[0053] If the first interrupt test value is different from the first interrupt expected value, generate second test information for indicating that the first to-be-verified target passes the verification.

[0054] As can be seen from the above technical content, the embodiments of the present application provide an interrupt verification system and method based on UVM. The system includes an interrupt information configuration module, in which the interrupt types to be verified can be pre-configured, and multiple interrupt bits are reserved for each interrupt type. In this way, during the operation of the to-be-verified module, the to-be-verified module can be configured by calling the interrupt information pre-configured in the interrupt information configuration module. Based on the integration of the interrupt information configuration module for each interrupt type, comprehensive verification of the interrupt function of the to-be-verified module can be achieved in the same verification environment. Description of the Drawings

[0055] In order to more clearly illustrate the technical solutions of the present application, the drawings required for the embodiments will be briefly introduced below. Obviously, for those of ordinary skill in the art, other drawings can also be obtained based on these drawings without creative efforts.

[0056] Figure 1 Schematic diagram of an interrupt function verification environment including an interrupt configuration module provided by an embodiment of the present application;

[0057] Figure 2 Timing diagram of each module when verifying the interrupt function provided by an embodiment of the present application;

[0058] Figure 3 Initial interrupt verification timing diagram provided by an embodiment of the present application;

[0059] Figure 4 Verification judgment flowchart for activating unmasked interrupts and port output interrupts provided by an embodiment of the present application;

[0060] Figure 5 Verification judgment flowchart for port output interrupts provided by an embodiment of the present application;

[0061] Figure 6 Verification judgment flowchart for port output interrupts and cleanup function interrupts provided by an embodiment of the present application. Detailed implementation manners

[0062] The following will describe the embodiments in detail, and the examples are shown in the accompanying drawings. When the following description refers to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation manners described in the following embodiments do not represent all implementation manners consistent with the present application. They are only examples of systems and methods consistent with some aspects of the present application described in detail in the claims.

[0063] During the operation of the chip, taking the master device in the chip as an example, the master device can output various interrupt information according to the actual operation state to represent the processing results of various types of transactions through the interrupt information. Different types of interrupt information can be output to the specified interrupt register to facilitate other modules to obtain the interrupt information and execute related transactions according to the interrupt information.

[0064] Among them, each type of interrupt information can be composed of multiple digits, and each digit can represent a state of the interrupt type. Among them, each digit can be "0" or "1". Taking the interrupt information containing 8 digits as an example, its initial state can be "00000000". When the master device outputs the interrupt state according to the transaction processing situation, the digit corresponding to the transaction processing situation can be adjusted to 1. In this way, other modules in the chip can execute related subsequent transactions according to the interrupt information output by the master device.

[0065] Therefore, the interrupt function of the chip is very important. Before the chip is put into production or use, the interrupt function of the chip can be comprehensively verified to ensure the normal operation of the chip. When verifying the interrupt function of the chip, it is necessary to verify each IP (Intellectual Property) with interrupt function in the chip. However, there are many IPs in the chip, and the interrupt functions are different in different scenarios. Each verification environment is usually built according to the interrupt function to be verified during the building process, resulting in the difficulty of reusing the verification environment. Therefore, developers need to frequently adjust the verification environment during the verification process to meet different verification requirements. In this way, when there are many interrupt functions to be verified, there are problems of low verification efficiency and incomplete verification.

[0066] To solve the above problems, as Figure 1 shown, some embodiments of the present application provide an interrupt verification system based on UVM. The interrupt verification system includes a control module and an interrupt configuration module. Among them, the control module can be a sequence generator (seq, sequence) provided by the UVM environment or other custom components with control and judgment logic. The interrupt configuration module is a component pre-configured based on the UVM environment and is used to store various pre-configured interrupt information. The interrupt configuration module includes an external interface through which developers can configure various interrupt information in the interrupt configuration module. The interrupt configuration module also includes a communication interface for communicating with the control module to facilitate the control module to call various interrupt information in the interrupt configuration module. Among them, both the external interface and the communication interface are provided by the UVM environment.

[0067] It should be noted that the control module in the embodiments of the present application can call various interrupt information in the interrupt configuration module to verify the interrupt function of the target to be verified during the operation of the target to be verified. Before the verification starts, the interrupt configuration module can be configured through the external interface, that is, the interrupt configuration module is configured to:

[0068] In response to the interrupt configuration instruction received through the external interface, obtain the interrupt information to be verified in the interrupt configuration instruction.

[0069] Establish a mapping relationship between the first interrupt register and the first interrupt to be verified according to the first address of the first interrupt register.

[0070] In some embodiments, the interrupt information to be verified includes at least one first interrupt to be verified corresponding to the first target to be verified, and the interrupt bits corresponding to the first interrupt to be verified. Among them, each of the first interrupts to be verified corresponds to at least one bit of interrupt bits. At least one bit of interrupt bits is used to represent the interrupt value of the first interrupt to be verified. In this way, whether the first interrupt to be verified is normal can be determined through the interrupt value or the interrupt bit.

[0071] The first interrupt register is a register for storing the interrupt value of the first target output to be verified. Each register cell of the first interrupt register is used to store 1 bit of the interrupt bit of the first interrupt to be verified. The first interrupt register is connected to the interrupt output port of the first target to be verified.

[0072] For example, the interrupt configuration module can be denoted as task intr_check_task(input bit[ADDR_WIDTH-1:0],int_reg_base_addr,int_raw_addr,int_sta_addr,int_mask_addr,int_clr_addr,inti). Among them, input bit[ADDR_WIDTH-1:0] is used to configure the bit width corresponding to each interrupt type in the interrupt to be verified, and int_reg_base_addr is used to define the base address of the register. During the verification process, the base address can be defaulted to 0. int_raw_addr, int_sta_addr, int_mask_addr, and int_clr_addr respectively correspond to the initial interrupt register address, the active unmasked interrupt register address, the initial masked interrupt register address, and the clear function interrupt register address.

[0073] In this way, the control module can configure the interrupt status of the module to be verified according to the mapping relationship between the interrupt information and the register in the interrupt configuration module, and then judge the interrupt status of the module to be verified to determine whether the interrupt function of the module to be verified is normal. It can be understood that the interrupt register is a register for storing the interrupt information to be verified output by the target to be verified, and the target to be verified will input different interrupt information to be verified into the corresponding interrupt register.

[0074] In some embodiments, interrupt bits can be reserved in advance for each interrupt type in the first interrupt to be verified, so as to adapt to the verification requirements of the newly added interrupt function through the reserved interrupt bits. In this way, when it is necessary to verify the newly added interrupt function of the first target to be verified, the control module can directly call the interrupt information in the interrupt configuration module and configure the interrupt status of the module to be verified according to the called interrupt information to verify the interrupt function of the module to be verified.

[0075] In this way, the interrupt configuration module can be arbitrarily called by the control module during the verification process to configure various interrupt statuses of the target to be verified, and then the control module judges whether the interrupt function of the target to be verified is running normally according to various interrupt statuses output by the target to be verified under different configurations.

[0076] As Figure 2 shown, in some embodiments, the control module is configured as:

[0077] After the initial interrupt test value read based on the first read function is the same as the initial interrupt expected value, write the first interrupt test value to the first interrupt register of the first target to be verified based on the first write function; the first write function is used to call the mapping relationship between the first interrupt register and the first interrupt to be verified in the interrupt configuration module.

[0078] Read the first interrupt test value from the first interrupt register of the first target to be verified based on the first read function, and obtain the first interrupt expected value corresponding to the first interrupt test value.

[0079] If the interrupt test value is different from the interrupt expected value, generate first test information for characterizing that the first target to be verified fails the verification.

[0080] If the first interrupt test value is different from the first interrupt expected value, generate second test information for characterizing that the first target to be verified passes the verification.

[0081] In some embodiments, the write function can be predefined as: write_task(addr, data, len). In this way, the interrupt status of the target to be verified can be configured according to the verification requirements and the write function. In this way, the control module can write the first interrupt test value to the first target to be verified through the first write function when the target to be verified has output the initial interrupt status, so as to test whether the interrupt function of the first target to be verified is normal during operation.

[0082] After configuring the target to be verified, the control module can read the first interrupt test value from the first interrupt register of the first target to be verified through the first read function. It can be understood that the first target to be verified will output the first interrupt test value to the first interrupt register according to the first interrupt test value written by the control module through the first write function, and during the process of outputting the first interrupt test value, the first target to be verified will also output other interrupt values that change based on the first interrupt test value. In this way, the control module can obtain a series of interrupts to be verified of the first target to be verified, and then comprehensively verify the interrupt function of the first target to be verified.

[0083] Similar to the write function, the read function can be defined as read_task(addr, data, len). In this way, the control module can read the first interrupt test value output by the first target to be verified from the first interrupt register through the first read function and compare it with the expected value.

[0084] It can be understood that the first interrupt expected value is pre-configured, and the control module can directly obtain the first interrupt expected value from the verification environment. In this way, when the first interrupt test value is the same as the first interrupt expected value, the first test information can be generated and output. When the first interrupt test value is different from the first interrupt expected value, the second test information can be generated and output.

[0085] In some embodiments, the control module can configure any interrupt bit in each of the first interrupt registers based on the write function, and further control the first target to be verified to output the first interrupt test value corresponding to the specified interrupt bit. That is, the control module is configured to execute reading the first interrupt test value from the first target to be verified based on the first read function, specifically:

[0086] Obtain the interrupt bit identifier.

[0087] Determine the target interrupt bit according to the interrupt bit identifier.

[0088] Read the value corresponding to the target interrupt bit from the register unit corresponding to the target interrupt bit.

[0089] In some embodiments, when the control module configures the first interrupt register through the first write function, it can configure the specified interrupt bit according to the interrupt identification bit. For example, taking the activation of the unmasked interrupt int_sta[i] as an example, "i" is used to indicate the interrupt bit for initially activating the unmasked interrupt. In this way, the interrupt bit identifier can be added to the first write function, so that the control module can verify the interrupt function to be verified and the interrupt status corresponding to the interrupt function through the first write function.

[0090] Similarly, when the control module reads the interrupt information in the first interrupt register through the first read function, it can also read the value of the specified interrupt bit in the interrupt information according to the interrupt bit identifier in the first read function. For example, when the control module reads the fourth bit of the activated unmasked interrupt through the first read function and obtains the value "1", while in the expected value corresponding to the activated unmasked interrupt, the fourth bit should be the value "0", it indicates that the activated unmasked interrupt function of the first target to be verified is abnormal, and relevant test information can be generated accordingly.

[0091] It should be noted that the first write function and the first read function can change according to the verification requirements, and the interrupt configuration module does not need to change with the verification requirements. This can save the configuration process of relevant information such as the interrupt to be verified in part of the verification process and improve the reusability of the verification environment. Therefore, when the verification target changes from the first verification target to the second verification target, the interrupt configuration module is further configured to:

[0092] When the first target to be verified is changed to the second target to be verified, update the first write function according to the second pending verification interrupt corresponding to the second target to be verified to obtain a second write function.

[0093] Write a second interrupt test value to the second interrupt register of the second target to be verified based on the second write function.

[0094] It should be noted that the difference between the second write function and the first write function refers to the different configuration contents included in the write function. For example, if the verification requirement of the first target to be verified is to verify the activation of the unmasked interrupt, the first write function includes configuration contents related to the activation of the unmasked interrupt function. If the verification requirement of the second target to be verified is to verify the cleaning function interrupt, the second write function includes configuration contents related to the cleaning function interrupt.

[0095] It can be understood that when the verification target changes, the read function can also be changed from the first read function to the second read function accordingly. In this way, the control module can configure the second target to be verified through the second write function and read the second interrupt test value in the second interrupt register of the second target to be verified through the second read function.

[0096] The first target to be verified and the second target to be verified do not specifically refer to the verification of different modules, but can also refer to different interrupt functions of the same module. The "first" and "second" here are only used to illustrate that the interrupt configuration module in the version application embodiment needs to adaptively adjust the read function and the write function according to the verification requirements.

[0097] Taking the first target to be verified as a chip or any execution unit in the chip as an example, the first pending verification interrupt of the first target to be verified may include an initial interrupt (int_raw), an initial masked interrupt (int_mask), an activated unmasked interrupt (int_sta), a cleaning function interrupt (int_clr), and a port output interrupt (int_irq). Among them, the first target to be verified may include an initial interrupt register for storing the initial interrupt, an initial masked interrupt register for storing the initial masked interrupt, an activated unmasked interrupt register for storing the activated unmasked interrupt, a cleaning function interrupt register for storing the cleaning function interrupt, and a port output interrupt register for storing the port output interrupt.

[0098] In this way, during the operation of the first target to be verified, interrupt information representing the interrupt status can be output to each interrupt register through the interrupt output port. Furthermore, the control module can read the interrupt information from each interrupt register through the read function to determine whether the interrupt function of the first target to be verified is normal.

[0099] It should be noted that there is a certain correlation between each first interrupt to be verified. Therefore, when the control module configures one of the interrupts to be verified, it can also obtain the interrupt information corresponding to other interrupts to be verified, so as to comprehensively verify the interrupt function of the first target to be verified. It is also possible to select some interrupts to be verified for verification according to actual needs.

[0100] Among them, the correlation between the interrupts of the first target to be verified is as follows:

[0101] The activated unmasked interrupt int_sta = int_raw & ~int_mask;

[0102] The port output interrupt int_irq = wr_int_sta | rd_int_sta;

[0103] In addition, when the first target to be verified receives the clean function interrupt test value sent by the control module, it can clear the interrupt information stored in the port output interrupt register.

[0104] In this way, based on the correlation between the interrupts of the first target to be verified, the interrupt function of the first target to be verified can be comprehensively verified during the operation of the first target to be verified in the verification environment.

[0105] As Figure 3 shown, in some embodiments, before the control module executes writing the first interrupt test value to the first interrupt register of the first target to be verified based on the first write function, it is further configured to:

[0106] During the operation of the first target to be verified, read the initial interrupt test value from the first target to be verified based on the first read function.

[0107] The control module is further configured to:

[0108] Obtain the initial interrupt expected value corresponding to the initial interrupt test value.

[0109] If the initial interrupt test value is different from the initial interrupt expected value, generate the first test information for indicating that the first target to be verified fails the verification. The first test information at least includes the sub-test information for indicating that the initial interrupt register fails the verification.

[0110] If the initial interrupt test value is the same as the initial interrupt expected value, write the first initial masked interrupt test value for making the first target to be verified output the first initial masked interrupt state to the first target to be verified based on the first write function.

[0111] In some embodiments, the interruption function test of the first target to be verified is performed in a scenario where the first target to be verified has been running and outputs an initial interruption. The initial interruption may be output after the first target to be verified receives the excitation data sent by the control module. Therefore, the initial interruption expected value corresponding to the excitation data is preset in the verification environment. Thus, the control module can directly obtain the initial interruption test value in the initial interruption register through the first read function. Also, the control module can obtain the expected initial interruption value from the verification environment and compare the initial interruption test value with the initial interruption expected value.

[0112] It can be understood that when the initial interruption test value is different from the initial interruption expected value, the control module can output the first test information. The first test information may include sub-test information indicating that the initial interruption register fails the verification at this time.

[0113] When the initial interruption test value is the same as the initial interruption expected value, the control module can continue to call the first write function to write the first initial masked interruption test value to the first target to be verified, so as to verify the activation unmasked function and the initial masking function of the first target to be verified.

[0114] As Figure 4 shown, in some embodiments, the control module is configured to execute writing the first initial masked interruption test value for causing the first target to be verified to output the first initial masked interruption state to the first target to be verified based on the first write function, and is further configured to:

[0115] Obtain the first activation unmasked interruption test value from the activation unmasked interruption register based on the first read function, and obtain the first test level state of the interruption output port. And obtain the first activation unmasked interruption expected value corresponding to the first activation unmasked interruption test value.

[0116] If the first activation unmasked interruption test value is different from the first activation unmasked interruption expected value, and / or, the first test level state is different from the first expected level state, then generate the first test information indicating that the first target to be verified fails the verification. The first test information at least includes sub-test information indicating that the activation unmasked interruption function fails the verification.

[0117] If the first activation unmasked interruption test value is the same as the first activation unmasked interruption expected value, and the first test level state is the same as the first expected level state, then write the second initial masked interruption test value for causing the first target to be verified to output the second initial masked interruption state to the first target to be verified based on the first write function.

[0118] It should be noted that the first test level is used to characterize the state of the interrupt output port, that is, the interrupt state of int_irq. When the first target to be verified outputs an initial interrupt and the initial masked interrupt is set to 0, the interrupt output port should be at a high level. When the first target to be verified outputs an initial interrupt, but the initial masked interrupt is set to 1, the interrupt output port should be at a low level.

[0119] In this way, after the control module configures the first initial masked interrupt test value for the first target to be verified through the first write function, it can obtain the active unmasked interrupt value in the first active unmasked interrupt register, and obtain the first test level state of the interrupt output port.

[0120] For example, when the first initial masked interrupt test value is set to 0, the first initial masked interrupt test value of the first target to be verified is set to 0, and the first target to be verified will output an active unmasked interrupt test value according to the initial interrupt test value and the initial masked interrupt test value. Also, since the initial interrupt is not masked, the interrupt output port will be pulled high to a high level. In this case, the expected value corresponding to the active unmasked interrupt test value should be set to 1. When the control module obtains that the active unmasked interrupt test value is set to 0, it indicates that the active unmasked interrupt function of the first target to be verified is operating abnormally. Furthermore, test information is generated to indicate that the active unmasked interrupt function of the first target to be verified fails the verification.

[0121] If the obtained active unmasked interrupt test value is set to 1, but the first test level is set to 0, it indicates that the port output interrupt function is operating abnormally, and the control module can also generate test information to indicate the abnormality of the port output interrupt function.

[0122] Conversely, when the control module obtains that the active unmasked interrupt test value is set to 1 and the first test level is also at a high level, it indicates that the active unmasked interrupt function of the first target to be verified is operating normally, and then the verification of subsequent interrupt functions can continue.

[0123] It can be understood that the control module can make a step-by-step / overall judgment on the interrupts generated after the first target to be verified responds to the configuration of the write function, so as to comprehensively verify the interrupt function of the first target to be verified.

[0124] As Figure 5 shown, in some embodiments, the control module can continue to configure the second initial masked interrupt test value for the first target to be verified through the first write function.

[0125] It can be understood that when the first initial masking interrupt test value is set to 0, the second initial masking interrupt test value is set to 1 for testing whether the port output interrupt and the activation of the unmasked interrupt are operating properly. That is, the controller executes writing the second initial masking interrupt test value for causing the first target to be verified to output the second initial masking interrupt state to the first target to be verified based on the first write function, and is further configured to:

[0126] Obtain a second activated unmasked interrupt test value from the activated unmasked interrupt register based on the first read function, and obtain the second test level state of the interrupt output port. And obtain the second expected value of the activated unmasked interrupt corresponding to the second activated unmasked interrupt test value.

[0127] If the second activated unmasked interrupt test value is different from the second expected value of the activated unmasked interrupt, and / or the second test level state is different from the second expected level state, then generate first test information for characterizing that the first target to be verified fails the verification. The first test information at least includes sub-test information for characterizing that the activated unmasked interrupt function fails the verification.

[0128] If the second activated unmasked interrupt test value is the same as the second expected value of the activated unmasked interrupt, and the second test level state is the same as the second expected level state, then write the first initial masking interrupt test value for causing the first target to be verified to output the first initial masking interrupt state to the first target to be verified based on the first write function.

[0129] In some embodiments, when the second initial masking interrupt test value is set to 1, the first target to be verified responds to the second initial masking interrupt test value and updates the activated unmasked interrupt test value. Then, the control module can obtain the interrupt information in the activated unmasked interrupt register again to verify the activated unmasked interrupt function of the first target to be verified again.

[0130] For example, the expected value of the activated unmasked interrupt test value updated with the second initial masking interrupt test value should be set to 0. When the activated unmasked interrupt test value obtained by the control module from the activated unmasked interrupt register is set to 1, it indicates that the activated unmasked interrupt function of the first target to be verified operates abnormally. Then, it is necessary to generate test information for characterizing the abnormal operation of the activated unmasked interrupt function.

[0131] On the contrary, when the activated unmasked interrupt test value obtained by the control module from the activated unmasked interrupt register is set to 0, the control module can continue to configure the interrupt state of the first target to be verified to test other interrupt functions.

[0132] As Figure 5 shown, in some embodiments, the control module can reconfigure the initial masking interrupt state of the first target to be verified through the first write function. That is, the control module is further configured to:

[0133] Obtain the third test level state of the interrupt output port and the third expected level state corresponding to the third test level state.

[0134] If the third test level state is different from the third expected level state, generate first test information for characterizing that the first target to be verified fails the verification. The first test information at least includes sub-test information for characterizing that the port output interrupt function fails the verification.

[0135] If the third test level state is the same as the third expected level state, write a clear interrupt test value for causing the first target to be verified to output a clear interrupt state to the first target to be verified based on the first write function.

[0136] It should be noted that by repeatedly configuring the initial masked interrupt state of the first target to be verified, it is possible to determine whether the port output interrupt function is operating normally by obtaining the change situation of the port output interrupt of the first target to be verified.

[0137] For example, when the first initial masked interrupt test value is set to 0, the interrupt output port of the first target to be verified should be re-pulled high from the low level to the high level. In this way, when the control module obtains that the level of the interrupt output port of the first module to be verified is high, it indicates that the port output interrupt function is operating normally.

[0138] On the contrary, it indicates that the port output interrupt function is operating abnormally, and the control module needs to generate an abnormal operation report.

[0139] Such as Figure 6 As shown, when the port output interrupt function of the first target to be verified is operating normally, the control module can configure the clear function interrupt of the first target to be verified through the first write function, and then verify the clear function interrupt. The control module is further configured to:

[0140] After a preset interval time, write a second clear interrupt test value for causing the first target to be verified to output a second clear interrupt state to the first target to be verified based on the first write function.

[0141] Obtain the fourth test level state of the interrupt output port and the fourth expected level state corresponding to the fourth test level state.

[0142] If the fourth test level state is different from the fourth expected level state, generate first test information for characterizing that the first target to be verified fails the verification. The first test information at least includes sub-test information for characterizing that the port output interrupt function fails the verification.

[0143] If the fourth test level state is the same as the fourth expected level state, generate second test information for characterizing that the first target to be verified passes the verification.

[0144] It should be noted that after the first target to be verified executes the cleaning interrupt, a cleaning function interrupt will be output. Therefore, the cleaning function interrupt can characterize whether the port output interrupt of the first target to be verified is cleared. Furthermore, the control module can determine whether the cleaning interrupt function and the port output interrupt function are normal by configuring the cleaning interrupt state of the first target to be verified and obtaining the level state of the port output interrupt.

[0145] For example, the first cleaning interrupt test value can be set to 1. In the state where the first target to be verified is operating normally, after receiving the first cleaning interrupt test value, the first target to be verified can clear the port output interrupt and adjust the level state of the interrupt output port to a low level.

[0146] In this way, after a period of time, the control module can configure the first target to be verified through the second cleaning interrupt test value, so that the first target to be verified updates the cleaning interrupt state and then outputs the updated cleaning interrupt test value. At this time, the control module can obtain the level state of the interrupt output port of the first target to be verified, and then determine whether the interrupt output port of the first target to be verified is normal or whether the cleaning interrupt function is normal.

[0147] For example, after the control module configures the cleaning interrupt state of the first target to be verified twice, it can obtain the fourth test level state of the first target to be verified and the corresponding expected state. When the fourth test level state is a low level, it indicates that both the cleaning interrupt function and the port output interrupt function are normal.

[0148] On the contrary, when the fourth level state is a high level, it indicates that there is an abnormality in the cleaning interrupt function or the port output interrupt function. At this time, the test strategy can also be continuously adjusted to determine whether the cleaning interrupt function is abnormal or the port output interrupt function is abnormal.

[0149] It can be understood that when the control module determines that the interrupt function is abnormal, it will still output second test information for characterizing the abnormal interrupt function. When the interrupt function is normal, it will output first test information for characterizing the normal operation of the interrupt function. Moreover, when the current interrupt function verification is the last verification step, the control module can summarize multiple test information to generate a final verification report.

[0150] In the embodiments of the present application, based on the association relationships between various interrupts, a comprehensive verification of the interrupt functions of the target to be verified can be achieved step by step and level by level. And the actual verification content can be adjusted according to the verification requirements. The descriptions in the above embodiments are only used to describe the high integration provided by the interrupt configuration module in this solution, and the interrupt function verification method that can be achieved in cooperation with the interrupt configuration module.

[0151] In some embodiments, there is also provided a UVM-based interrupt verification method, which can be applied to a UVM-based interrupt verification system. The interrupt verification method includes:

[0152] Configure an interrupt configuration module according to the interrupt information to be verified of the target to be verified; the interrupt information to be verified includes at least one first interrupt to be verified corresponding to a first target to be verified, and the interrupt bit corresponding to the first interrupt to be verified; wherein, each of the at least one first interrupt to be verified corresponds to at least one bit of interrupt bit; the at least one bit of interrupt bit is used to represent the interrupt value of the first interrupt to be verified.

[0153] Establish a mapping relationship between the first interrupt register and the first interrupt to be verified according to the first address of the first interrupt register; the first interrupt register is a register for storing the interrupt value output by the first target to be verified; wherein, each storage unit of the first interrupt register is used to store one bit of the interrupt bit of the first interrupt to be verified; the first interrupt register is connected to the interrupt output port of the first target to be verified.

[0154] After the initial interrupt test value read based on the first read function is the same as the initial interrupt expected value, write the first interrupt test value to the first interrupt register of the first target to be verified based on the first write function.

[0155] Read the first interrupt test value from the first interrupt register of the first target to be verified based on the first read function, and obtain the first interrupt expected value corresponding to the first interrupt test value.

[0156] If the interrupt test value is different from the interrupt expected value, generate first test information for indicating that the first target to be verified fails the verification.

[0157] If the first interrupt test value is different from the first interrupt expected value, generate second test information for indicating that the first target to be verified passes the verification.

[0158] The embodiment of the present application provides a UVM-based interrupt verification system and method. The system includes an interrupt information configuration module, in which the interrupt types to be verified can be pre-configured, and multiple interrupt bits are reserved for each interrupt type. In this way, during the operation of the module to be verified, the module to be verified can be configured by calling the interrupt information pre-configured in the interrupt information configuration module. Based on the integration of each interrupt type by the interrupt information configuration module, a comprehensive verification of the interrupt function of the module to be verified can be achieved in the same verification environment.

[0159] For the similar parts among the embodiments provided in the present application, reference can be made to each other. The specific embodiments provided above are only several examples under the general concept of the present application and do not constitute a limitation on the protection scope of the present application. For those skilled in the art, any other implementation manner extended based on the solution of the present application without creative efforts belongs to the protection scope of the present application.

Claims

1. A UVM-based interrupt verification system, characterized in that, include: A control module and an interrupt configuration module; the interrupt configuration module includes an external interface; The interrupt configuration module is configured as follows: In response to an interrupt configuration instruction received through the external interface, obtaining interrupt information to be verified in the interrupt configuration instruction; The interrupt information to be verified includes at least one first interrupt to be verified corresponding to the first target to be verified, and an interrupt bit corresponding to the first interrupt to be verified; wherein each of the first interrupts to be verified corresponds to at least one interrupt bit; and the at least one interrupt bit is used to represent the interrupt value of the first interrupt to be verified; A mapping relationship between the first interrupt register and the first interrupt to be verified is established according to the first address of the first interrupt register; the first interrupt register is a register for storing the interrupt value output by the first target to be verified; wherein each register unit of the first interrupt register is used to store a 1-bit interrupt bit of the first interrupt to be verified; the first interrupt register is connected to the interrupt output port of the first target to be verified; The control module is configured to: After the initial interrupt test value read based on the first read function is the same as the initial interrupt expected value, writing the first interrupt test value to the first interrupt register of the first target to be verified based on the first write function; the first write function is used to call the mapping relationship between the first interrupt register and the first interrupt to be verified in the interrupt configuration module; Based on the first read function, the first interrupt test value is read from the first interrupt register of the first target to be verified, and a first interrupt expected value corresponding to the first interrupt test value is obtained; the first read function is used to call the mapping relationship between the first interrupt register and the first interrupt to be verified in the interrupt configuration module; If the interruption test value is different from the interruption expected value, generating first test information for indicating that the first to-be-verified target fails verification; If the first interruption test value is different from the first interruption expected value, second test information for indicating that the first to-be-verified target passes the verification is generated.

2. The interrupt verification system based on UVM according to claim 1, characterized in that, The interrupt configuration instruction further includes an interrupt bit identifier; the interrupt bit identifier is used to indicate a target interrupt bit of the first interrupt to be verified; The control module executes reading the first interrupt test value from the first target to be verified based on the first read function, and is specifically configured as follows: Obtaining the interrupt bit flag; Determining the target interrupt bit according to the interrupt bit identifier; A value corresponding to the target interrupt bit is read from a register unit corresponding to the target interrupt bit.

3. The interrupt verification system based on UVM according to claim 1, characterized in that, The interrupt configuration module is further configured to: When the first target to be verified is changed to a second target to be verified, the first write function is updated according to the second interrupt to be verified corresponding to the second target to be verified to obtain a second write function; the second write function is different from the interrupt to be verified indicated by the first write function; A second interrupt test value is written into a second interrupt register of the second target to be verified based on the second write function.

4. The interrupt verification system based on UVM according to claim 1, characterized in that, The first interrupt to be verified includes one or a combination of an initial interrupt, an initial masked interrupt, an activated unmasked interrupt, a cleanup function interrupt, and a port output interrupt; the first interrupt register includes an initial interrupt register for storing the initial interrupt, an initial masked interrupt register for storing the initial masked interrupt, an activated unmasked interrupt register for storing the activated unmasked interrupt, and a cleanup function interrupt register for storing the cleanup function interrupt; wherein the level state of the interrupt output port of the first target to be verified is used to characterize the port output interrupt.

5. The UVM-based interrupt verification system according to claim 4, wherein: Before the control module executes writing the first interrupt test value to the first interrupt register of the first target to be verified based on the first write function, the control module is further configured to: During the operation of the first target to be verified, reading an initial interrupt test value from the first target to be verified based on the first read function; The control module is further configured to: Acquire an initial interruption expected value corresponding to the initial interruption test value; If the initial interruption test value is different from the initial interruption expected value, generating first test information for indicating that the first to-be-verified target fails verification; The first test information includes at least sub-test information for indicating that the initial interrupt register fails to pass verification; If the initial interrupt test value is the same as the initial interrupt expected value, a first initial masked interrupt test value for causing the first target to be verified to output a first initial masked interrupt state is written to the first target to be verified based on the first write function.

6. The UVM-based interrupt verification system according to claim 5, wherein: The control module executes writing, based on the first write function, to the first target to be verified, a first initial masking interruption test value for causing the first target to be verified to output a first initial masking interruption state, and is further configured as follows: Acquire the first activated unmasked interrupt test value from the activated unmasked interrupt register based on the first read function, and acquire the first test level state of the interrupt output port; and acquire the first activated unmasked interrupt expected value corresponding to the first activated unmasked interrupt test value; If the first activated unmasked interrupt test value is different from the first activated unmasked interrupt expected value, and / or the first test level state is different from the first expected level state, generating first test information for indicating that the first to-be-verified target fails verification; The first test information includes at least sub-test information for indicating that the activation of the unmasked interrupt function fails to pass the verification; If the first activated unmasked interrupt test value is the same as the first activated unmasked interrupt expected value, and the first test level state is the same as the first expected level state, then based on the first write function, the second initial masked interrupt test value is written to the first target to be verified to make the first target to be verified output a second initial masked interrupt state.

7. The UVM-based interrupt verification system according to claim 6, wherein: The control module executes writing, based on the first write function, to the first target to be verified, a second initial masking interruption test value for causing the first target to be verified to output a second initial masking interruption state, and is further configured as follows: Acquire the second activated unmasked interrupt test value from the activated unmasked interrupt register based on the first read function, and acquire the second test level state of the interrupt output port; and acquire the second activated unmasked interrupt expected value corresponding to the second activated unmasked interrupt test value; If the second activated unmasked interrupt test value is different from the second activated unmasked interrupt expected value, and / or the second test level state is different from the second expected level state, generating first test information for indicating that the first to-be-verified target has failed verification; The first test information includes at least sub-test information for indicating that the activation of the unmasked interrupt function fails to pass the verification; If the second activated unmasked interrupt test value is the same as the second activated unmasked interrupt expected value, and the second test level state is the same as the second expected level state, then based on the first write function, the first initial masked interrupt test value is written to the first target to be verified to make the first target to be verified output a first initial masked interrupt state.

8. The UVM-based interrupt verification system according to claim 7, wherein: The control module writes a first initial masking interruption test value for causing the first target to be verified to output a first initial masking interruption state to the first target to be verified based on the first write function, and is further configured as follows: Acquire a third test level state of the interrupt output port, and a third expected level state corresponding to the third test level state; If the third test level state is different from the third expected level state, generating first test information for indicating that the first to-be-verified target fails verification; The first test information at least includes sub-test information for indicating that the port output interrupt function fails to pass the verification; If the third test level state is the same as the third expected level state, a cleanup interruption test value for causing the first target to be verified to output a cleanup interruption state is written to the first target to be verified based on the first write function.

9. The UVM-based interrupt verification system according to claim 8, characterized in that, The control module writes a first cleaning interruption test value for causing the first target to be verified to output a first cleaning interruption state to the first target to be verified based on the first write function, and is further configured as follows: After a preset interval time, writing a second cleanup interruption test value for causing the first target to be verified to output a second cleanup interruption state to the first target to be verified based on the first write function; Acquire a fourth test level state of the interrupt output port, and a fourth expected level state corresponding to the fourth test level state; If the fourth test level state is different from the fourth expected level state, generating first test information for indicating that the first to-be-verified target fails verification; The first test information at least includes sub-test information for indicating that the port output interrupt function fails to pass the verification; If the fourth test level state is the same as the fourth expected level state, second test information for indicating that the first target to be verified has passed verification is generated.

10. A UVM-based interrupt verification method, characterized in that, The UVM-based interrupt verification system applied to any one of claims 1-9, wherein the interrupt verification method comprises: An interrupt configuration module is configured according to the interrupt information to be verified of the target to be verified; the interrupt information to be verified includes at least one first interrupt to be verified corresponding to the first target to be verified, and an interrupt bit corresponding to the first interrupt to be verified; wherein each of the first interrupts to be verified corresponds to at least one interrupt bit; the at least one interrupt bit is used to represent the interrupt value of the first interrupt to be verified; A mapping relationship between the first interrupt register and the first interrupt to be verified is established according to the first address of the first interrupt register; the first interrupt register is a register for storing the interrupt value output by the first target to be verified; wherein each register unit of the first interrupt register is used to store a 1-bit interrupt bit of the first interrupt to be verified; the first interrupt register is connected to the interrupt output port of the first target to be verified; After the initial interrupt test value read based on the first read function is the same as the initial interrupt expected value, writing the first interrupt test value to the first interrupt register of the first target to be verified based on the first write function; Reading the first interrupt test value from the first interrupt register of the first target to be verified based on a first read function, and acquiring a first interrupt expected value corresponding to the first interrupt test value; If the interruption test value is different from the interruption expected value, generating first test information for indicating that the first to-be-verified target fails verification; If the first interruption test value is different from the first interruption expected value, second test information for indicating that the first to-be-verified target passes verification is generated.

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