System-on-a-chip and its operation method for cryptographic applications including monotonic counters

Abstract

Various embodiments of this disclosure relate to on-chip systems and methods of operation thereof for cryptographic applications including monotonic counters. In one embodiment, an on-chip system includes a persistent power supply and a replay protection mechanism, the replay protection mechanism including a monotonic counter, the monotonic counter including a volatile counter register powered by the persistent power supply.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of French patent application No. 2009973, filed on September 30, 2020, which is incorporated herein by reference. Technical Field

[0003] Various embodiments of the present invention relate to a system-on-a-chip, and more particularly to a system-on-a-chip for cryptographic applications including a monotonic counter and a method of operating such a monotonic counter. Background Technology

[0004] As is well known, electronic devices are ubiquitous, especially in the field of wireless communication, such as those used for IoT (“Internet of Things”), where messages exchanged between two devices need to be encrypted in order to obtain secure data transmission.

[0005] Typically, the sending and receiving of signed and / or encrypted messages are performed by systems built on a single system-on-a-chip (“System-on-a-Chip”), which are embedded within the electronic device itself.

[0006] More specifically, messages are encrypted when the confidentiality of the message content is important. Therefore, by using encrypted messages, the confidentiality of the message can be guaranteed, proving that the message comes from an authorized user, and ensuring the integrity of the message.

[0007] When message confidentiality is not important, messages are signed. In this case, the message includes a signature. Therefore, by using signed messages, it can be proven that the message comes from an authorized user and the integrity of the message can be guaranteed.

[0008] You can also encrypt the message first and then sign it.

[0009] However, such a cryptographic system can be vulnerable to replay attacks, in which an external user (hacker) records the messages sent and reuses them.

[0010] Specifically, when the message is encrypted, a hacker cannot read or understand the encrypted message content. Nevertheless, a hacker can still reuse the encrypted information to deceive the recipient, thereby inducing the recipient to perform unwanted actions.

[0011] Furthermore, when a message is signed, the hacker can see its content and therefore know precisely what actions the recipient can perform. Thus, a hacker can reuse signed messages to trick the recipient into performing unwanted actions known to the hacker. By recording signed messages in different communications, a hacker can build a collection of signed messages and use them at will.

[0012] To prevent external users from reusing the message, it typically also includes an anti-duplicate field (or "anti-replay field" or "freshness field") that is uniquely associated with a specific transaction or communication between two people. Therefore, because the anti-replay field must be different from previously recorded fields, external users cannot reuse the recorded message.

[0013] The anti-replay field is also used in message encryption operations or message signature calculations.

[0014] The value of the anti-replay field is not secret. However, cryptographic and signature calculations are performed using this unique anti-replay key.

[0015] Specifically, in the case of symmetric cryptography, the key used for encryption and signature calculations is a secret key known to both the sender and receiver. Therefore, even if the anti-replay field is not secret, an external user cannot decrypt the message or calculate the signature without knowing the secret key.

[0016] Furthermore, in the case of asymmetric cryptography, the key used for encryption is the recipient's public key, and the recipient's private key is used for decryption (only the recipient can decrypt). Therefore, even if the anti-replay field is not secret, an external user cannot decrypt the message without knowing the recipient's private key.

[0017] In asymmetric cryptography, signature computation is performed by the sender using their private key. The signature can be verified by the receiver using the sender's public key. However, because external users cannot generate a signature without knowing the sender's private key, and the value of the anti-replay field must differ from the value of the recorded message, the recorded message cannot be reused.

[0018] The anti-replay field can be formed by a timestamp, a causal or pseudo-random number (“random number”), or a value generated by a monotonic counter.

[0019] A monotonic counter is configured to increment its value for each transaction. Therefore, using a monotonic counter provides a value associated with a transaction that is greater than the value associated with previous transactions, and is typically used in single-chip integrated cryptographic systems because it eliminates the need for complex time synchronization.

[0020] The value of a monotonic counter cannot be modified from the outside. Therefore, using a monotonic counter provides a secure anti-replay mechanism.

[0021] Furthermore, a monotonic counter must have a large number of bits to guarantee several increments that can be performed during the lifetime of the on-chip system.

[0022] The cryptographic architecture is known, in which a monotonic counter is implemented using pages of non-volatile memory (e.g., flash memory).

[0023] However, using non-volatile memory involves numerous erase and write cycles of the memory itself to increase the value of the monotonic counter. These numerous cycles cause the non-volatile memory to age, thus posing a high risk of data loss. Previous monotonic counter implementations were based on flash memory (or any other non-volatile memory) with dozens of pages allocated for this service.

[0024] To support the above, hundreds of millions of erase / programming cycles are required for the flash memory areas. This will lead to data loss due to flash memory page aging.

[0025] Moreover, even if power is lost during an erase or write operation, the cryptographic architecture is still at high risk of data loss.

[0026] Furthermore, incrementing the volatile counter register involves modifications to the flash memory. Such modifications are slow to implement. Summary of the Invention

[0027] The various embodiments provide a system-on-chip architecture for cryptographic applications that can overcome the above-mentioned drawbacks.

[0028] According to an embodiment, a system-on-chip includes a persistent power supply and a monotonic counter, the monotonic counter including a volatile counter register powered by the persistent power supply.

[0029] Specifically, the system-on-chip may include an anti-replay mechanism that includes the monotonic counter, which includes the volatile counter register powered by a persistent power supply.

[0030] The persistent power supply is a power source such as a backup battery, which is configured to maintain system configuration data during on-chip system power failures or restarts.

[0031] The likelihood of the persistent power supply being turned off is very small.

[0032] The monotonic counter is configured to increment the value of the volatile counter register each time the value of the volatile counter register is read.

[0033] Therefore, the fact that the volatile counter register is powered by a persistent power supply ensures that the value of the volatile counter register can be preserved even when the on-chip system is inactive (stopped, in standby, etc.).

[0034] In fact, the risk of power loss is low.

[0035] Moreover, compared to non-volatile registers, using volatile registers allows for faster incrementing of the value of the volatile counter register stored in the volatile register.

[0036] This monotonic counter can be used to provide anti-replay mechanisms. In particular, the value of the volatile counter register can be used for the anti-replay field of secure transactions.

[0037] According to a particularly advantageous embodiment, the monotonic counter includes a bus interface configured to receive commands for a volatile counter register; and a command interpreter including command units configured to interpret the commands received at the bus interface and command the volatile counter according to the commands received at the bus interface.

[0038] The bus interface is configured to connect to the bus in order to communicate with other components of the system on chip.

[0039] According to a particularly advantageous embodiment, the command interpreter further includes a volatile power dissipation register powered by a persistent power supply. The command unit is also configured to store a defined bit word in the power dissipation register, read a bit word from the power dissipation register, compare that bit word with the defined bit word, and, when the command unit determines from the comparison that the bit word in the power dissipation register differs from the defined bit word, transmit an interrupt to the bus interface.

[0040] The defined bitword can be selected during the design phase.

[0041] When a persistent power source delivers power, the defined bit word is stored in the power loss register. However, in the event of power loss from the persistent power source, the bit word in the power loss register is modified.

[0042] The power loss register is used to ensure the integrity of the data stored in the persistent counter.

[0043] In reality, the value of the volatile counter register is lost when the power of the persistent power supply is lost.

[0044] Therefore, by reading the bit word of the power loss register, it can be determined whether the value of the volatile counter register is correct.

[0045] According to a particularly advantageous embodiment, the defined bit word comprises half of the bits set to '0' and the other half of the bits set to '1'. This defined bit word is robust, for example, resistant to attacks including changing the power supply of the on-chip system out of legal range or adding noise or errors to the power supply.

[0046] According to a particularly advantageous embodiment, the command unit is configured to read a bit word stored in the power loss register and compare the bit word with a defined bit word before executing a counter command.

[0047] In the event of power loss from the persistent power supply, the monotonic counter is configured to continue the reset mechanism to ensure the monotonicity of the volatile counter register, that is, to ensure that the value of the volatile counter register is better than the value of the volatile counter register before the power loss from the persistent power supply.

[0048] According to a particularly advantageous embodiment, the command unit is configured to reset the volatile counter register after an interrupted transmit when the bit word of the power loss register is different from the defined bit word.

[0049] The reset process is used to set the value of the volatile counter register.

[0050] The monotonic counter is unavailable until the reset process is complete.

[0051] The command unit can be configured to implement different reset procedures.

[0052] In particular, according to a particularly advantageous embodiment, the command unit is configured to register one bit in non-volatile memory, referred to as a milestone bit, every n increments of the value of the volatile counter register. In the case of resetting the volatile counter register, the command unit is configured to read each milestone bit and set the value of the volatile counter register to MTC = (n+1)*m, where m is the number of milestone bits read.

[0053] This reset process is easy to implement and automatically guarantees the monotonicity of the volatile counter register.

[0054] According to a particularly advantageous embodiment, the command unit is configured to restore the defined bit word from non-volatile memory in the power loss register after resetting the volatile counter register.

[0055] Advantageously, the command interpreter includes a configuration register configured to store configuration data for the monotonic counter.

[0056] According to another embodiment, a method is disclosed for operating a monotonic counter for an anti-replay mechanism in an on-chip system, wherein the monotonic counter includes a volatile counter register, and wherein the method includes: powering the volatile counter register with a persistent power supply.

[0057] Preferably, the method includes: receiving a command for a volatile counter register via a bus interface of a monotonic counter; interpreting the command received at the bus interface using a command unit of a command interpreter of a monotonic counter; and using the command unit to command the volatile counter register according to the command received at the bus interface.

[0058] According to a particularly advantageous embodiment, the method includes: powering a volatile power loss register of a monotonic counter with a persistent power supply; storing a defined bit word in the power loss register; reading the bit word in the power loss register and comparing the bit word with the defined bit word; and transmitting an interrupt to a bus interface when the comparison indicates that the bit word in the power loss register is different from the defined bit word.

[0059] Preferably, the defined bit word includes half of the bits set to "0" and the other half of the bits set to "1".

[0060] According to a particularly advantageous implementation, the bit word stored in the power loss register is read and the value of the power loss register is compared with the defined bit word before the counter command is executed.

[0061] Advantageously, the method includes a reset procedure to reset the volatile counter register after an interrupted transmit if the bit word of the power loss register differs from the defined bit word.

[0062] According to a particularly advantageous implementation, the method includes: registering a bit in non-volatile memory, referred to as a milestone bit, every n increments of the value of the volatile counter register; the reset process includes: reading each milestone bit and setting the value of the volatile counter register to MTC = (n+1)*m, where m is the number of milestone bits read.

[0063] According to a particularly advantageous implementation, the method includes: after resetting the volatile counter register, restoring the defined bit word from non-volatile memory in the power loss register. Attached Figure Description

[0064] Other advantages and features of the invention will become apparent from the detailed description of the embodiments and implementation methods, which are in no way limiting, and are also shown in the accompanying drawings:

[0065] Figure 1 The implementation of the first embodiment is illustrated schematically;

[0066] Figure 2 The implementation of the second embodiment is illustrated schematically; and

[0067] Figure 3 The implementation of the third embodiment is illustrated schematically. Detailed Implementation

[0068] Figure 1 The diagram shows a system-on-a-chip (SoC) including a monotonic counter MTC and several other components ELT1, ..., ELT5.

[0069] Each component (ELT1, ..., ELT5) of a System-on-a-Chip (SoC) has its own function. For example, an SoC may include memory, cryptographic devices, etc.

[0070] The system-on-chip also includes a persistent power supply (VP). The persistent power supply (VP), such as a backup battery, is used to maintain system configuration data during power loss or system-on-chip restarts.

[0071] The likelihood of the persistent power VP being turned off is very small.

[0072] Different components ELT1, ..., ELT5 of the System-on-Chip (SOC) and Monotonic Counter (MTC) are connected via the bus BU.

[0073] The bus (BU) can be an Advanced Microcontroller Bus Architecture (AMBA). For example, the bus can be AHB (“AMBA High Performance Bus”) or AXI (Advanced Extensible Interface).

[0074] More specifically, the monotonic counter MTC can be connected to the bus BU via the security stub SS.

[0075] Security stubs (SS) can be used to constrain the use of monotonic counters to certain security perimeter subdomains.

[0076] The monotonic counter MTC includes a bus interface BI.

[0077] The bus interface BI is configured to receive commands from outside the monotonic counter MTC via the BU_SIG signal. Commands can be user commands used to increment, read, or store the value in the volatile counter register CNT of the monotonic counter MTC. Commands can also be configuration commands.

[0078] The volatile counter register CNT is powered by a persistent power supply.

[0079] This ensures that the value of the volatile counter register can be preserved even when the on-chip system is inactive (stopped, in standby, etc.).

[0080] In reality, the risk of power loss is very low.

[0081] Moreover, compared to non-volatile registers, using volatile registers allows for faster incrementing of the value of the volatile counter register stored in the volatile register.

[0082] In particular, the value of the volatile counter register can be used in the anti-replay field of safe transactions.

[0083] The bus interface BI also receives a clock signal CLK to synchronize the bus interface BI and a reset signal RST to reset the bus interface.

[0084] The monotonic counter MTC also receives the power-start reset signal PRST.

[0085] Specifically, the monotonic counter MTC includes a command interpreter CI. The command interpreter CI is configured to recognize the command CMD_DAT received at the bus interface BI. The command interpreter CI includes a command unit CSM that recognizes the command and registers CDR, CFR, and PLR that store, for example, the command and data.

[0086] Specifically, the command interpreter (CI) includes command and data registers (CDR).

[0087] These command and data registers (CDRs) are configured to store commands in the volatile counter register (CNT) before they are executed.

[0088] The Command and Data Register (CDR) is also configured to receive the value MTC_VAL from the Volatile Counter Register (CNT) and deliver the new reset value MTC_VAL_RST to the Volatile Counter Register (CNT).

[0089] The command and data registers (CDR) also receive the clock signal CLK to synchronize them and the reset signal RST to reset them.

[0090] The command interpreter CI also includes a configuration register CFR. The configuration register CFR is powered by a persistent power supply VP. The configuration register CFR is configured to store configuration data.

[0091] Specifically, the configuration register CFR is used to store data regarding the command execution mode. For example, when the security stub SS is used between the monotonic counter MTC and the bus BU, the command can be executed directly. Furthermore, when the security stub SS is not used between the monotonic counter MTC and the bus BU, the command can be executed through the authentication process disclosed below. Therefore, the configuration register CFR is used to store data indicating whether the command must be executed directly or after the authentication procedure. The configuration register CFR can also be used to store response command criteria (direct or authenticated).

[0092] The configuration registers CFR also receive clock signals CLK to synchronize them and reset signals RST to reset them.

[0093] like Figure 2 As shown, the command interpreter CI includes the command unit CSM.

[0094] The command unit CSM is configured to recognize commands received at the bus interface BI. When the command unit CSM recognizes a command, it is also configured to store that command in the command and data register CDR. The command unit CSM is also configured to command the volatile counter register CNT based on the commands received at the bus interface BI.

[0095] More specifically, the command unit CSM is a state machine circuit system.

[0096] More specifically, the command unit CSM has an output configured to deliver the signal INCR to the volatile counter register CNT to increment its value.

[0097] The command unit CSM also has an output configured to deliver the signal RD to the volatile counter register CNT to read its value upon instruction. When the command unit CSM reads an instruction, the volatile counter register CNT delivers its actual value, MTC_VAL, to the command and data register CDR. This value, MTC_VAL, is then transmitted to the bus interface BI.

[0098] The command unit CSM also has an output configured to deliver the signal STR to the volatile counter register CNT to instruct the value to be stored in the volatile counter register CNT. When the command unit CSM instruction is stored, the volatile counter register CNT stores the value MTC_VAL_RST from the command and data registers CDR.

[0099] The command unit CSM is also configured to receive a clock signal CLK to synchronize it and a reset signal RST to reset it.

[0100] The command unit CSM is also configured to exchange data CFG_DAT with the configuration register CFR.

[0101] The command unit CSM is also configured to transfer commands LCMD and data LDAT to the command and data registers.

[0102] The command unit CSM is powered by VLOG, which is not a persistent power source.

[0103] The command unit CSM is configured to determine whether a command is valid based on the first byte of the command received at the bus interface BI.

[0104] If the command unit CSM determines that the command received at the bus interface BI is a valid command, the command unit is configured to enable the storage of the command LCMD and associated data LDAT in the command and data register CDR or in the configuration register CFR.

[0105] If the command unit CSM determines that the command received at the bus interface BI is not a valid command, the command unit CSM is configured to discard the command.

[0106] Before executing a command, the command unit CSM checks whether the value of the volatile counter register CNT is complete.

[0107] In fact, as mentioned earlier, the likelihood of the persistent power VP being turned off is very small.

[0108] However, when the persistent power supply VP is off, the value of the volatile counter register CNT is lost.

[0109] Therefore, to ensure the integrity of the value of the volatile counter register CNT, the command interpreter CI also includes a power loss register PLR.

[0110] The power loss register PLR is an M-bit (such as 8-bit or 16-bit) register powered by the persistent power module VP. The power loss register PLR can also be reset via the signal VP_RST.

[0111] The command unit is configured to store the defined bit word in the power loss register PLR.

[0112] To ensure the integrity of the value of the volatile counter register CNT, the command unit CSM is configured to read the bit word stored in the power loss register PLR and compare it with a defined bit word before executing the command. The bit word stored in the power loss register PLR is transmitted to the command unit CSM via the signal PLR_DAT.

[0113] If the bit word in the power loss register PLR is the same as the defined bit word, this indicates that the system on-chip (SOC) is not experiencing power loss.

[0114] However, if the bit word in the power loss register PLR is different from the defined bit word, this indicates that the system-on-chip (SoC) has already experienced power loss.

[0115] When the persistent power supply VP delivers power, the defined bit word is stored in the power loss register PLR. However, in the event of power loss by the persistent power supply VP, the bit word in the power loss register is modified.

[0116] The defined bit word can be selected during the design phase. For example, the defined bit word can be equal to 0xAA (hexadecimal representation).

[0117] Preferably, the defined bit word comprises half of the bits set to '0' and the other half of the bits set to '1' (e.g., 0xAA, 0x55, 0x0F, etc.). This defined bit word is robust, for example, resistant to attacks that include changing the power supply of the on-chip system out of legal range or adding noise or errors to the power supply. In practice, such attacks could be used to modify the value of the power dissipation register to 0x00 or 0xFF. Therefore, because the defined bit word comprises half of the bits set to '0' and the other half of the bits set to '1', the defined bit word is significantly different from the values ​​that could be generated by these attacks.

[0118] The power loss register PLR is used to ensure the integrity of the data stored inside the persistent counter.

[0119] Specifically, because the Command Unit (CSM) is configured to read the bit word stored in the Power Dissipation Register (PLR) and compare that bit word with a defined bit word, the CSM can determine whether the System-on-Chip (SoC) has already experienced power dissipation before executing a command. The reading and comparison of the PLR ​​can also be performed periodically.

[0120] In particular, in the case of power loss, the bit word stored in the power loss register can be changed. Therefore, the bit word stored in the power loss register may differ from the expected pattern of the defined bit word (e.g., 0xAA or 0x55). For example, after power loss, the bit word stored in the power loss register may be equal to 0x00.

[0121] Furthermore, the command unit CSM is configured to issue an transmit interrupt INT1 when the command unit detects from the compare that the bit word of the power loss register PLR differs from the expected defined bit word. This interrupt INT1 is transmitted to the bus interface BI.

[0122] The interrupt INT1 is used to indicate to other components of the on-chip system that the value of the volatile counter register CNT may be incorrect due to power loss.

[0123] When the command unit (CSM) detects that the system-on-chip (SoC) is experiencing power loss, the CSM is configured to initiate a reset procedure. The reset procedure sets the value of the volatile counter register (CNT) to restore its integrity. The reset procedure can be configured using configuration registers.

[0124] In particular, the command unit CSM can be configured to implement different reset procedures.

[0125] For example, the first reset process involves providing new values ​​to the volatile counter register and configuration value using a certified command. The certified command is a signed command. The signature is calculated using a MAC algorithm with freshness. A random number generator is used to provide random numbers to calculate the signature.

[0126] The second reset process involves providing new values ​​to the volatile counter register and configuration values ​​using encrypted command packets. For example, the command packets are encrypted using the AES algorithm (“Advanced Encryption Standard”). The command packets include random numbers generated by a random number generator to prevent replay attacks.

[0127] Preferably, a third reset process is implemented.

[0128] The third reset process involves defining the value of the volatile counter register CNT based on several bits (called milestone bits) from the non-volatile memory. The non-volatile memory can be the system-on-chip's internal flash memory.

[0129] Specifically, during normal operation of the volatile counter register CNT, the command unit CSM is configured to register a milestone bit in non-volatile memory every n increments of the value of the volatile counter register CNT. The number of increments n required to store the milestone bit is defined according to the desired granularity. The higher the value of n, the lower the granularity and the greater the amount of non-volatile memory required to store the milestone bit.

[0130] During the reset process, the command unit CSM is configured to read each milestone bit. The command unit is then configured to set the value of the volatile counter register to MTC = (n+1)*m, where m is the number of milestone bits read and n represents the granularity (the incrementing number of milestone bits that need to be stored).

[0131] The monotonic counter is unavailable until the reset process is complete.

[0132] If persistent power is stored, the defined bit word is restored in the power loss register PLR via the REST signal at the end of the reset process.

[0133] Furthermore, when the command unit CSM detects that the system-on-chip (SoC) is not experiencing power loss, the command unit CSM can be configured to perform additional security checks before executing a command, based on the command execution mode stored in the configuration register CFR.

[0134] Specifically, when the security stub (SS) is used between the monotonic counter (MTC) and the bus (BU), commands can be executed directly without additional security checks. In fact, the security stub is configured to perform these security checks.

[0135] However, if the security stub SS is not used between the monotonic counter MTC and the bus BU, the command unit CSM can be configured to perform an authentication process before executing the command.

[0136] Specifically, in the authenticated command execution mode, cryptographic methods are used to ensure authentication. Therefore, the command group includes a MAC signature (MAC stands for "Message Authentication Code") and a freshness field. The value of the freshness field is a random value provided by the on-chip random number generator or generated by a pseudo-random generator implemented by a dedicated kernel of the on-chip system.

[0137] Specifically, the command unit CSM can be configured to perform a freshness check. During the freshness check, the command unit checks whether the value of the freshness field (i.e., the value of the volatile counter register CNT) is the expected value. Specifically, the command unit CSM compares the value of the volatile counter register with the value of the freshness field.

[0138] If the value of the freshness field is different from the value of the volatile counter register CNT, the command is discarded.

[0139] Otherwise, the Command Unit (CSM) is configured to initiate a signature check process. At the start of the signature check procedure, the CSM is configured to generate a specific signature check interrupt (INT2) to one of the kernels in the System-on-Chip (SoC) kernel and wait for the result of the signature check performed by the kernel to determine if the signature is correct. Specifically, the SoC kernel is configured to perform the signature check and send the result to a monotonic counter indicating whether the signature matches the expected signature. The kernel may include hardware resources for performing the signature check. Alternatively, the kernel may be configured to execute software modules suitable for performing the signature check. The kernel may also use both hardware resources and software modules simultaneously to perform the signature check.

[0140] Then, when an interrupt is serviced by the kernel, the command unit CSM is configured to provide the stored command packets upon kernel request.

[0141] The kernel then calculates the MAC signature using another component of the system-on-chip (SoC) or via software, and provides the calculated signature to the command unit (CSM). The calculated signature can then be written into the command and data registers (CDR).

[0142] Then, the command unit CSM compares the calculated signature with the signature received with the command.

[0143] If the calculated signature differs from the signature received with the command, the command is discarded.

[0144] Otherwise, the command unit (CSM) executes the command. The command result is then communicated to the host according to the mode selected in the configuration register. In particular, the command response mode can be a direct response or an authenticated response.

[0145] When the selection mode is direct response mode, the command unit CSM is configured to send command response packets directly to the host (internal or external to the system-on-chip) by following the bus protocol rules.

[0146] When the selected mode is Authentication Response Mode, the command response packet is signed using a MAC algorithm, such as HMAC-SHA256. Therefore, the command response packet includes the command response, a freshness field, and a response signature. This command response packet is sent to the host (internal or external to the on-chip system) according to the bus protocol rules.

[0147] Figure 3 The operation method of a monotonic counter is shown.

[0148] At initial step 30, the monotonic counter begins its design phase. During this phase, the command unit stores the defined bit word in the power dissipation register. The power dissipation register is powered by a persistent power supply.

[0149] At step 31, the monotonic counter receives a command at its bus interface BI.

[0150] At step 32, the command unit CSM receives the first byte of the command from the bus interface and determines whether the command is valid.

[0151] If the command unit CSM determines that the command is a valid command, the command unit stores the command and related data in the command and data register CDR or the configuration register CFR at step 34.

[0152] If the command unit CSM determines that the command is not a valid command, the command unit CSM discards the command at step 33.

[0153] After step 34, the command unit CSM verifies the integrity of the value of the volatile counter register CNT at step 35.

[0154] Specifically, the command unit reads the bit word stored in the power loss register and compares the bit word with the defined bit word.

[0155] If the command unit CSM determines that the bit word stored in the power loss register PLR is the same as the defined bit word, the command unit concludes that the system-on-chip (SoC) has not yet experienced power loss and that the value of the volatile counter register is correct. Therefore, at step 39, the command unit may perform additional safety checks if necessary before executing the command.

[0156] However, if the command unit determines that the bit word stored in the power loss register PLR is different from the defined bit word, the command unit concludes that the system-on-chip (SoC) has experienced power loss and that the value of the volatile counter register is incorrect. In this case, the command unit issues interrupt INT1 at step 36, which is transmitted to the bus interface BI.

[0157] Following transmit interrupt INT1, the command unit performs a reset procedure in step 37 to retrieve the integrity of the volatile counter register CNT. Specifically, the command unit reads the configuration register to determine which reset procedure was selected.

[0158] For example, if the selected reset procedure is the third procedure described earlier, the command unit CSM reads each milestone bit stored in the non-volatile memory. The command unit is then configured to set the value of the volatile counter register to MTC = (n+1)*m, where m is the number of milestone bits read and n represents the granularity (the incremental sparse number of milestone bits required to store them).

[0159] Then, at step 38, the command unit restores the defined bit word in the power loss register PLR.

[0160] In addition, as mentioned above, when the command unit CSM detects that the system-on-chip (SoC) has not yet experienced power loss, it may perform other safety checks at step 39 if necessary before executing the command.

[0161] Specifically, the command unit reads the configuration register (CFR) to understand the command execution mode.

[0162] In step 41, if the command execution mode is direct execution mode, the command unit can directly execute the command.

[0163] At step 39, if the command execution mode is the certified command execution mode, the command unit continues to perform other security checks (such as the freshness check and signature check described above).

[0164] If the command passes the security check, it can be executed at step 41. Otherwise, the command is discarded at step 40.

[0165] The command execution at step 41 results in a command result issued from the volatile counter register. At step 42, this command result is transmitted to the command unit. The command unit transmits the command result to the host via the bus interface, depending on the response mode selected in the configuration register (such as an authenticated response or a direct response as described above).

[0166] The embodiment provides an architecture for a monotonic counter that can be integrated into a system-on-a-chip (SoC) for cryptographic applications. Because it uses volatile registers, the system is not susceptible to data loss or aging. Furthermore, using volatile registers allows for an increased rate of increase in the monotonic counter value.

[0167] Of course, these embodiments are susceptible to various changes and modifications, as will be apparent to those skilled in the art. For example, a monotonic counter may include more than one counter powered by a persistent power supply. In this case, the monotonic counter may still contain only one command interpreter (CI). In particular, the command unit of the command interpreter may be configured to command each counter by selecting the counter addressed by the command. More specifically, the command unit may include an output dedicated to enabling or disabling the counter. Thus, to command a counter, the command unit may enable that counter and disable other counters.

Claims

1. A system-on-a-chip, comprising: Long-lasting power supply; as well as An anti-replay mechanism includes a monotonic counter, the monotonic counter including a volatile counter register powered by the persistent power supply, wherein the monotonic counter includes a volatile power loss register powered by the persistent power supply, and wherein the monotonic counter is configured to: Store the defined bit word in the volatile power loss register; Read the bit word from the volatile power loss register and compare the bit word with the defined bit word; as well as In response to the comparison determining that the bit word of the volatile power loss register is different from the defined bit word, an interrupt is transmitted to the bus interface.

2. The system-on-chip according to claim 1, wherein the monotonic counter comprises: The bus interface is configured to receive commands for the volatile counter register; as well as A command interpreter, including a command unit, the command unit being configured to: Interpret the command received at the bus interface; as well as The volatile counter register is commanded according to the command received at the bus interface.

3. The system-on-a-chip according to claim 2, The command interpreter further includes the volatile power loss register, and The command unit is further configured to: The defined bit word is stored in the volatile power loss register. Read the bit word from the volatile power loss register and compare the bit word with the defined bit word. The interrupt was transmitted.

4. The system-on-a-chip according to claim 3, wherein the defined bit word is a bit word in which half of the bits are set to '0' and the other half of the bits are set to '1'.

5. The system-on-a-chip of claim 3, wherein the command unit is configured to read the bit word stored in the volatile power loss register before the execution of the command, and compare the value of the bit word stored in the volatile power loss register with a defined bit word.

6. The system-on-a-chip according to claim 3, wherein the command unit is configured to: reset the volatile counter register after the interruption is transmitted when the bit word of the volatile power loss register is different from the defined bit word.

7. The system-on-a-chip of claim 6, wherein the command unit is configured to register a bit in non-volatile memory every n increments of the value of the volatile counter register, the bit being referred to as a milestone bit, and wherein, in the event of a reset of the volatile counter register, the command unit is configured to read each milestone bit and set the value of the volatile counter register to MTC = (n+1)*m, where m is the number of milestone bits read.

8. The system-on-a-chip of claim 6, wherein the command unit is configured to restore the defined bit word from non-volatile memory in the volatile power loss register after resetting the volatile counter register.

9. The system-on-a-chip of claim 2, wherein the command interpreter includes a configuration register configured to store configuration data for the monotonic counter.

10. A method for operating a monotonic counter for an anti-replay mechanism in an on-chip system, wherein the monotonic counter includes a volatile counter register and a volatile power loss register, the method comprising: The volatile counter register and the volatile power loss register are powered by a persistent power supply. Store the defined bit word in the volatile power loss register; Read the bit word from the volatile power loss register. Compare the bit word with the defined bit word; as well as In response to the comparison determining that the bit word of the volatile power loss register is different from the defined bit word, an interrupt is transmitted to the bus interface.

11. The method of claim 10, further comprising: Commands for the volatile counter register are received via the bus interface through the monotonic counter. The command unit of the command interpreter of the monotonic counter interprets the command received at the bus interface; as well as The command unit commands the volatile counter register according to the command received at the bus interface.

12. The method of claim 10, wherein the defined bit word is a bit word in which half of the bits are set to '0' and the other half of the bits are set to '1'.

13. The method of claim 10, wherein prior to the execution of the command, a read of the bit word stored in the volatile power loss register and a comparison of the value of the bit word in the volatile power loss register with the defined bit word are performed.

14. The method of claim 10, further comprising: When the bit word of the volatile power loss register is different from the defined bit word, a reset procedure is performed to reset the volatile counter register after the interrupted transmission.

15. The method of claim 14, further comprising: Every n increments of the value of the volatile counter register, a bit is registered in non-volatile memory, referred to as a milestone bit. The reset process includes: reading each milestone bit and setting the value of the volatile counter register to MTC = (n+1)*m, where m is the number of milestone bits read.

16. The method of claim 14, further comprising: After the reset of the volatile counter register, the defined bit word is restored from the non-volatile memory in the volatile power loss register.

17. A method for operating a monotonic counter of an on-chip system, wherein the monotonic counter includes a volatile counter register, a volatile power loss register, and a bus interface, the method comprising: The volatile power loss register is powered by a persistent power supply; Receive commands at the bus interface; The integrity of the value of the volatile counter register is verified in the following way: Read the bit word from the volatile power loss register and compare the bit word with the defined bit word; as well as Determine whether the monotonic counter is subject to power loss; When the comparison indicates that the bit word of the volatile power loss register is different from the defined bit word, and it is determined that the monotonic counter is subject to the power loss, an interrupt is sent to the bus interface. as well as Following the interrupted transmission, a reset procedure is performed to reset the volatile counter register.

18. The method of claim 17, further comprising: Every n increments of the value in the volatile counter register, a bit is registered in non-volatile memory, referred to as a milestone bit. The reset process includes: reading each milestone bit and setting the value of the volatile counter register to MTC = (n+1)*m, where m is the number of milestone bits read.

19. The method of claim 17, further comprising: After the reset of the volatile counter register, the defined bit word is restored from the non-volatile memory in the volatile power loss register.

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