Verification methods and systems for state machines in digital integrated circuit design

Abstract

The present invention provides a verification method and a verification system for a state machine in a digital integrated circuit design. The verification method lists the output signals and interaction signals expected to appear in each state of the state machine in a table, and then writes the corresponding first SVA assertion according to the expected changes of each signal in the table. When the state machine is simulated and run using a simulation module, each first SVA assertion automatically checks the timing of the corresponding signal of the state machine in each state, automatically determines whether the assertion is successful or failed, and quickly verifies the output signal and interaction signal of the state machine, thereby improving the verification efficiency. Compared with the traditional scoreboard comparison verification method, the solution of the present invention is applied to block-level or even UT-level digital integrated circuit verification. Based on SVA assertions, according to the timing of each signal of the state machine, a large number of output signals and interaction signals generated by the state machine in each state are verified, so that the verification can be completed in a shorter time, and the verification efficiency is higher.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a verification method and a verification system for a state machine in digital integrated circuit design. Background Art

[0002] The module level (block) and IP (Verification Intellectual Properties) level contain a large number of digital integrated circuits. In the design of digital integrated circuits, state machines are usually used in large quantities to implement corresponding functions. In different states of the state machine, there will be many output signals and interactive signals. The existing verification method for IP and block-level digital circuits is mainly to verify the output signals and interactive signals of each state machine through scoreboard comparison and manual waveform viewing, which is very convenient for data comparison. However, for digital integrated circuit verification, there are many state machines that need to be verified in block-level or even UT-level verification. At this time, the number of output signals and interactive signals is large, and the verification method through traditional scoreboard comparison will be very complicated and inefficient. Summary of the invention

[0003] The present invention provides a verification method and a verification system for a state machine in digital integrated circuit design, so as to complete the verification of the state machine in a shorter time and with higher verification efficiency.

[0004] In a first aspect, the present invention provides a verification method for a state machine in a digital integrated circuit design, the verification method comprising: obtaining output signals and interaction signals expected to appear in each state of the state machine to form a table; writing a corresponding first SVA (Systerm Verilog Assertion) assertion according to the expected changes of each signal in the table; using a simulation module to simulate and run the state machine; automatically judging whether the assertion is successful or failed according to the timing of the signal corresponding to each first SVA assertion; if all the first SVA assertions are successful, it is determined that the output signals and interaction signals expected to appear in each state of the state machine are consistent with the expected changes; if there is a first SVA assertion failure, it is determined that the output signal or interaction signal expected to appear in a certain state of the state machine does not meet the expected changes, the simulation is interrupted, and an error message is printed.

[0005] In the above scheme, the output signals and interactive signals expected to appear in each state of the state machine are listed in a table, and then the corresponding first SVA assertions are written according to the expected changes of each signal in the table. When the simulation module is used to simulate the running state machine, each first SVA assertion automatically checks the timing of the corresponding signals of the state machine in each state, automatically determines whether the assertion is successful or failed, and quickly verifies the output signals and interactive signals of the state machine, thereby improving the verification efficiency. Compared with the traditional scoreboard comparison verification method, the scheme of the present invention is applied to the block-level or even UT-level digital integrated circuit verification. Based on the SVA assertion, according to the timing of each signal of the state machine, a large number of output signals and interactive signals generated by the state machine in each state are verified, so that the verification can be completed in a shorter time, and the verification efficiency is higher.

[0006] In a specific implementation, the verification method further includes: if there is a first SVA assertion failure, after receiving the modified state machine, re-verifying the modified state machine according to the verification method until all first SVA assertions are successful. During the verification of the state machine, if it is found that there is a first SVA assertion failure, the simulation will be interrupted, and the error information will be delivered to the relevant designer to modify the code of the state machine, and the modified state machine will be re-verified in the above manner until it is determined that the output signals and interaction signals expected to appear in each state of the state machine meet the expected changes, so as to facilitate targeted modification of the state machine code, which not only improves the verification efficiency, but also improves the accuracy of the verification.

[0007] In a specific implementation, the verification method further includes: obtaining all possible flip situations expected by the state machine and adding them to a table; writing corresponding second SVA assertions according to each flip situation in the table; while using the simulation module to simulate the state machine, automatically judging whether the assertion is successful or failed according to the expected flip situation corresponding to each second SVA assertion; if all second SVA assertions are successful, it is determined that all possible flip situations expected by the state machine meet the expected flip; if there is a second SVA assertion failure, it is determined that the state machine has a flip situation that does not meet the expectations, interrupting the simulation, and printing an error message. All possible flip situations of the state machine are also verified based on the SVA assertion, so that when there are a large number of flip situations in the state machine, all flip situations of the state machine can be verified in a shorter time, and the verification efficiency is higher.

[0008] In a specific implementation, if all second SVA assertions are successful, the verification method further includes: checking the coverage of all flip situations listed in the table covered by all second SVA assertions; judging whether the coverage reaches 100%; if it reaches 100% and all first SVA assertions are successful, outputting a verification result that the state machine design meets the standard; if it is less than 100%, printing an error message. When it is determined that all flip situations that may occur in the state machine meet the expected flip, it is further checked whether the second SVA assertion can completely cover all flip situations listed in the table to prevent the occurrence of flip situations that are not verified, thereby improving the accuracy of the verification result.

[0009] In a specific implementation, the verification method further includes: if there is a second SVA assertion failure, or the coverage is less than 100%, after receiving the modified state machine, re-verifying the modified state machine according to the verification method until all second SVA assertions are successful and the coverage reaches 100%. During the verification of the state machine, if it is found that there is a second SVA assertion failure, the simulation will be interrupted, and the error information will be delivered to the relevant designer to modify the code of the state machine, and the modified state machine will be re-verified in the above manner until it is determined that the output signals and interaction signals expected to appear in each state of the state machine meet the expected changes, so as to facilitate targeted modification of the state machine code, which not only improves the verification efficiency, but also improves the accuracy of the verification.

[0010] In a specific implementation, writing a corresponding second SVA assertion according to each flip situation in the table includes: using a scripting language tool to extract all flip situations in the table, and automatically generating a second SVA assertion that can traverse all possible flip situations of the state machine, thereby improving the efficiency of generating the second SVA assertion.

[0011] In a specific implementation, the scripting language tool is Python. The Python script uses the relatively simple SVA code during state machine flip check. When dealing with a large number of flip situations in the state machine, a list of all possible flip situations can be directly listed, and then the Python script is used to automatically generate the relevant second SVA assertion, which greatly improves efficiency.

[0012] In the second aspect, the present invention also provides a verification system for a state machine in a digital integrated circuit design, the verification system comprising: an acquisition module, a first SVA assertion generation module, a simulation module, a first SVA assertion judgment module and a statistical determination module. The acquisition module is used to obtain the output signals and interactive signals expected to appear in each state of the state machine and form a table; the first SVA assertion generation module is used to write the corresponding first SVA assertion according to the expected changes of each signal in the table; the simulation module is used to simulate the running state machine; the first SVA assertion judgment module is used to automatically determine whether each first SVA assertion is a successful assertion or a failed assertion according to the signal timing corresponding to each first SVA assertion; the statistical determination module is used to determine that the output signals and interactive signals expected to appear in each state of the state machine are in accordance with the expected changes when all the first SVA assertions are successful; the statistical determination module is also used to interrupt the simulation and print an error message when the first SVA assertion fails, and the output signal or interactive signal expected to appear in a certain state of the state machine does not meet the expected changes.

[0013] In the above scheme, the output signals and interactive signals expected to appear in each state of the state machine are listed in a table, and then the corresponding first SVA assertions are written according to the expected changes of each signal in the table. When the simulation module is used to simulate the running state machine, each first SVA assertion automatically checks the timing of the corresponding signals of the state machine in each state, automatically determines whether the assertion is successful or failed, and quickly verifies the output signals and interactive signals of the state machine, thereby improving the verification efficiency. Compared with the traditional scoreboard comparison verification method, the scheme of the present invention is applied to the block-level or even UT-level digital integrated circuit verification. Based on the SVA assertion, according to the timing of each signal of the state machine, a large number of output signals and interactive signals generated by the state machine in each state are verified, so that the verification can be completed in a shorter time, and the verification efficiency is higher.

[0014] In a specific implementation, the acquisition module is also used to obtain all possible flip situations that are expected to occur in the state machine and add them to the table. The verification system also includes a second SVA assertion generation module and a second SVA assertion judgment module; wherein the second SVA assertion generation module is used to write corresponding second SVA assertions according to each flip situation in the table; the second SVA assertion judgment module is used to automatically determine whether each second SVA assertion is a successful assertion or a failed assertion according to the expected flip situation corresponding to each second SVA assertion while simulating the state machine. The statistical determination module is also used to determine that all possible flip situations that may occur in the state machine meet the expected flip when all second SVA assertions are successful; the statistical determination module is also used to determine that the state machine has a flip situation that does not meet the expectations when there is a second SVA assertion failure, interrupt the simulation, and print an error message. All possible flip situations of the state machine are also verified based on the SVA assertion, so that when there are a large number of flip situations in the state machine, all flip situations of the state machine can be verified in a shorter time, and the verification efficiency is higher.

[0015] In a specific embodiment, the verification system also includes: a viewing module, which is used to view the coverage of all the second SVA assertions covering all the flip situations listed in the table when all the second SVA assertions are successful. The statistical determination module is also used to output the verification result that the state machine design meets the standards when the coverage reaches 100% and all the first SVA assertions are successful. And the statistical determination module is also used to print errors when the coverage is less than 100%. When it is determined that all the flip situations that may be expected to occur in the state machine meet the expected flips, it is further checked whether the second SVA assertions can completely cover all the flip situations listed in the table to prevent the occurrence of flip situations that are not verified, thereby improving the accuracy of the verification results. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A flow chart of a method for verifying a state machine in a digital integrated circuit design provided by an embodiment of the present invention;

[0017] Figure 2 A flowchart of another method for verifying a state machine in a digital integrated circuit design provided by an embodiment of the present invention;

[0018] Figure 3 A flowchart of another method for verifying a state machine in a digital integrated circuit design provided by an embodiment of the present invention;

[0019] Figure 4 A code schematic diagram of a first SVA assertion provided by an embodiment of the present invention;

[0020] Figure 5A code schematic diagram of a second SVA assertion provided by an embodiment of the present invention;

[0021] Figure 6 A schematic diagram of a coverage viewing page provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0022] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0023] In order to facilitate understanding of the polarizer provided by the embodiment of the present invention, the following first describes the application scenario of the verification method of the state machine in the digital integrated circuit design provided by the embodiment of the present invention, and the verification method is applied to the verification process of the state machine designed in the digital integrated circuit design. The verification method of the state machine in the digital integrated circuit design is described in detail below in conjunction with the accompanying drawings.

[0024] refer to Figure 1 , the verification method of the state machine in the digital integrated circuit design provided by the embodiment of the present invention includes:

[0025] S10: Obtain output signals and interaction signals expected to appear in each state of the state machine and form a table;

[0026] S20: writing a corresponding first SVA assertion according to the expected changes of each signal in the table;

[0027] S30: using a simulation module to simulate the running state machine;

[0028] S40: automatically determining whether the assertion is successful or failed according to the timing of the signal corresponding to each first SVA assertion;

[0029] S51: If all first SVA assertions are successful, it is determined that the output signals and interaction signals expected to appear in each state of the state machine conform to the expected changes;

[0030] S52: If the first SVA assertion fails, it is determined that the output signal or interaction signal expected to appear when the state machine exists in a certain state does not conform to the expected change, the simulation is interrupted, and an error message is printed.

[0031] In the above scheme, the output signals and interactive signals expected to appear in each state of the state machine are listed in a table, and then the corresponding first SVA assertions are written according to the expected changes of each signal in the table. When the simulation module is used to simulate the state machine, each first SVA assertion automatically checks the timing of the corresponding signals of the state machine in each state, and automatically determines whether the assertion is successful or failed, and quickly verifies the output signals and interactive signals of the state machine, thereby improving the verification efficiency. Compared with the traditional scoreboard comparison verification method, the scheme of the present invention is applied to block-level or even UT-level digital integrated circuit verification. Based on SVA assertions, according to the timing of each signal of the state machine, a large number of output signals and interactive signals generated by the state machine in each state are verified, so that the verification can be completed in a shorter time, and the verification efficiency is higher. The above steps are described in detail below with reference to the accompanying drawings.

[0032] First, refer to Figure 1 and Figure 2 , obtain the output signals and interaction signals expected to appear in each state of the state machine, and fill the output signals and interaction signals in a table to form a table containing the output signals and interaction signal information of the state machine in each state. In addition, when there are multiple state machines to be verified, the output signals and interaction signals expected to appear in each state machine in each state can be added to the table. Subsequently, the output signals and interaction signals of each state machine can be verified separately at the same time.

[0033] Next, refer to Figure 1 and Figure 2 , write the corresponding first SVA assertion according to the expected changes of each signal in the table. That is, according to the output signals and interaction signals in each state listed in the previous step, write the corresponding SVA assertion for judgment. The reason why this SVA assertion is defined as the first SVA assertion is to distinguish it from another SVA assertion that appears in the subsequent embodiments. It should be noted that "first" and "second" are not used as limitations on the substantive content of the SVA language. Figure 4 The code for the first SVA assertion is shown as an example.

[0034] Next, refer to Figure 1 and Figure 2 , use the simulation module to simulate the running state machine, that is, run the state machine for simulation. The simulation module can use EDA tools or other simulation modules that can run the state machine.

[0035] Next, refer to Figure 1 and Figure 2In the process of using the simulation module to simulate the state machine, each first SVA assertion will search for the timing of the corresponding signal, and automatically determine whether the assertion is successful or failed based on the timing of the corresponding signal. If the assertion is successful, it means that the output and interaction of the state machine are correct; if the assertion fails, the assertion will interrupt the simulation and print an error message, and the error message will be delivered to the relevant designers through emails and other means to modify the code of the state machine. Specifically, if all the first SVA assertions are successful, it is determined that the output signals and interaction signals expected to appear in each state of the state machine are consistent with the expected changes, indicating that the output and interaction of the state machine are correct. If there is a failure of the first SVA assertion, it is determined that the output signal or interaction signal expected to appear in a certain state of the state machine does not meet the expected changes, the simulation will be interrupted, and an error message will be printed, and the error message will be delivered to the relevant designers to modify the code of the state machine.

[0036] The method shown above lists the output signals and interactive signals expected to appear in each state of the state machine in a table, and then writes the corresponding first SVA assertions according to the expected changes of each signal in the table. When the simulation module is used to simulate the state machine, each first SVA assertion automatically checks the timing of the corresponding signal of the state machine in each state, automatically determines whether the assertion is successful or failed, and quickly verifies the output signals and interactive signals of the state machine, thereby improving the verification efficiency. Compared with the traditional scoreboard comparison verification method, the solution of the present invention is applied to block-level or even UT-level digital integrated circuit verification. Based on SVA assertions, according to the timing of each signal of the state machine, a large number of output signals and interactive signals generated by the state machine in each state are verified, so that the verification can be completed in a shorter time, and the verification efficiency is higher.

[0037] In addition, if there is a failure of the first SVA assertion, after the relevant designer modifies the code of the state machine according to the printed error information, the verification method may further include: re-verifying the modified state machine in the above manner, that is, receiving the modified state machine, and after receiving the modified state machine, re-verifying the modified state machine according to the verification method until all the first SVA assertions are successful. During the verification of the state machine, if it is found that the first SVA assertion fails, the simulation will be interrupted, and the error information will be delivered to the relevant designer to modify the code of the state machine, and the modified state machine will be re-verified in the above manner until it is determined that the output signals and interaction signals expected to appear in each state of the state machine meet the expected changes, so as to facilitate targeted modification of the state machine code, which not only improves the verification efficiency, but also improves the accuracy of the verification.

[0038] Furthermore, reference Figure 2 and Figure 3 In the process of obtaining the output signals and interaction signals expected to appear in each state of the state machine, you can further obtain all the expected flip situations of the state machine. When filling in the output signals and interaction signals expected to appear in each state of the state machine into the table, you can also add all the expected flip situations of the state machine obtained to the table, so that while running the state machine, the expected flip situations of the state machine can also be verified. That is, at this time, the table contains not only the output signals and interaction signals of the state machine, but also all the expected flip situations of the state. And when there are multiple state machines to be verified, all the expected flip situations of each state machine can be added to the table, and then the expected flip situations of each state machine can be verified separately.

[0039] When verifying all the possible flip situations that the state machine is expected to encounter, refer to Figure 2 , according to each flip situation of the state machine in the table, a corresponding second SVA assertion can be written. The second SVA assertion is an SVA assertion for verifying each flip situation of the state machine. The "second" here is only used to distinguish it from the first SVA assertion mentioned above, and does not make a substantial limitation. Figure 5 The code of a second SVA assertion is shown as an example. While the simulation module is used to simulate the state machine, it will automatically determine whether the assertion is successful or failed according to the expected flip situation corresponding to each second SVA assertion, that is, the second SVA assertion will check whether each flip situation of the state machine meets the flip situation we listed. If all the second SVA assertions are successful, it means and determines that all the flip situations that may occur in the state machine meet the expected flip situation. If there is a second SVA assertion failure, it means and determines that the state machine has a flip situation that does not meet the expectations, interrupts the simulation, prints an error message, and delivers the error message to the relevant designer to modify the code of the state machine. For example, if an unlisted flip situation may occur, an assertion failure will occur and an error message will be printed, and it will be delivered to the relevant designer to modify the code of the state machine. In the above manner, all possible flip situations of the state machine are also verified based on the SVA assertion, so that when there are a large number of flip situations in the state machine, all flip situations of the state machine can be verified in a shorter time, and the verification efficiency is higher.

[0040] In addition, refer to Figure 2 and Figure 3If all the second SVA assertions are successful, the verification method can further check whether the second SVA assertions can fully cover the verification of all the flip situations listed in the table. Specifically, when all the second SVA assertions are successful, the coverage of all the flip situations listed in the table can be further checked to determine whether the second SVA assertions can fully cover the verification of all the flip situations based on the coverage. Specifically, determine whether the coverage reaches 100%. Reference Figure 2 and Figure 6 If the coverage reaches 100% and all the first SVA assertions are successful, it means that the verification of the output signal and interaction signal of the state machine meets the expected design, and the verification of all flip situations of the state machine also meets expectations, and the verification coverage of all flip situations can reach 100%, indicating that the output state machine design meets the verification results, that is, the design of the state machine is successful, and the output signal, interaction signal and flip situation can meet the design requirements. If it is less than 100%, it means that the second SVA assertion cannot completely cover all the flip situations listed in the table, indicating that there are flip situations listed in the table that have not been verified. Since they have not been verified, it is not certain whether the flip situations that have not been verified meet expectations, indicating that the state machine at this time still has problems, and the error information can be printed and delivered to the relevant designers to modify the state machine code.

[0041] When determining that all possible flip situations expected in the state machine meet the expected flip situations, further checking whether the second SVA assertion can completely cover all flip situations listed in the table can prevent some flip situations from being unverified, thereby improving the accuracy of the verification result.

[0042] When writing the corresponding second SVA assertion according to the various flip situations in the table, refer to Figure 2 and Figure 3 , you can use a scripting language tool to extract all the flip situations in the table and automatically generate a second SVA assertion that can traverse all possible flip situations of the state machine, thereby improving the efficiency of generating the second SVA assertion. Figure 2 and Figure 3 , you can choose Python as the scripting language tool, and use the relatively simple SVA code of Python script when checking the state machine flip. When there are a large number of flip situations in the state machine, you can directly list all possible flip situations, and then use Python script to automatically generate the relevant second SVA assertion, which will greatly improve efficiency.

[0043] In addition, reference Figure 3 and Figure 4If the second SVA assertion fails or the coverage is less than 100%, after modifying the state machine code or the second SVA assertion, refer to Figure 2 , the verification method may further include: receiving the modified state, and after receiving the modified state machine, re-verifying the modified state machine according to the verification method until all second SVA assertions are successful and the coverage reaches 100%. During the verification of the state machine, if it is found that the second SVA assertion fails, the simulation will be interrupted, and the error information will be delivered to the relevant designer to modify the code of the state machine, and the modified state machine will be re-verified in the above manner until it is determined that the output signals and interaction signals expected to appear in each state of the state machine meet the expected changes, so as to facilitate targeted modification of the state machine code, which not only improves the verification efficiency, but also improves the accuracy of the verification.

[0044] In each of the embodiments shown above, the output signals and interactive signals expected to appear in each state of the state machine are listed in a table, and then the corresponding first SVA assertions are written according to the expected changes of each signal in the table. When the simulation module is used to simulate the state machine, each first SVA assertion automatically checks the timing of the corresponding signal of the state machine in each state, automatically determines whether the assertion is successful or failed, and quickly verifies the output signals and interactive signals of the state machine, thereby improving the verification efficiency. Compared with the traditional scoreboard comparison verification method, the solution of the present invention is applied to the block-level or even UT-level digital integrated circuit verification. Based on the SVA assertion, according to the timing of each signal of the state machine, a large number of output signals and interactive signals generated by the state machine in each state are verified, so that the verification can be completed in a shorter time, and the verification efficiency is higher.

[0045] In addition, an embodiment of the present invention also provides a verification system for a state machine in a digital integrated circuit design, the verification system comprising: an acquisition module, a first SVA assertion generation module, a simulation module, a first SVA assertion judgment module and a statistical determination module. The acquisition module is used to obtain the output signals and interactive signals expected to appear in each state of the state machine and form a table; the first SVA assertion generation module is used to write the corresponding first SVA assertion according to the expected changes of each signal in the table; the simulation module is used to simulate the running state machine; the first SVA assertion judgment module is used to automatically determine whether each first SVA assertion is an assertion success or an assertion failure according to the signal timing corresponding to each first SVA assertion; the statistical determination module is used to determine that the output signals and interactive signals expected to appear in each state of the state machine are consistent with the expected changes when all the first SVA assertions are successful; the statistical determination module is also used to interrupt the simulation and print an error message when the first SVA assertion fails, and the output signal or interactive signal expected to appear in a certain state of the state machine does not meet the expected changes.

[0046] In the above scheme, the output signals and interactive signals expected to appear in each state of the state machine are listed in a table, and then the corresponding first SVA assertions are written according to the expected changes of each signal in the table. When the simulation module is used to simulate the running state machine, each first SVA assertion automatically checks the timing of the corresponding signals of the state machine in each state, automatically determines whether the assertion is successful or failed, and quickly verifies the output signals and interactive signals of the state machine, thereby improving the verification efficiency. Compared with the traditional scoreboard comparison verification method, the scheme of the present invention is applied to the block-level or even UT-level digital integrated circuit verification. Based on the SVA assertion, according to the timing of each signal of the state machine, a large number of output signals and interactive signals generated by the state machine in each state are verified, so that the verification can be completed in a shorter time, and the verification efficiency is higher.

[0047] The specific operation methods of the above-mentioned functional modules can refer to the description of the verification method of the state machine in the digital integrated circuit design, which will not be repeated here. In addition, regarding the setting method of the acquisition module, the first SVA assertion generation module, the simulation module, the first SVA assertion judgment module and the statistical determination module, each functional module not only includes hardware including storage media and logical operations, but also includes software for storing and running corresponding functions.

[0048] In addition, refer to Figure 2, the acquisition module can also be used to obtain all the expected flip situations of the state machine and add them to the table. The verification system can also include a second SVA assertion generation module and a second SVA assertion judgment module; wherein the second SVA assertion generation module is used to write the corresponding second SVA assertion according to each flip situation in the table; the second SVA assertion judgment module is used to automatically determine whether each second SVA assertion is a successful assertion or a failed assertion according to the expected flip situation corresponding to each second SVA assertion while simulating the state machine. The statistical determination module is also used to determine that all the flip situations expected to occur in the state machine meet the expected flip when all the second SVA assertions are successful; the statistical determination module is also used to determine that the state machine has a flip situation that does not meet the expectations when the second SVA assertion fails, interrupt the simulation, and print an error message. All possible flip situations of the state machine are also verified based on the SVA assertion, so that when there are a large number of flip situations in the state machine, all flip situations of the state machine can be verified in a shorter time, and the verification efficiency is higher. The specific operation methods of the second SVA assertion generation module and the second SVA assertion judgment module mentioned above can refer to the description of the verification method of the state machine in the digital integrated circuit design mentioned above, and will not be repeated here. In addition, in the above-mentioned setting method of the second SVA assertion generation module and the second SVA assertion judgment module, each functional module not only includes hardware including storage media and logical operations, but also includes software for storing and running corresponding functions.

[0049] In addition, reference Figure 2 and Figure 3 , the verification system may also include: a viewing module, which is used to view the coverage of all the second SVA assertions listed in the coverage table when all the second SVA assertions are successful. The statistical determination module is also used to output the verification result that the state machine design meets the standard when the coverage reaches 100% and all the first SVA assertions are successful. And the statistical determination module is also used to print errors when the coverage is less than 100%. When it is determined that all the flip situations that may occur in the state machine meet the expected flips, it is further checked whether the second SVA assertion can completely cover all the flip situations listed in the table to prevent the existing flip situations from being unverified and improve the accuracy of the verification results. The specific operation method of the above-mentioned viewing module can refer to the aforementioned description of the verification method of the state machine in the digital integrated circuit design, and will not be repeated here. In addition, in the above-mentioned setting method of the viewing module, each functional module not only includes hardware including storage media and logical operations, but also includes software for storing and running corresponding functions.

[0050] It should be additionally explained that the verification system of the state machine in the digital integrated circuit design may also include other types of functional modules to implement the functions of the corresponding operations in the above-mentioned verification method of the state machine in the digital integrated circuit design.

[0051] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A method for verifying a state machine in a digital integrated circuit design, characterized in that: include: Obtain the output signals and interaction signals expected to appear in each state of the state machine and form a table; According to the expected changes of each signal in the table, write a corresponding first SVA assertion; Using a simulation module to simulate and run the state machine; According to the signal timing corresponding to each first SVA assertion, automatically determine whether the assertion is successful or failed, so as to verify the output signal and interaction signal of the state machine; If all first SVA assertions are successful, it is determined that the output signals and interaction signals expected to appear in each state of the state machine all conform to the expected changes; If the first SVA assertion fails, it is determined that the output signal or interaction signal expected to appear when the state machine is in a certain state does not conform to the expected change, the simulation is interrupted, and an error message is printed.

2. The verification method according to claim 1, characterized in that: Also includes: If there is a first SVA assertion failure, after receiving the modified state machine, the modified state machine is re-verified according to the verification method until all first SVA assertions are successful.

3. The verification method according to claim 1, characterized in that: Also includes: Obtain all possible flip situations that may occur in the state machine and add them to the table; According to each flip situation in the table, write a corresponding second SVA assertion; While the state machine is being simulated and run using the simulation module, automatically determining whether the assertion is successful or failed according to the expected flip situation corresponding to each second SVA assertion; If all second SVA assertions are successful, it is determined that all flip situations that may be expected to occur in the state machine meet the expected flip; If the second SVA assertion fails, it is determined that the state machine has an unexpected flip condition, the simulation is interrupted, and an error message is printed.

4. The verification method according to claim 3, characterized in that: If all second SVA assertions are successful, the verification method further includes: Check the coverage of all second SVA assertions for all flip situations listed in the table; Determining whether the coverage rate reaches 100%; If it reaches 100% and all the first SVA assertions are successful, then the verification result that the state machine design meets the standard is output; If it is less than 100%, an error message is printed.

5. The verification method according to claim 4, characterized in that: Also includes: If there is a second SVA assertion failure, or the coverage is less than 100%, after receiving the modified state machine, the modified state machine is re-verified according to the verification method until all second SVA assertions are successful and the coverage reaches 100%.

6. The verification method according to claim 3, characterized in that: The writing of the corresponding second SVA assertion according to each flip situation in the table includes: A scripting language tool is used to extract all the flipping conditions in the table and automatically generate the corresponding second SVA assertions.

7. The verification method according to claim 6, characterized in that: The scripting language tool is Python.

8. A verification system for a state machine in a digital integrated circuit design, characterized in that: include: The acquisition module is used to obtain the output signals and interaction signals expected to appear in each state of the state machine and form a table; A first SVA assertion generating module, configured to write a corresponding first SVA assertion according to the expected changes of each signal in the table; A simulation module, used for simulating and running the state machine; A first SVA assertion judgment module, used for automatically judging whether each first SVA assertion is an assertion success or an assertion failure according to a signal timing corresponding to each first SVA assertion, so as to verify an output signal and an interaction signal of the state machine; The statistical determination module is used to determine that the output signals and interaction signals expected to appear in each state of the state machine conform to the expected changes when all the first SVA assertions are successful; and is also used to interrupt the simulation and print an error message when the first SVA assertion fails and the output signals or interaction signals expected to appear in a certain state of the state machine do not conform to the expected changes.

9. The verification system according to claim 8, characterized in that: The acquisition module is also used to acquire all possible flip situations that are expected to occur in the state machine and add them to the table; The verification system further includes: a second SVA assertion generation module and a second SVA assertion judgment module; wherein the second SVA assertion generation module is used to write corresponding second SVA assertions according to each flip situation in the table; the second SVA assertion judgment module is used to automatically judge whether each second SVA assertion is asserted successfully or failed according to the expected flip situation corresponding to each second SVA assertion while simulating and running the state machine; The statistical determination module is also used to determine that all flip situations that may be expected to occur in the state machine meet the expected flip when all second SVA assertions are successful; The statistical determination module is also used to determine that the state machine has an unexpected flip situation when the second SVA assertion fails, interrupt the simulation, and print error information.

10. The verification system according to claim 9, characterized in that: Also includes: A checking module, used for checking the coverage of all the second SVA assertions covering all the flip situations listed in the table when all the second SVA assertions are successful; The statistical determination module is also used to output a verification result that the state machine design meets the standard when the coverage reaches 100% and all first SVA assertions are successful; The statistical determination module is also used for printing errors when the coverage rate is less than 100%.

Images