Storage device

Abstract

A storage device includes a storage unit capable of holding data, and an ECC circuit capable of generating a correction code and detecting an error based on the correction code. The storage unit is accessed by a pipelined operation. The pipelined operation includes at least four pipeline stages, including: a read cycle of reading data from the storage unit, an ECC cycle of performing generation or error detection of the correction code for the storage unit in the ECC circuit, a wait cycle during which no processing for data related to the storage unit is performed, and a write cycle of writing data to the storage unit.

Description

Technical Field

[0001] The present disclosure relates to a storage device. Background Art

[0002] Due to the accelerating speed, increasing reliability, and growing complexity of information processing, error correction is required to be performed in a memory system. In recent years, a resistive change type memory that stores "0" data or "1" data according to the difference in resistance value has been expected as a next-generation memory. The resistive change type memory includes a magnetic resistive random access memory (MRAM), a resistive random access memory (ReRAM), a phase change RAM (PCM), and the like. They are different in the mechanism of changing the resistance value.

[0003] MRAM has a magnetic tunnel junction (MTJ) as a constituent element. The MTJ has a configuration in which an insulating layer is provided between a fixed layer and a free layer. The MTJ stores data through the tunneling magnetoresistance effect, in which the magnitude of the resistance on the current path through the MTJ depends on two states, that is, whether the magnetization state of the free layer is parallel or antiparallel to the magnetization direction of the fixed layer. Data rewriting is performed by the spin transfer torque (STT) method, in which an electron spin torque is applied to the free layer to cause magnetization reversal.

[0004] ReRAM includes a metal oxide thin film sandwiched between electrodes. Then, by applying a voltage to the metal oxide thin film, metal ions are deposited as filaments, and a conduction path is generated in the oxide thin film. The resistance value of the storage cell differs depending on the presence or absence of the conduction path, and data is stored according to the difference in resistance value.

[0005] PCM stores data by utilizing the difference in resistance value between the crystalline phase and the amorphous phase of a substance. In PCM, a resistance change layer (e.g., chalcogenide) can be rapidly heated and cooled by passing a current to change from the crystalline phase to the amorphous phase, and can return from the amorphous phase to the crystalline phase by maintaining the crystallization temperature for a certain period of time.

[0006] In any memory, data is read by passing a current and reading the resistance value of the storage cell. That is, a larger current flows when rewriting data, and a smaller current flows when reading data. That is, precise control of voltage and current is very important when rewriting and reading data. Therefore, write errors, read errors, or data corruption (read interference) may occur during reading. Therefore, in order to improve operation reliability, it is preferable to use an error correction code.

[0007] An error correction code achieves t-bit error correction by adding k bits of code to m bits of data (where m, k, and t are natural numbers of 1 or greater). The correction ability is defined as follows by the minimum Hamming distance dmin (the minimum value of the number of bits with different values in the (m + k)-bit codeword).

[0008] dmin ≥ 2t + 1

[0009] For example, technologies related to MRAM and error correction as described above are described in Japanese Patent Application Laid-Open No. 2018-152146 and International Publication No. WO2007 / 046349. Summary of the Invention

[0010] According to one aspect of the present invention, there is provided a storage device including a storage unit capable of holding data, and an ECC circuit capable of generating a correction code and detecting an error based on the correction code. The storage unit is accessed by a pipelined operation. The pipelined operation includes at least four pipeline stages, including: a read cycle for reading data from the storage unit, an ECC cycle for generating or detecting an error of the correction code in the ECC circuit for the storage unit, a wait cycle during which no processing of data related to the storage unit is performed, and a write cycle for writing data to the storage unit. Brief Description of the Drawings

[0011] Figure 1 is a block diagram of a processor system according to a first embodiment of the present disclosure;

[0012] Figure 2 is a circuit diagram of a storage cell array according to a first embodiment of the present disclosure.

[0013] Figure 3A is a schematic diagram of a storage cell according to a first embodiment of the present disclosure;

[0014] Figure 3B is another schematic diagram of a storage cell according to a first embodiment of the present disclosure;

[0015] Figure 4A is a flowchart of a master read operation according to a first embodiment of the present disclosure;

[0016] Figure 4B is a flowchart of a master write operation according to a first embodiment of the present disclosure;

[0017] Figure 4C is another flowchart of a master read operation according to a first embodiment of the present disclosure;

[0018] Figure 4D is another flowchart of a master write operation according to a first embodiment of the present disclosure;

[0019] Figure 4E is a flowchart of a master write operation and a master read operation according to a first embodiment of the present disclosure;

[0020] Figure 5 is a timing diagram of various signals when accessing a storage device according to a first embodiment of the present disclosure;

[0021] Figure 6 is a block diagram of a processor system according to a second embodiment of the present disclosure;

[0022] Figure 7 is a flowchart of a master write operation according to a second embodiment of the present disclosure;

[0023] Figure 8 is a conceptual diagram of a master write operation according to a second embodiment of the present disclosure;

[0024] Figure 9 is a flowchart of a master write operation according to a third embodiment of the present disclosure;

[0025] Figure 10 is a timing diagram of various signals when accessing a storage device according to a third embodiment of the present disclosure;

[0026] Figure 11A is a block diagram of a storage device according to a fourth embodiment of the present disclosure;

[0027] Figure 11B is another block diagram of a storage device according to a fourth embodiment of the present disclosure;

[0028] Figure 11C is another block diagram of a storage device according to a fourth embodiment of the present disclosure;

[0029] Figure 11D is another block diagram of a storage device according to a fourth embodiment of the present disclosure;

[0030] Figure 11E is another block diagram of a storage device according to a fourth embodiment of the present disclosure;

[0031] Figure 11F is another block diagram of a storage device according to a fourth embodiment of the present disclosure;

[0032] Figure 12A is another block diagram of a storage device according to a fourth embodiment of the present disclosure;

[0033] Figure 12B is another block diagram of a storage device according to a fourth embodiment of the present disclosure;

[0034] Figure 12CAnother block diagram of a storage device according to a fourth embodiment of the present disclosure;

[0035] Figure 12D Another block diagram of a storage device according to a fourth embodiment of the present disclosure;

[0036] Figure 12E Another block diagram of a storage device according to a fourth embodiment of the present disclosure;

[0037] Figure 12F Another block diagram of a storage device according to a fourth embodiment of the present disclosure;

[0038] Figure 13A Another block diagram of a storage device according to a fourth embodiment of the present disclosure;

[0039] Figure 13B Another block diagram of a storage device according to a fourth embodiment of the present disclosure;

[0040] Figure 13C Another block diagram of a storage device according to a fourth embodiment of the present disclosure;

[0041] Figure 13D Another block diagram of a storage device according to a fourth embodiment of the present disclosure;

[0042] Figure 13E Another block diagram of a storage device according to a fourth embodiment of the present disclosure;

[0043] Figure 14 A block diagram of a processor system according to a modification example of the first to fourth embodiments of the present disclosure; and

[0044] Figure 15 A block diagram of another processor system according to a modification example of the first to fourth embodiments of the present disclosure. Detailed Description of the Invention

[0045] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. In the drawings, the same or equivalent elements will be denoted by the same reference numerals, and redundant description thereof will be omitted.

[0046] <First Embodiment>

[0047] A storage device according to a first embodiment of the present disclosure will be described.

[0048] <Configuration>

[0049] First, reference will be made to Figure 1 to describe the configuration of the storage device according to this embodiment. Figure 1 is a block diagram of a processor system 1 according to this embodiment, for example.

[0050] As shown in the figure, the processor system 1 includes a bus master device 10 and a storage device 20, both of which are communicably connected to each other via a bus. The bus master device 10 is, for example, a processor (such as a CPU or a DMA controller). The bus master device 10 instructs the storage device 20 to write or read data. The storage device 20 is, for example, a resistive change type non-volatile memory, and in this example, it is an STT-MRAM. For example, the storage device 20 serves as a cache memory or a main memory of the processor.

[0051] The bus master device 10 sends a clock and a control signal to the storage device 20, and also sends write data to the storage device 20 during a write operation. The storage device 20 operates according to the signals received from the bus master device 10, stores the received write data during a write operation, and transfers the data read from a specified address to the bus master device 10 during a read operation.

[0052] Next, details of the configuration of the storage device 20 will be described. As Figure 1 shown, the storage device 20 includes a memory cell array 21, a read address buffer 22, a write address buffer 23, a decoder (row decoder and column decoder) 24, a write data buffer 25, a read data buffer 26, a sense amplifier 27, and a write driver 28, and is provided with an error checking and correction (ECC) circuit 29, selectors 30, 31, and 32, and a controller 33.

[0053] The memory cell array 21 includes a plurality of memory cells. The memory cells are arranged in a matrix and are associated with rows and columns. The memory cells store data in a non-volatile manner. Details of the configuration of the memory cell array 21 will be described later with reference to Figure 2 description.

[0054] The address buffer 22 holds the addresses (row address and column address) of the memory cell array 21 received from the bus master device 10 during a data read operation and a data write operation. The write address buffer 23 receives the address from the read address buffer 22 and holds the address. Hereinafter, the read address buffer 22 and the write address buffer 23 may be simply referred to as the address buffer 22 and the address buffer 23, respectively.

[0055] The selector 30 selects the address held by the address buffer 22 or 23 based on, for example, an instruction from the controller 33. Then, the selector 30 transfers the selected address to the decoder 24.

[0056] The decoder 24 decodes the row address and column address received from the selector 30. Then, the decoder 24 selects the row direction and column direction in the memory cell array 21 based on the decoding result. With this configuration, the memory cells to be read or written are selected. Hereinafter, the unit of the decoder 24 that selects the row direction will be referred to as the row decoder 24A, and the unit of the decoder 24 that selects the column direction will be referred to as the column decoder 24B.

[0057] The sense amplifier 27 reads data from the selected memory cells, reads out and amplifies the read data.

[0058] The write driver 28 applies a voltage or supplies a current to the selected memory cells based on the write data. With this configuration, data is written to the selected memory cells.

[0059] The ECC circuit 29 performs ECC processing on the read data and write data. The ECC circuit 29 includes an error correction circuit 34 and a parity code generator 35. The parity code generator 35 generates redundant bits (e.g., parity bits) based on the write data at the time of writing data. Then, the generated parity bits are added to the write data, and this write data with parity bits is transmitted to the write driver 28. The error correction circuit 34 also receives the read data from the sense amplifier 27. Then, the error correction circuit 34 generates a syndrome based on the received read data and detects an error. Then, when an error is detected, the error correction circuit 34 corrects the error.

[0060] The write data buffer 25 holds the write data in the memory cells. The read data buffer 26 holds the data read from the memory cells. Hereinafter, the write data buffer 25 and the read data buffer 26 may be simply referred to as the data buffer 25 and the data buffer 26, respectively.

[0061] The selector 32 selects the output of the error correction circuit 34 of the ECC circuit 29 or the data held in the write data buffer 25 based on an instruction from, for example, the controller 33. Then, the selector 32 transmits the selected data to the read data buffer 26.

[0062] The selector 31 selects the write data received from the bus master device 10 or the data held in the read data buffer 26 based on an instruction from, for example, the controller 33. Then, the selector 31 transmits the selected data to the write data buffer 25.

[0063] The controller 33 controls the operation of the entire storage device 20. For example, the controller 33 operates in synchronization with the clock received from the bus master device 10. Then, the controller 33 controls the operations of the selectors 30, 31, and 32 as described above. The controller 33 performs a data write operation and a data read operation in the storage device 20 by pipeline operation. This will be described later with reference toFigure 4A The details of this operation are described in and subsequent figures.

[0064] Figure 2 is a circuit diagram of a partial area of the circuit diagram of the memory cell array 21 according to the present embodiment. As shown, the memory cell array 21 includes a plurality of memory cells MC arranged in a matrix. Each memory cell MC includes a selection transistor ST and a memory element ME. For example, the selection transistor ST is a MOS transistor. The memory element ME is a variable resistance element and is an MTJ element in this example. Then, the source of the selection transistor ST is connected to one end of the memory element ME.

[0065] In the memory cell array 21, the gates of the selection transistors ST of the memory cells MC in the same row are commonly connected to the same word line WLj (j is a natural number from 1 to N, and N is a natural number of 2 or more). The drains of the selection transistors ST of the memory cells MC in the same column are commonly connected to the same bit line BLk (k is a natural number from 1 to M, and M is a natural number of 2 or more). In addition, the other ends of the memory elements ME of the memory cells MC in the same column are commonly connected to the same source line SLk.

[0066] In the above configuration, one of the word lines WL is selected by the row decoder 24A during the data write operation and the data read operation. A voltage is applied to the selected word line WL by the row decoder 24A, and the selection transistor ST connected to the selected word line WL is turned on (ON).

[0067] During the data write operation and the data read operation, the bit line BL or the source line SL is selected by a column selector (not shown). The selection operation of the column selector is based on the decoding result in the column decoder 24B. Then, when reading data from the memory cell MC, the selected bit line BL is connected to the sense amplifier (S / A) 27, and the selected source line SL is grounded. When writing data to the memory cell MC, the selected bit line BL and the source line SL are connected to the write driver (W / D) 28.

[0068] Figure 3A and Figure 3B is a schematic diagram of the memory cell MC, and particular attention is paid to the configuration of the MTJ element. As shown, the MTJ element includes two ferromagnetic films 40 and 41 and a tunnel insulating film 42 between the two ferromagnetic films. The ferromagnetic film 40 is a fixed layer (also referred to as a reference layer) whose magnetization direction is fixed. On the other hand, the ferromagnetic film 41 is a free layer (also referred to as a storage layer) whose magnetization direction can be changed by current. In this example, the fixed layer 40 is connected to the source of the selection transistor ST, and the free layer 41 is connected to the bit line BL.

[0069] The MTJ element can take two states, asFigure 3A and Figure 3B as shown. In the figure, the arrows shown on the ferromagnetic films 40 and 41 indicate the magnetization directions. In Figure 3A the example of, the magnetization directions of the fixed layer 40 and the free layer 41 are parallel. Therefore, when the magnetization directions of the two layers are in a parallel state, the resistance value between the bit line BL and the source line SL is small. On the contrary, in Figure 3B the example of, the magnetization directions of the fixed layer 40 and the free layer 41 are opposite to each other. In this way, when the magnetization directions of the two layers are in an antiparallel state, the resistance value between the bit line BL and the source line SL is large. The MTJ element utilizes this change in the resistance value to hold "0" data and "1" data.

[0070] Data rewriting is performed by supplying current to the MTJ element. For example, by causing a constant current to flow from the bit line BL to the source line SL, the MTJ element is brought into a parallel state. On the contrary, by causing a constant current to flow from the source line SL to the bit line BL, the MTJ element is brought into an antiparallel state. Then, current is supplied to the MTJ element through the write driver 28, and the direction of the current flowing through the write driver 28 is determined based on the write data.

[0071] Data reading is performed by detecting whether current flows through the bit line BL. That is, when the MTJ element is in a parallel state, current flows from the bit line BL to the source line SL via the memory cell MC. On the other hand, when the MTJ element is in an antiparallel state, almost no current flows. The sense amplifier 27 reads and amplifies this current difference.

[0072] In Figure 3A and 3B the example of, the fixed layer 40 is provided on the source line SL side, while the free layer 41 is provided on the bit line BL side. However, the free layer 41 can be provided on the source line SL side, and the fixed layer 40 can be provided on the bit line BL side.

[0073] "Operation"

[0074] Next, the operation of the storage device 20 according to the present embodiment will be described. The operation of the storage device 20 corresponding to a write command from the bus master device 10 includes reading data from the memory cell MC and writing data to the memory cell MC. Similarly, the operation of the storage device 20 corresponding to a read command from the bus master device 10 also includes writing data to the memory cell MC and reading data from the memory cell MC.

[0075] Accordingly, in the following text, a series of processes executed in response to a write command and a read command received from the bus master device 10 are respectively referred to as a master write operation and a master read operation. With this configuration, the master read operation and the master write operation are respectively distinguished from a read operation for reading data from the memory cell MC and a write operation for writing data to the memory cell MC.

[0076] First, refer to Figure 4A Describe the master read operation. Figure 4A is a flowchart showing the master read operation according to the present embodiment. In Figure 4A The steps described by the double solid line box are the stages in which the sense amplifier 27 operates. The steps described by the dashed box and the solid box are the stages in which the write driver 28 operates.

[0077] As shown in the figure, the master read operation includes four pipeline stages. These four pipeline stages include: a first pipeline stage for executing a read cycle, a second pipeline stage for executing an ECC cycle, a third pipeline stage for executing a wait cycle, and a fourth pipeline stage for executing a write cycle.

[0078] First, the storage device 20 that receives the master read command from the bus master device 10 executes a read cycle in the first pipeline stage. That is, data is read from the memory cell MC corresponding to the address specified by the bus master device 10 (step S10). Specifically, the address sent from the bus master device 10 is held in the address buffer 22, and the selector 30 selects the address held in the address buffer 22 and transfers the address to the decoder 24. The row decoder 24A selects an arbitrary word line WL, and the column decoder 24B selects an arbitrary bit line BL and a source line SL. Then, the selected bit line BL is charged, and the source line SL is grounded. As a result, the sense amplifier 27 reads the current flowing through the selected bit line BL. For example, based on the current flowing through the selected bit line BL, the sense amplifier 27 determines whether the data held in the selected memory cell MC is "0" or "1" according to whether the resistance value of the selected memory cell MC is greater than or less than a reference value.

[0079] Next, the storage device 20 executes an ECC cycle in the second pipeline stage. That is, the error correction circuit 34 determines whether an error exists in the data read in step S10, and corrects the error when an error is detected (step S11). The selector 32 selects the error correction circuit 34, and the data for which error correction has been performed is transmitted to the data buffer 26. Then, when the second pipeline stage ends, the data is output from the data buffer 26 to the bus master device 10 as the read data from the storage device 20. In the second pipeline stage, the data held in the data buffer 26 is transmitted to the parity code generator 35 through the selector 31 and the data buffer 25. Then, the parity code generator 35 generates redundant data (parity bit) based on the transmitted data.

[0080] Next, the storage device 20 executes a wait cycle in the third pipeline stage (step S12). That is, at least the decoder 24, the sense amplifier 27, the write driver 28, and the ECC circuit 29 do not perform operations related to the master read operation. More specifically, based on the master read command, the sense amplifier 27 does not perform a read operation, the write driver 28 does not apply voltage to the bit line BL and the source line SL, and the ECC circuit 29 does not perform ECC processing.

[0081] Next, the storage device 20 executes a write cycle in the fourth pipeline stage. That is, a data write operation (write-back operation) is performed (step S13). In step S13, the selector 30 selects the address transmitted from the address buffer 22 to the address buffer 23. Then, the decoder 24 selects an arbitrary word line WL, bit line BL, and source line SL based on this address. Then, based on the data transmitted from the parity code generator 35, the write driver 28 supplies current to the selected memory cell MC in the direction from the bit line BL to the source line SL or in the opposite direction. That is, when an error is found in the read data in step S11, the data held in the corresponding memory cell MC is not retained as it is, but the data corrected in step S11 is written back to the memory cell MC. This is the processing of step S13.

[0082] Next, reference will be made to Figure 4B describe the master write operation. Figure 4B is a flowchart showing the flow of the master write operation according to the present embodiment.

[0083] As shown in the figure, the master write operation includes four pipeline stages. These four pipeline stages include: a first pipeline stage that executes a read cycle, a second pipeline stage that executes a wait cycle, a third pipeline stage that executes an ECC cycle, and a fourth pipeline stage that executes a write cycle.

[0084] First, the storage device 20 receiving the master write command from the bus master 10 performs a read cycle in the first pipeline stage. That is, data is read from the memory cell MC corresponding to the address specified by the bus master 10 (step S20). This operation is the same as step S10 in the master read operation. However, in step S20, this operation is performed until error correction is performed in the error correction circuit 34.

[0085] Next, the storage device 20 performs a waiting cycle in the second pipeline stage (step S21). That is, at least the decoder 24, the sense amplifier 27, the write driver 28, and the ECC circuit 29 do not perform operations related to the master write operation. More specifically, based on the master write command, the sense amplifier 27 does not perform a read operation, the write driver 28 does not apply a voltage to the bit line BL and the source line SL, and the ECC circuit 29 does not perform an ECC process.

[0086] Next, the storage device 20 performs an ECC cycle in the third pipeline stage. That is, an ECC process (step S22) is performed. In the third pipeline stage, the data that has been error-corrected in step S20 is transmitted to the data buffer 25 via the selectors 32 and 31 and the data buffer 26. In addition, the write data received from the bus master 10 is transmitted to the data buffer 25 via the selector 31. Then, in the data buffer 25, the data from the data buffer 26 and the data from the bus master 10 are combined to generate the write data. This operation is used to supplement the missing bits with the data obtained from the data buffer 26 when the data provided from the bus master 10 is less than the number of bits required to generate the parity bits. This will be described in the fourth embodiment. Subsequently, the obtained write data is transmitted to the check code generator 35, and the check code generator 35 generates the parity bits.

[0087] Then, the memory device 20 performs a write cycle in the fourth pipeline stage. That is, a data write operation is performed (step S23). That is, the bit string of write data and the parity bit as a predetermined write unit are written into the memory cell MC connected to the selected word line WL and the selected bit line BL.

[0088] Next, we will refer to Figure 4C , Figure 4D and Figure 4E The pipeline operation of the memory device 20 is described when the bus master device 10 continuously issues a master read command and / or a master write command. Figure 4C , Figure 4D and Figure 4E 1 and 2 are flowcharts respectively showing a case where a master read command is issued continuously, a case where a master write command is issued continuously, and a case where a master write command and a master read command are issued continuously.

[0089] First, a case of continuously issuing a master read command will be described with reference to Figure 4C As shown in the figure, it is assumed that the bus master device 10 first issues a first master read command for the address ADD[n], and then issues a second master read command for the address ADD[m] (each of n and m is a natural number of 1 or greater). Then, the storage device 20 executes a first pipeline stage corresponding to the first master read command during the time period from t1 to t2, and reads data from the memory cell MC.

[0090] Subsequently, the storage device 20 executes a second pipeline stage corresponding to the first master read command during the time period from t2 to t3, and performs error correction and parity bit generation.

[0091] Next, during the time period from t3 to t4, the storage device 20 executes a third pipeline stage corresponding to the first master read command. That is, access to the memory cell array 21 related to the first master read command is prohibited. At the same time, the storage device 20 executes a first pipeline stage corresponding to the second master read command. During the time period from t3 to t4, a wait cycle is executed for the first master read command, but a read cycle is executed for the second master read command. Therefore, the processing unit (decoder 24 or sense amplifier 27) related to the read operation does not execute the processing corresponding to the first master read command, but executes the processing related to the data reading corresponding to the second master read command.

[0092] Next, during the time period from t4 to t5, the storage device 20 executes a fourth pipeline stage corresponding to the first master read command. That is, the storage device 20 writes the data that has been error-corrected and has parity bits added based on the first master read command into the memory cell MC. At the same time, the storage device 20 executes a second pipeline stage corresponding to the second master read command.

[0093] Thereafter, the storage device 20 executes a third pipeline stage corresponding to the second master read command during the time period from t5 to t6, and executes a fourth pipeline stage corresponding to the second master read command during the period starting from t6.

[0094] In this way, in two consecutive pipeline operations, the four stages of the two stages of the sense amplifier 27 operation (from time t1 to t2 and from time t3 to t4) and the two stages of the write driver 28 operation (from time t4 to t5 and the time starting from t6) do not overlap in time. Therefore, bus contention can be avoided.

[0095] Next, with reference to Figure 4DDescribe the situation of continuously issuing master write commands. As shown in the figure, assume that the bus master device 10 first issues a first master write command for the address ADD[n], and then issues a second master write command for the address ADD[m]. Then, during the time period from t1 to t2, the storage device 20 executes the first pipeline stage corresponding to the first master write command and reads data from the memory cell MC.

[0096] Subsequently, during the time period from t2 to t3, the storage device 20 executes the second pipeline stage corresponding to the first master write command. That is, access to the memory cell array 21 related to the first master write command is prohibited.

[0097] Next, during the time period from t3 to t4, the storage device 20 executes the third pipeline stage corresponding to the first master write command. That is, the storage device generates write data based on the data received from the bus master device 10 and the data received from the data buffer 26, and further generates a parity bit. At the same time, the storage device 20 executes the first pipeline stage corresponding to the second master write command.

[0098] Next, during the time period from t4 to t5, the storage device 20 executes the fourth pipeline stage corresponding to the first master write command. That is, the storage device 20 writes the data that has been error-corrected and has a parity bit added based on the first master write command into the memory cell MC. At the same time, the storage device 20 executes the second pipeline stage corresponding to the second master write command. During the time period from t4 to t5, a wait cycle is executed for the second master write command, but a write cycle is executed for the first master write command. Therefore, the processing unit (decoder 24 or write driver 28) related to the write operation does not execute the processing corresponding to the second master write command, but executes the processing related to the data writing corresponding to the first master write command.

[0099] Thereafter, the storage device 20 executes the third pipeline stage corresponding to the second master write command during the time period from t5 to t6, and executes the fourth pipeline stage corresponding to the second master write command during the period starting from t6.

[0100] Also in this example, in two consecutive pipeline operations, the four stages of the two stages of the sense amplifier 27 operation (from time t1 to t2 and from time t3 to t4) and the two stages of the write driver 28 operation (from time t4 to t5 and the time starting from t6) do not overlap in time.

[0101] Next, refer to Figure 4EDescribe the case where a master write command is first issued and then a master read command is issued successively. As shown in the figure, assume that the bus master device 10 first issues a master write command for the address ADD[n], and then issues a master read command for the address ADD[m]. Even in this case, the operation phases of the sense amplifier 27 are the time periods from time t1 to t2 and from time t3 to t4, and the operation phases of the write driver 28 are the time periods from time t4 to t5 and from time t6 onwards. Therefore, the overlap of these four phases is suppressed.

[0102] Figure 5 is a timing diagram showing the states of the clock CLK, address ADD, command CMD, read data RDAT, and write data WDAT transmitted and received between the bus master device 10 and the storage device 20, and the five pipelines PP1 to PP5 executed in the storage device 20. In Figure 5 it shows the case where the bus master device 10 sequentially issues the first master read command RD1, the second master read command RD2, the first master write command WR1, the second master write command WR2, and the third master read command RD3.

[0103] As shown in the figure, at time t1, the bus master device 10 issues the read target address ADD[n] together with the master read command RD1. Then, at time t1, the storage device 20 executes the first pipeline operation PP1 in response to the master read command RD1 corresponding to the address ADD[n]. At time t3, when the ECC process ends, the data in the data buffer 26 is output to the bus master device 10 as the read data RDAT[n] from the storage device 20.

[0104] Subsequently, at time t3, the bus master device 10 issues the read target address ADD[n + 1] together with the master read command RD2. Then, at time t3, the storage device 20 executes the second pipeline operation PP2 in response to the master read command RD2 corresponding to the address ADD[n + 1]. At time t5, when the ECC process ends, the data in the data buffer 26 is output to the bus master device 10 as the read data RDAT[n + 1] from the storage device 20.

[0105] In addition, at time t5, the bus master device 10 issues the write target address ADD[m] together with the master write command WR1. Then, at time t5, the storage device 20 executes the third pipeline operation PP3 in response to the master write command WR1 corresponding to the address ADD[m]. Then, at time t7, when the write data WDAT[m] is received from the bus master device 10, the ECC process is executed, and the data is written into the memory cell MC during the time period from time t8 to time t9. The same applies to the following text.

[0106] Effect of the Present Embodiment

[0107] As described above, the storage device according to the present embodiment can improve operation reliability. The following will describe such an effect.

[0108] The storage device according to the present embodiment includes four stages of a read cycle S10, an ECC cycle S11, a wait cycle S12, and a write cycle S13, and four types of pipelines to respond to a read request from the bus master device 10. Similarly, it includes four stages of a read cycle S20, a wait cycle S21, an ECC cycle S22, and a write cycle S23, and four types of pipelines to respond to a write request from the bus master device 10.

[0109] Therefore, the data write-back cycle (write cycle S13) caused by error correction during reading can be executed in parallel with any processing stage of the next pipeline operation and is invisible to the bus master device 10. That is, the bus master device 10 can issue the next command without waiting for the data write-back process. Therefore, the operation speed of the storage device 20 can be increased. In this case, by providing the wait cycles S12 and S21, contention between the bus between the bus master device 10 and the storage device 20 and the bus inside the storage device 20 can be suppressed. As a result, when viewed from the perspective of the bus master device 10, the generation of random weights can be suppressed. In addition, the number of required cycles (the number of pipeline stages) can be made the same between the master read operation and the master write operation, and an operation very suitable for a single-chip microcomputer or the like that requires a constant operation cycle can be achieved. In this regard, an MRAM that is a non-volatile memory and can operate at high speed can be used as the high-speed cache memory of the processor. Then, by applying the present embodiment to the MRAM for such an application, the operation reliability of the processor can be improved. Furthermore, in the MRAM, it is important to ensure a sufficient difference between the resistance values of the memory cells holding "0" data and the memory cells holding "1" data. This is because by increasing this difference, the data read reliability can be improved. However, it may be difficult to increase the difference between the resistance values. Then, the difference between the read current when reading "0" data and the read current when reading "1" data becomes relatively small, and the possibility of misreading may increase. In addition, when the write time is shortened for high-speed operation, the possibility of miswriting may increase. Therefore, by using a correction code as in the present embodiment, the operation reliability of the MRAM can be significantly improved.

[0110] In addition, by preparing address buffers and data buffers for reading and writing, another operation cycle (e.g., an ECC cycle or a wait cycle) can be inserted between the read cycle and the write cycle, and as a result, the above four pipeline stages can be achieved.

[0111] In addition, among these four pipeline stages, the sense amplifier 27 operates in the first half (steps S10 and S20), and the write driver 28 operates in the second half (steps S13 and S23). Therefore, the four pipeline stages can be executed without interruption.

[0112] <Second Embodiment>

[0113] Next, a storage device according to a second embodiment of the present disclosure will be described. In this embodiment, in the master read operation described in the first embodiment for the bit string of the data read from the storage cell array 21, only the bits having bit errors are rewritten to the storage cell MC. Only the points different from the first embodiment will be described below.

[0114] <Configuration>

[0115] Figure 6 is a block diagram of the processor system 1 according to this embodiment. As shown, the storage device 20 according to this embodiment further includes a bypass path for transmitting the data read by the sense amplifier 27 to the Figure 1 write driver 28 described in the first embodiment. Other configurations are similar to those of the first embodiment.

[0116] <Operation>

[0117] Figure 7 is a flowchart of the master read operation according to this embodiment. As shown, the difference from the Figure 4A described in the first embodiment is that in the fourth pipeline stage, the read data from the storage cell MC and the data after error correction are compared (step S14).

[0118] That is, in the fourth pipeline stage, the corrected data added with the parity bit generated in the third pipeline stage is transmitted to the write driver 28. In this embodiment, the data read in the first pipeline stage is transmitted to the write driver 28 through the Figure 6 bypass path described in. As long as this transmission timing does not interfere with the next pipeline operation, this transmission timing can be executed in any one of the first to fourth pipeline stages. Then, the write driver 28 compares the data transmitted from the check code generator 35 with the data transmitted from the sense amplifier 27, and performs a write operation only on the bit lines corresponding to the bits whose values have changed.

[0119] The above operation will be briefly described using a Figure 8 specific example in. Figure 8 is a schematic diagram of the data processed by the write driver 28.

[0120] As shown in the figure, assume that the data DAT read by the sense amplifier 27 is 8-bit data "00110011". Assume that the bits after error correction and addition of parity bits, excluding the parity bits of the data DATP, are 8-bit data "00111011". Then, the write driver 28 compares the 8-bit data DAT with the 8-bit data DATP. Then, the only bit that is different between the data DAT and DATP is bit B5. That is to say, this means that there is an error in the data read by the sense amplifier 27 at bit B5. Therefore, the write driver 28 prohibits the selection of bit lines corresponding to the other bits B1 to B4 and B6 to B8, and writes data only to the memory cell MC that is connected to the bit line corresponding to bit B5 and the bit line corresponding to the parity bit.

[0121] 《Effect of this Embodiment》

[0122] According to this embodiment, the write driver 28 detects the bit in which the data is inverted, that is, the error bit from among the multiple columns (bit lines) to be rewritten. Then, the corrected data is written into the memory cell MC corresponding to the bit in which the data is inverted. Therefore, it is not necessary to supply a write current to the memory cell MC that does not require rewriting. As a result, deterioration of the memory cell MC can be suppressed, and data reliability can be improved.

[0123] In Figure 8 the example of, all bits of the parity bit are rewritten. However, also for the parity bit, only the bits whose values are changed can be rewritten.

[0124] <Third Embodiment>

[0125] Next, a storage device according to a third embodiment of the present disclosure will be described. In this embodiment, in the master write operation described in the first embodiment or the second embodiment, verification is performed on the data written into the memory cell MC. Only the points different from the first embodiment and the second embodiment will be described below.

[0126] 《Configuration》

[0127] The configuration of the storage device 20 according to this embodiment is as described in the second embodiment Figure 6 as shown, and thus its description will be omitted.

[0128] 《Operation》

[0129] Figure 9 is a flowchart of the master write operation according to this embodiment. As shown in the figure, the points different from those described in the first embodiment Figure 4B are as follows. That is to say, the master write operation is executed in six pipeline stages, and the fifth and sixth pipeline stages (steps S25 and S26) are sequentially executed after the first to fourth pipeline stages described in the first embodiment.

[0130] In the fifth pipeline stage, verification of the data written in step S23 is performed (step S25). That is, the controller 33 of the storage device 20 performs a data read operation on the memory cell MC in which data was written in step S23. The details of this operation are the same as those in step S20. The data read by the sense amplifier 27 is transmitted to the write driver 28 via a bypass path connecting the sense amplifier 27 and the write driver 28.

[0131] In the sixth pipeline stage, the write driver 28 compares the data written in the memory cell MC in step S23 with the data read in step S25. Then, as a result of the comparison, data is rewritten only for the different bits (step S26). For example, assume that the data written in the memory cell MC by the write driver 28 in step S23, in other words, the net data (data other than parity bits) of the data received from the ECC circuit 29, is "00110011". Then, assume that the data read in step S25 is "00111011". Then, it can be seen that the fifth bit data from the start is different from the value to be written. Therefore, in step S26, the write driver 28 rewrites the data "0" to the memory cell MC corresponding to the fifth bit from the start. Of course, if there is an error in any bit, not only that bit but also all bits (and parity bits) can be rewritten. That is, the data is repaired in step S25, and the repaired data is written back to the memory cell MC in step S26 (therefore, step S26 can also be referred to as a write repair cycle).

[0132] Figure 10 Corresponding to that described in the first embodiment Figure 5 and shows a case where the bus master device 10 sequentially issues a first master write command WR1, a second master write command WR2, and a master read command RD3.

[0133] As shown in the figure, first, in response to the master write command WR1 for the address ADD[m], the pipeline operation PP1 starts at time t1. Next, in response to the master write command WR2 for the address ADD[m + 1], the pipeline operation PP2 starts at time t3. Then, in response to the master read command RD3 for the address ADD[n + 2], the pipeline operation PP3 starts at time t5. Thus, when the pipeline operations are continuously executed, the controller 33 inserts wait cycles into each of the pipeline operations PP1 to PP3 as needed to suppress bus contention.

[0134] In Figure 10In the example, it is shown that the pipelined operations PP1 and PP2 are executed in 8 pipeline stages and the pipelined operation PP3 is executed in 7 pipeline stages. As shown in the figure, in the pipelined operation PP1, two wait cycles are inserted during the time from t5 to t7. During this period, the ECC operation (step S22) and the write operation (step S23) of the pipelined operation PP2, and the read operation (step S10) and the ECC operation (step S11) of the pipelined operation PP3 are executed. Similarly, in the pipelined operation PP2, two wait cycles are inserted during the time from t7 to t9. During this period, the verification operation (step S25) and the write operation (step S26) of the pipelined operation PP1 are executed. In the pipelined operation PP3, three wait cycles are inserted during the time from t8 to t11. During this period, the write operation (step S26) of the pipelined operation PP1, and the verification operation (step S25) and the write operation (step S26) of the pipelined operation PP2 are executed.

[0135] As described above, by appropriately providing wait cycles, the access efficiency to the memory cell array 21 can be improved.

[0136] <<Effects of the present embodiment>>

[0137] According to the present embodiment, in the host write operation, the written data is verified and the bits with write errors are rewritten. Therefore, write errors can be suppressed and the reliability of the host write operation can be improved.

[0138] <<Fourth Embodiment>>

[0139] Next, a storage device according to a fourth embodiment of the present disclosure will be described. This embodiment relates to the operation details of the storage device 20 during the host read operation and the host write operation in the first embodiment. Hereinafter, the case where the host read operation is continuously executed, the case where the host write operation is continuously executed, and the case where the host write operation and the host read operation are continuously executed will be described.

[0140] <<Case where the host read operation is continuous>>

[0141] First, reference will be made to Figures 11A to 11F to describe the case where the host read operation is continuous. Figures 11A to 11F is a block diagram of the storage device 20 and corresponds to the operation during the time from t1 to t7 in Figure 5 In Figures 11A to 11F the signal flow is also shown. The solid arrows in the figure indicate the valid signal flow, and the dashed arrows indicate that the signal is not transmitted through the path. This also applies to the description of the case where the host write operation described below is continuously executed and the case where the host write operation and the host read operation described below are continuously executed.

[0142] Figure 11A corresponds toFigure 5 from time t1 to t2. That is, the storage device 20 synchronously receives the first master read command RD1 and the address ADD1 sent from the bus master device 10 with the clock CLK. The address ADD1 is held in the address buffer 22, and the controller 33 further instructs the selector 30 to select the output of the address buffer 22. As a result, the address ADD1 is transmitted to the decoder 24, and the data DAT1 is read from the memory cell MC in the memory cell array 21 by the sense amplifier 27.

[0143] Figure 11B corresponding to Figure 5 from time t2 to t3. That is, the storage device 20 performs ECC processing on the data DAT1 read from the memory cell array 21. That is, the data DAT1 is transmitted from the sense amplifier 27 to the error correction circuit 34, and its error is corrected. In addition, the controller 33 instructs the selector 32 to select the output of the error correction circuit 34. With this configuration, the error-corrected data DAT1 is held in the data buffer 26. In addition, the controller 33 instructs the selector 32 to select the output of the data buffer 26. With this configuration, the error-corrected data DAT1 is held in the data buffer 25. In addition, the data DAT1 is transmitted from the data buffer 25 to the parity code generator 35, and a parity bit is generated. The combination of the error-corrected data DAT1 and the parity bit is referred to as the data DATP1. The address ADD1 held in the address buffer 22 is transmitted to the address buffer 23.

[0144] Figure 11C corresponding to Figure 5 from time t3 to t4. During this period, the pipeline operation PP1 based on the master read command RD1 executes a wait cycle. That is, the operations of the sense amplifier 27 and the write driver 28 based on the master read command RD1 are not performed. At time t3, the error-corrected data DAT1 held in the data buffer 26 is output to the bus master device 10 as the data RDAT1 read from the storage device 20.

[0145] In the time period from t3 to t4, the storage device 20 synchronously receives the second master read command RD2 and the address ADD2 sent from the bus master device 10 with the clock CLK. The address ADD2 is held in the address buffer 22, and the controller 33 further instructs the selector 30 to select the output of the address buffer 22. As a result, the address ADD2 is transmitted to the decoder 24, and the data DAT2 is read from the memory cell MC in the memory cell array 21 by the sense amplifier 27.

[0146] Figure 11D corresponding to Figure 5During the time t4 to t5. That is, the storage device 20 transfers the data DATP1 regarding the pipeline operation PP1 generated by the check code generator 35 to the write driver 28. According to the instruction from the controller 33, the selector 30 selects the address ADD1 held in the address buffer 23 and transfers the address ADD1 to the decoder 24. As a result, the data DATP1 is written to the address ADD1.

[0147] Regarding the pipeline operation PP2, the Figure 11B ECC processing described in is performed. That is, the data DAT2 is transferred from the sense amplifier 27 to the error correction circuit 34, its error is corrected and further transferred to the data buffer 25 and the check code generator 35 via the selector 32, and parity bits are generated. The combination of the error-corrected data DAT2 and the parity bits is referred to as the data DATP2. The address ADD2 held in the address buffer 22 is transferred to the address buffer 23.

[0148] Figure 11E Corresponding to Figure 5 During the time t5 to t6. During this period, the pipeline operation PP2 based on the master read command RD2 performs a wait cycle. That is, the operations of the sense amplifier 27 and the write driver 28 based on the master read command RD2 are not executed. At time t3, the error-corrected data DAT2 held in the data buffer 26 is output as the read data RDAT2 from the storage device 20 to the bus master device 10.

[0149] Figure 11F Corresponding to Figure 5 During the time t6 to t7. That is, the storage device 20 transfers the data DATP2 generated by the check code generator 35 to the write driver 28. According to the instruction from the controller 33, the selector 30 selects the address ADD2 held in the address buffer 23 and transfers the address ADD2 to the decoder 24. As a result, the data DATP2 is written to the address ADD2.

[0150] 《Case where the master write operation is continuous》

[0151] Next, the case where the master write operation is continuous will be described with reference to Figures 12A to 12F is a block diagram of the storage device 20 and corresponds to the operation during the time t5 to t11 in Figures 12A to 12F is a block diagram of the storage device 20 and corresponds to the operation from time t5 to t11. Figure 5 in

[0152] Figure 12A Corresponding to Figure 5During the time t5 to t6 in []. That is, the storage device 20 receives the first master write command WR1 and the address ADD1 sent from the bus master device 10 synchronously with the clock CLK. Then, similar to the case of Figure 11A , the address ADD1 is held in the address buffer 22, and the address ADD1 is further transmitted to the decoder 24 through the selector 30. Then, the data DAT1 is read from the memory cell MC in the memory cell array 21 by the sense amplifier 27, and the error of the data DAT1 is further corrected by the error correction circuit 34.

[0153] Figure 12B Corresponding to Figure 5 During the time t6 to t7 in []. During this period, the pipeline operation PP3 based on the master write command WR1 executes a wait cycle. That is, the operations of the sense amplifier 27 and the write driver 28 based on the master write command WR1 are not executed.

[0154] Figure 12C Corresponding to Figure 5 During the time t7 to t8 in []. That is, the storage device 20 receives the write data WDAT1 sent from the bus master device 10 synchronously with the clock CLK and performs ECC processing. As shown in the figure, the selector 31 transmits the data WDAT1 sent from the bus master device 10 to the data buffer 25 based on the instruction of the controller 33. In addition, the controller 33 instructs the selector 32 to select the output of the error correction circuit 34. With this configuration, the error-corrected data DAT1 is held in the data buffer 26. In addition, the controller 33 instructs the selector 31 to select the output of the data buffer 26. With this configuration, the error-corrected data DAT1 is transmitted to the data buffer 25. The reasons why the data WDAT1 and DAT1 are transmitted to the data buffer 25 are as follows. That is, parity bits are generated in units of specific fixed bits. In this example, it is assumed that parity bits are generated in units of 32 bits, for example. However, the number of bits of the data WDAT1 sent from the bus master device 10 may not be limited to 32 bits. For example, in the example of Figure 12C , the data WDAT1 is 8 bits. Then, the number of bits (24 bits) for generating parity bits is insufficient. Therefore, the data buffer 25 supplements the missing 24 bits with the data DAT1 to generate 32-bit write data CBDAT1. Then, the data CBDAT1 is transmitted from the data buffer 25 to the parity code generator 35, and parity bits are generated. The combination of the data CBDAT1 and the parity bits is called the data DATP1.

[0155] In the time period from time t7 to t8, the storage device 20 receives the second master write command WR2 and the address ADD2 sent from the bus master device 10 synchronously with the clock CLK. The address ADD2 is held in the address buffer 22, and the controller 33 further instructs the selector 30 to select the output of the address buffer 22. As a result, the address ADD2 is transmitted to the decoder 24, data DAT2 is read from the memory cell MC in the memory cell array 21 through the sense amplifier 27, and the error of the data DAT12 is corrected by the error correction circuit 34. The address ADD1 held in the address buffer 22 before that is transmitted to the address buffer 23.

[0156] Figure 12D Corresponding to Figure 5 the time t8 to t9 in. That is, regarding the pipeline operation PP3, the storage device 20 transmits the data DATP1 generated by the parity code generator 35 to the write driver 28. According to the instruction from the controller 33, the selector 30 selects the address ADD1 held in the address buffer 23 and transmits the address ADD1 to the decoder 24. As a result, the data DATP1 is written to the address ADD1.

[0157] During the time t8 to t9, the pipeline operation PP4 based on the master write command WR2 executes a wait cycle. That is, the operations of the sense amplifier 27 and the write driver 28 based on the master write command WR2 are not executed.

[0158] Figure 12E Corresponding to Figure 5 the time t9 to t10 in. That is, similar to Figure 12C the above, the storage device 20 receives the write data WDAT2 sent from the bus master device 10 synchronously with the clock CLK and performs ECC processing. As shown in the figure, the data WDAT1 is transmitted to the data buffer 25, and the error-corrected data DAT2 is transmitted from the data buffer 26 to the data buffer 25. With this configuration, for example, 32-bit write data CBDAT2 is generated. Then, the data CBDAT2 is transmitted from the data buffer 25 to the parity code generator 35, and parity bits are generated. The combination of the data CBDAT2 and the parity bits is called the data DATP2.

[0159] Figure 12F Corresponding to Figure 5 the time t10 to t11 in. That is, the storage device 20 transmits the data DATP2 generated by the parity code generator 35 to the write driver 28. According to the instruction from the controller 33, the selector 30 selects the address ADD2 held in the address buffer 23 and transmits the address ADD2 to the decoder 24. As a result, the data DATP2 is written to the address ADD2.

[0160] "Case where Master Write Operation and Master Read Operation are Continuous"

[0161] Next, the case of performing a master write operation and continuously performing a master read operation will be described. This operation corresponds to Figure 5 the operation during the period from time t7 to t13 in

[0162] When the target address for the master write operation and the target address for the master read operation are different, a combination such as the above-mentioned Figures 12A to 12D and Figures 11A to 11D is obtained. That is, the operation described in Figure 12A is performed during the period from time t7 to t8, and the operation described in Figure 12B is performed during the period from time t8 to t9. Thereafter, during the time period from t9 to t10, the ECC cycle described in Figure 12C is performed for the master write operation, and the read cycle described in Figure 11A is performed for the master read operation. During the time period from t10 to t11, the write cycle described in Figure 12D is performed for the master write operation, and the ECC cycle described in Figure 11B is performed for the master read operation. Thereafter, the wait cycle and write cycle described in Figure 11C and 11D are performed for the master read operation.

[0163] Next, the case where the address for the master write operation and the address for the master read operation are the same will be described. First, during the period from time t7 to t9, the operations described with reference to Figure 12A and Figure 12B are performed in the same manner as above. Thereafter, during the time period from t9 to t10 as well, the operations described in Figure 12C and Figure 11A are performed in the same manner as above. This state is as shown in Figure 13A . Figure 13A The difference from Figure 12C is that a master read command RD3 is sent from the bus master device 10, and the target address is the same as the target address of the previous master write command WR2(ADD1). As described in the reference Figure 12C , in the data buffer 25, data CBDAT1 is generated based on the write data WDAT and the corrected read data DAT1.

[0164] Next, during the period from time t10 to t11, the operation shown in Figures 13B to 13D is performed. First, as shown in Figure 13BAs shown, data CBDAT1 is held in data buffer 25, data DATP1 is written to memory cell MC based on master write command WR2, and data DAT1 read out based on the master read instruction is held in data buffer 26.

[0165] Next, as Figure 13C shown, in response to the target address of the master write operation being the same as the target address of the master read operation, controller 33 causes selector 31 to select data buffer 26. As a result, data CBDAT1 including the written data WDAT1 is transferred to data buffer 26, and the read data DAT1 held in data buffer 26 before that is evicted. Subsequently, as Figure 13D shown, controller 33 causes selector 31 to select data buffer 26 and disables selector 32. As a result, data DAT1 is held in data buffer 25. That is, through the operations shown in Figure 13C and Figure 13D , the data (CBDAT1 and DAT1) held in data buffers 25 and 26 are swapped.

[0166] Figure 13E Corresponds to the period from time t11 to t12 in Figure 5 . As shown, a wait cycle is executed, and data CBDAT1 in data buffer 26 is output as read data RDAT1 of storage device 20 to bus master device 10.

[0167] 《Effects of this Embodiment》

[0168] The pipeline stages described in the first to third embodiments can be implemented by the operations described in this embodiment.

[0169] As Figure 4E shown, when a master write operation and a master read operation are continuously executed, the read cycle (step S10) in the master read operation is executed before the write cycle (step S23) in the master write operation. In view of this, in this embodiment, when the addresses for the master write operation and the master read operation are the same, instead of data DAT actually read from memory cell MC, the written data CBDAT generated by the master write operation (see Figures 13C to 13E ) is output as read data RDAT to bus master device 10. With this configuration, the data to be written in the master write operation can be regarded as read data, and correct data can be output to bus master device 10.

[0170] The description of the case where a master read operation and a master write operation are continuously executed is omitted. However, in this case, for example, the processing of Figures 11A to 11D can be performed for the master read operation, and the processing of Figures 12A to 12DProcessing. In this case, since data is read in the first pipeline stage of the master read operation and written in the fourth pipeline stage of the master write operation, there is no particular problem even if the access target is the same address.

[0171] <Modification examples, etc.>

[0172] As described above, the storage device according to the first to fourth embodiments can improve the operation reliability. Although the above description is made using various embodiments, the embodiments are not limited to the above embodiments and can be variously modified.

[0173] For example, in the above embodiments, the following case is described as an example: The storage device 20 includes a set of memory cell arrays 21, a decoder 24, a sense amplifier 27, a write driver 28, and an ECC circuit 29. However, as Figure 14 shown, multiple such sets can be provided. Figure 14 is a block diagram of a processor system 1 according to a modification example of the above embodiment. As shown, the storage device 20 includes multiple sets of memory cell arrays 21, a decoder 24, a sense amplifier 27, a write driver 28, and an ECC circuit 29. Each of these sets is referred to as a subarray 100. The multiple subarrays 100 share the address buffers 22 and 23, the data buffers 25 and 26, and the selectors 30 to 32, and are controlled by the controller 33. According to this configuration, since the decoder 24, the sense amplifier 27, the write driver 28, and the ECC circuit 29 are provided for each memory cell array 21, data writing and reading can be performed on the memory cell arrays 21 of the multiple subarrays 100 simultaneously.

[0174] In addition, as Figure 15 shown, the address buffers 22 and 23, the data buffers 25 and 26, and the selectors 30 to 32 can also be provided for each subarray 100. In this case, the subarrays 100 can operate independently of each other, and the bus master device 10 can access the multiple subarrays 100 in parallel.

[0175] In the above embodiments, MRAM is described as an example of the storage device 20. However, the storage device 20 is not limited to MRAM and can be, for example, ReRAM, PCM, or other non-volatile memories.

[0176] In addition, although examples of pipeline stages are shown in Figure 4A and Figure 4B , the order is not limited to this order, and wait cycles can be added or the order of processing can be changed as needed. As long as there is no bus contention with other pipelines, the order of the pipeline stages is not restricted. In Figures 4C to 4EIn this case, a situation where accesses are performed twice in succession from the bus master device 10 is shown, but the number of accesses is not limited to two, and the number is unrestricted. In the above-described embodiment, a case where the storage device 20 is always accessed from the bus master device 10 is described as an example, but it may also include a cycle (wait or standby state) in which access is not performed from the bus master device 10.

[0177] In the above-described embodiment, although the processor system 1 is described as an example, for example, a memory system may be used instead of the processor system 1. In this case, the storage device 20 may be a memory for storage, and the bus master device 10 may be a host device such as a personal computer or a digital camera.

[0178] Although certain embodiments that are currently considered to be of the present invention have been described, it should be understood that various modifications can be made thereto, and it is intended that the appended claims cover all such modifications that fall within the true spirit and scope of the present invention.

[0179] Those skilled in the art should understand that various modifications, combinations, sub-combinations, and changes can occur depending on design requirements and other factors, as long as they are within the scope of the appended claims or their equivalents.

Claims

1. A storage device, comprising: A storage unit capable of holding data; An ECC circuit capable of generating a correction code and detecting an error based on the correction code; At least two or more address buffers; A write data buffer capable of holding write data in the storage unit; A read data buffer capable of holding read data from the storage unit; A first signal path capable of transferring data from the read data buffer to the write data buffer; And A second signal path capable of transferring data from the write data buffer to the read data buffer, Wherein, the storage unit is accessed through a pipelined operation, and the pipelined operation includes at least four pipeline stages, and the four pipeline stages include: A read cycle for reading data from the storage unit, An ECC cycle for performing generation or error detection of the correction code in the ECC circuit for the storage unit, A wait cycle during which no processing of data related to the storage unit is performed, and A write cycle for writing data into the storage unit, The address buffer includes: A write address buffer capable of holding the address of the storage unit received from the outside during an operation of writing data, and A read address buffer capable of holding the address of the storage unit received from the outside during an operation of reading data.

2. A storage device, comprising: A storage unit capable of holding data; And An ECC circuit capable of generating a correction code and detecting an error based on the correction code, Wherein, the storage unit is accessed through a pipelined operation, and the pipelined operation includes at least four pipeline stages, and the four pipeline stages include: A read cycle for reading data from the storage unit, An ECC cycle for performing generation or error detection of the correction code in the ECC circuit for the storage unit, A wait cycle during which no processing of data related to the storage unit is performed, and A write cycle for writing data into the storage unit, The pipelined operation during an operation of reading data from the storage unit is performed in the order of the read cycle, the ECC cycle, the wait cycle, and the write cycle, and The pipelined operation during an operation of writing data into the storage unit is performed in the order of the read cycle, the wait cycle, the ECC cycle, and the write cycle.

3. The storage device according to claim 2, wherein, Further comprising: A sense amplifier for reading read data from the storage unit; and A write driver for writing data into the storage unit, Wherein, the sense amplifier operates in the read cycle among at least four pipeline stages, and then the write driver operates in the write cycle among the at least four pipeline stages.

4. The storage device according to claim 2, wherein, When a write instruction for writing data into the storage unit and a read instruction for reading data from the storage unit are continuously received, The storage device outputs, to the outside, as read data corresponding to the read instruction, first data of write data received together with the write instruction.

5. The storage device according to claim 4, further comprising: A write data buffer capable of holding write data in the storage cell; A read data buffer capable of holding read data from the storage cell; A first signal path capable of transferring data from the read data buffer to the write data buffer; And A second signal path capable of transferring data from the write data buffer to the read data buffer, wherein, when the write instruction for writing data to the storage cell and the read instruction for reading data from the storage cell are continuously received, the storage device causes first data including the write data received together with the write instruction to be held in the write data buffer, causes second data read from the storage cell in the read cycle corresponding to the read instruction to be held in the read data buffer, transfers the first data to the read data buffer via the second signal path, and transfers the second data to the write data buffer via the first signal path.

6. A storage device, comprising: A storage cell capable of holding data; An ECC circuit capable of generating a correction code and detecting an error based on the correction code; At least two or more address buffers; A write data buffer capable of holding write data in the storage cell; A read data buffer capable of holding read data from the storage cell; A first signal path capable of transferring data from the read data buffer to the write data buffer; And A second signal path capable of transferring data from the write data buffer to the read data buffer, wherein the storage cell is accessed by a pipelined operation, and the pipelined operation includes at least four pipeline stages, and the four pipeline stages include: A read cycle that reads data from the storage cell, An ECC cycle that performs generation or error detection of the correction code in the ECC circuit for the storage cell, A wait cycle during which no processing of data related to the storage cell is performed, and A write cycle that writes data to the storage cell, The address buffer includes: A write address buffer capable of holding the address of the storage cell received from the outside during an operation of writing data, and A read address buffer capable of holding the address of the storage cell received from the outside during an operation of reading data, During an operation of writing data to the storage cell, the read data read from the storage cell in the read cycle is compared with the write data received from the outside, and As a result of the comparison, when the read data is different from the write data, the write data is written to the storage cell.

7. A storage device, comprising: A storage cell capable of holding data; And An ECC circuit capable of generating a correction code and detecting an error based on the correction code, Among them, the storage unit is accessed through a pipelined operation, and the pipelined operation includes at least four pipeline stages, and the four pipeline stages include: A read cycle that reads data from the storage unit, An ECC cycle that performs generation or error detection of the correction code for the storage unit in the ECC circuit, A wait cycle during which no processing of data related to the storage unit is performed, and A write cycle that writes data to the storage unit, During the operation of writing data to the storage unit, the read data read from the storage unit in the read cycle is compared with the write data received from the outside, and As a result of the comparison, when the read data is different from the write data, the write data is written to the storage unit, The pipelined operation during the operation of reading data from the storage unit is performed in the order of the read cycle, the ECC cycle, the wait cycle, and the write cycle, and The pipelined operation during the operation of writing data to the storage unit is performed in the order of the read cycle, the wait cycle, the ECC cycle, and the write cycle.

8. The storage device according to claim 7, wherein, Further includes: A sense amplifier that reads the read data from the storage unit; and A write driver that writes data to the storage unit, Among them, the sense amplifier operates in the read cycle of at least four pipeline stages, and then the write driver operates in the write cycle of the at least four pipeline stages.

9. A storage device, including: A storage unit that can hold data; An ECC circuit that can generate a correction code and detect errors based on the correction code; At least two or more address buffers; A write data buffer that can hold the write data in the storage unit; A read data buffer that can hold the read data from the storage unit; A first signal path that can transfer data from the read data buffer to the write data buffer; And A second signal path that can transfer data from the write data buffer to the read data buffer, Among them, the storage unit is accessed through a pipelined operation, and the pipelined operation includes at least four pipeline stages, and the four pipeline stages include: A read cycle that reads data from the storage unit, An ECC cycle that performs generation or error detection of the correction code for the storage unit in the ECC circuit, A wait cycle during which no processing of data related to the storage unit is performed, and A write cycle that writes data to the storage unit, The number of pipeline stages in the pipelined operation is different between the data write operation to the storage unit and the data read operation from the storage unit, The address buffer includes: A write address buffer that can hold the address of the storage unit received from the outside during the operation of writing data, and A read address buffer that can hold the address of the storage unit received from the outside during the operation of reading data.

10. The storage device according to any one of claims 1, 6, and 9, wherein, the storage device is one of a magnetoresistive random access memory (MRAM), a resistive random access memory (ReRAM), and a phase change memory (PCM).

11. A storage device, comprising: a storage cell capable of holding data; and an ECC circuit capable of generating a correction code and detecting an error based on the correction code, wherein the storage cell is accessed by a pipelined operation, and the pipelined operation includes at least four pipeline stages, and the four pipeline stages include: a read cycle for reading data from the storage cell, an ECC cycle for performing generation or error detection of the correction code in the ECC circuit for the storage cell, a wait cycle during which no processing of data related to the storage cell is performed, and a write cycle for writing data into the storage cell, the number of pipeline stages in the pipelined operation is different between a data write operation to the storage cell and a data read operation from the storage cell, the pipelined operation during an operation of reading data from the storage cell includes at least four pipeline stages executed in the order of the read cycle, the ECC cycle, the wait cycle, and the write cycle, the pipelined operation during an operation of writing data into the storage cell includes at least six pipeline stages executed in the order of the read cycle, the wait cycle, the ECC cycle, the write cycle, a verify read cycle, and a write repair cycle, in the verify read cycle, the data written into the storage cell in the write cycle is read and verified, and in the write repair cycle, data based on the verification result in the verify read cycle is written into the storage cell.

12. The storage device according to claim 11, wherein, Further comprising: a sense amplifier for reading the read data from the storage cell; and a write driver for writing data into the storage cell, the sense amplifier operates in the read cycle among at least four pipeline stages, and then the write driver operates in the write cycle among the at least four pipeline stages.

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