Semiconductor packaging method and semiconductor packaging structure

Abstract

The present application provides a semiconductor packaging method and a semiconductor packaging structure. The semiconductor packaging method includes: S1: attaching a first encapsulation structure to a support plate, wherein the first encapsulation structure encapsulates a first chip to be packaged; S2: forming a first redistribution structure on the first encapsulation structure, wherein the first redistribution structure is electrically connected to the first chip to be packaged; S3: attaching a second chip to be packaged to the first encapsulation structure, wherein the second chip to be packaged is partially stacked on the first chip to be packaged; S4: forming a second encapsulation structure; S5: forming a second redistribution structure on the second encapsulation structure, wherein the second redistribution structure is electrically connected to the first redistribution structure and the second chip to be packaged; S6: peeling off the support plate. The semiconductor packaging structure is manufactured by the semiconductor packaging method. The present application solves the structural fragility of ultra-thin chips by packaging the first chip and the second chip separately.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor packaging method and a semiconductor packaging structure. Background Art

[0002] In the prior art, to increase the chip capacity within a package (e.g., flash memory capacity), the chips are thinned and then stacked. As shown in Figure 1(a), chips 11' are first stacked layer by layer, then bonded using wires 20'. After bonding, the chips are encapsulated using a plastic encapsulation layer 30', as shown in Figure 1(b).

[0003] However, when the number of layers of multi-layer chip stacking is very large, the structure is very fragile and cannot be stacked too high due to the lack of support balance. Ultra-thin chips cannot be used. When the chip is too thin, it is very easy to cause the product to break during chip bonding and wire bonding. Summary of the Invention

[0004] One aspect of the present application provides a semiconductor packaging method, comprising the following steps:

[0005] S1: Providing a first encapsulation structure and attaching the first encapsulation structure to a support plate, wherein the first encapsulation structure encapsulates a first chip to be packaged, the first chip to be packaged comprising a front surface and a back surface opposite to each other and being encapsulated by a first encapsulation layer, the first encapsulation structure comprising a first surface and a second surface opposite to each other, the front surface of the first chip to be packaged corresponding to the first surface of the first encapsulation structure, and the second surface of the first encapsulation structure facing the support plate;

[0006] S2: forming a first redistribution structure on the first surface of the first encapsulation structure, wherein the first redistribution structure is electrically connected to the front surface of the first chip to be packaged;

[0007] S3: Mounting a second chip to be packaged on the first surface of the first encapsulation structure, with the back surface of the second chip to be packaged facing the first surface of the first encapsulation structure, and the second chip to be packaged partially overlapping the first chip to be packaged;

[0008] S4: Covering the first redistribution structure and the second chip to be packaged with a second encapsulation layer, and plastic-encapsulating the first redistribution structure and the second chip to be packaged to form a second encapsulation structure, wherein the second encapsulation structure includes a first surface and a second surface opposite to each other, and the front surface of the second chip to be packaged corresponds to the first surface of the second encapsulation structure;

[0009] S5: forming a second redistribution structure on the first surface of the second encapsulation structure, wherein the second redistribution structure is electrically connected to the first redistribution structure and the front surface of the second chip to be packaged;

[0010] S6: peeling off the support plate.

[0011] Optionally, before entering step S6, steps S3 to S5 are repeated to obtain N layers of stacked second encapsulation structures and N layers of stacked second redistribution structures, where N is an integer greater than 2, wherein:

[0012] The first layer of the second encapsulation structure encapsulates the first redistribution structure and the second chip to be packaged in the first layer of the second encapsulation structure, and the Nth layer of the second encapsulation structure encapsulates the N-1th layer of the second redistribution structure and the second chip to be packaged in the Nth layer of the second encapsulation structure;

[0013] The second chip to be packaged in the second encapsulation structure of the first layer is partially stacked on the first chip to be packaged, and the second chip to be packaged in the second encapsulation structure of the Nth layer is partially stacked on the second chip to be packaged in the second encapsulation structure of the N-1th layer;

[0014] The second rewiring structure of the first layer is electrically connected to the front surface of the second chip to be packaged in the second encapsulation structure of the first layer and the first rewiring structure, and the second rewiring structure of the Nth layer is electrically connected to the front surface of the second chip to be packaged in the second encapsulation structure of the Nth layer and the second rewiring structure of the N-1th layer.

[0015] Optionally, the front side of the second chip to be packaged is covered with the second encapsulation layer, and before step S5, the method further includes:

[0016] forming an opening on the first surface of the second encapsulation structure, wherein the position of the opening corresponds to the front surface of the second chip to be packaged;

[0017] A conductive pillar is formed in the opening, and the conductive pillar is used to connect the front surface of the second chip to be packaged and the second redistribution structure.

[0018] Optionally, the first redistribution structure is formed above one end of the first chip to be packaged; and the second redistribution structure can be formed at any position above the second chip to be packaged.

[0019] Optionally, the second rewiring structure of the first layer is formed above one end of the second chip to be packaged in the second encapsulation structure of the first layer, the second rewiring structure of the N-1 layer is formed above one end of the second chip to be packaged in the second encapsulation structure of the N-1 layer, and the second rewiring structure of the N layer can be formed at any position above the second chip to be packaged in the second encapsulation structure of the N layer; wherein the position above one end of the first chip to be packaged and the position of one end of the second chip to be packaged in the second encapsulation structure of each layer in the N-1 layer correspond to each other.

[0020] A second aspect of the present application provides a semiconductor package structure, comprising:

[0021] a first encapsulation structure, the first encapsulation structure comprising a first surface and a second surface opposite to each other, the first encapsulation structure encapsulating a first chip via a first encapsulation layer, the front side of the first chip corresponding to the first surface of the first encapsulation structure;

[0022] a second encapsulation structure, the second encapsulation structure comprising a first surface and a second surface, the second encapsulation structure encapsulating a first redistribution structure and a second chip via a second encapsulation layer, the first redistribution structure being electrically connected to a front surface of the first chip, the second chip being partially stacked on the first chip, and the front surface of the second chip corresponding to the first surface of the second encapsulation structure;

[0023] A second redistribution structure is formed on the first surface of the second encapsulation structure, and the second redistribution structure is electrically connected to the first redistribution structure and the front surface of the second chip.

[0024] Optionally, the semiconductor package structure includes N stacked layers of the second encapsulation structure and N stacked layers of the second redistribution structure, where N is an integer greater than 2, wherein:

[0025] The first second encapsulation structure of the first layer encapsulates the first redistribution structure and the second chip in the first second encapsulation structure; the second encapsulation structure of the Nth layer encapsulates the second redistribution structure of the Nth layer and the second chip in the Nth second encapsulation structure;

[0026] The second chip in the second encapsulation structure of the first layer is partially stacked on the first chip, and the second chip in the second encapsulation structure of the Nth layer is partially stacked on the second chip in the second encapsulation structure of the N-1th layer;

[0027] The second rewiring structure of the first layer is electrically connected to the front surface of the second chip in the second encapsulation structure of the first layer and the first rewiring structure, and the second rewiring structure of the Nth layer is electrically connected to the front surface of the second chip in the second encapsulation structure of the Nth layer and the second rewiring structure of the N-1th layer.

[0028] Optionally, the front side of the second chip is covered with the second encapsulation layer, and the first surface of the second encapsulation structure is provided with an opening, the position of the opening corresponds to the front side of the second chip; a conductive column is formed in the opening, and the conductive column is used to connect the front side of the second chip and the second redistribution structure.

[0029] Optionally, the first redistribution structure is located above one end of the first chip; and the second redistribution structure may be located at any position above the second chip.

[0030] Optionally, the second redistribution structure of the first layer is located above one end of the second chip in the second encapsulation structure of the first layer, the second redistribution structure of the N-1 layer is located above one end of the second chip in the second encapsulation structure of the N-1 layer, and the second redistribution structure of the N layer can be located at any position above the second chip in the second encapsulation structure of the N layer; wherein the positions of one end of the first chip and one end of the second chip in the second encapsulation structure of each layer in the N-1 layer correspond to each other.

[0031] The semiconductor packaging method and semiconductor packaging structure provided in the embodiments of the present application solve the structural fragility of ultra-thin chips by packaging the first chip and the second chip separately; each layer of chips is packaged with support, so it is not limited by the number of chip stacking layers, forming a structure in which the chips and connecting circuits are continuously interconnected and stacked.

[0032] Moreover, the electrical lead-out of the front side of the first chip and the second chip is realized through the rewiring structure. Compared with the conventional method of completing the electrical connection through leads in the prior art, the rewiring structure requires less space, especially the space in the thickness direction. Moreover, the layout of the rewiring structure is freer and more flexible, and the connection is more reliable. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] FIG1( a ) is a schematic diagram of a cross-sectional structure of a package in the prior art along a first direction.

[0034] FIG1( b ) is a schematic diagram of the cross-sectional structure of a package in the prior art along the second direction.

[0035] Figure 2 This is a flow chart of a semiconductor packaging method proposed in embodiment 1 of the present application.

[0036] Figure 3(a)-Figure 3(l) This is a process flow chart of the semiconductor packaging method proposed in Example 1 of the present application.

[0037] Figure 4 It is a structural schematic diagram of the semiconductor packaging structure proposed in Example 1 of the present application.

[0038] Figure 5(a)-Figure 5(e) This is a process flow chart of the semiconductor packaging method according to Example 2 of the present application.

[0039] Figure 6 It is a structural schematic diagram of the semiconductor packaging structure proposed in Example 2 of the present application. DETAILED DESCRIPTION

[0040] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

[0041] The terms used in this application are for the purpose of describing specific embodiments only and are not intended to limit this application. Unless otherwise defined, technical or scientific terms used in this application should have the ordinary meaning understood by a person of ordinary skill in the art to which this application belongs. The use of "a" or "an," and similar terms in this specification and claims does not indicate a limitation of quantity, but rather indicates the presence of at least one. "Multiple" means two or more. "Include" or "comprising," and similar terms mean that the elements or objects listed before "include" or "comprising" include the elements or objects listed after "include" or "comprising," and their equivalents, and do not exclude other elements or objects. "Connected" or "connected," and similar terms are not limited to physical or mechanical connections and can include electrical connections, whether direct or indirect. "On" and / or "below," and similar terms are for convenience only and are not limited to a single position or spatial orientation. As used in this specification and the appended claims, the singular forms "a," "the," and "the" are intended to include the plural forms unless the context clearly indicates otherwise. It will also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0042] Example 1

[0043] This embodiment provides a semiconductor packaging method and a semiconductor packaging structure.

[0044] Figure 2 FIG. 1 is a flow chart of the semiconductor packaging method proposed in this embodiment. Figure 2 As shown, the semiconductor packaging method includes the following steps:

[0045] Step 100: Providing a first encapsulation structure and attaching the first encapsulation structure to a support plate. The first encapsulation structure encapsulates a first chip to be packaged. The first chip to be packaged includes a front surface and a back surface opposite to each other and is encapsulated by a first encapsulation layer. The first encapsulation structure includes a first surface and a second surface opposite to each other. The front surface of the first chip to be packaged corresponds to the first surface of the first encapsulation structure, and the second surface of the first encapsulation structure faces the support plate.

[0046] Step 200: forming a first redistribution structure on the first surface of the first encapsulation structure, wherein the first redistribution structure is electrically connected to the front surface of the first chip to be packaged;

[0047] Step 300: Mounting a second chip to be packaged on the first surface of the first encapsulation structure, with the back surface of the second chip to be packaged facing the first surface of the first encapsulation structure, and the second chip to be packaged partially overlapping the first chip to be packaged;

[0048] Step 400: Covering the first rewiring structure and the second chip to be packaged with a second encapsulation layer, and plastic-encapsulating the first rewiring structure and the second chip to be packaged to form a second encapsulation structure, wherein the second encapsulation structure includes a first surface and a second surface opposite to each other, and the front side of the second chip to be packaged corresponds to the first surface of the second encapsulation structure;

[0049] Step 500: forming a second redistribution structure on the first surface of the second encapsulation structure, wherein the second redistribution structure is electrically connected to the first redistribution structure and the front surface of the second chip to be packaged;

[0050] Step 600: Peeling off the support plate.

[0051] The semiconductor packaging method provided in this embodiment addresses the structural fragility of ultra-thin chips by separately packaging the first and second chips. Each layer of chips is packaged with support, eliminating the limitation of the number of chip stacking layers and forming a stacked structure in which the chips and connecting circuits are continuously interconnected. Furthermore, a rewiring structure is used to connect the front surfaces of the first and second chips. Compared to the conventional prior art method of achieving electrical connection through wires, the rewiring structure requires less space, particularly in the thickness direction. Furthermore, the rewiring structure offers greater flexibility in layout and more reliable connections.

[0052] Specifically, if Figure 3(a)-Figure 3(l) As shown, the semiconductor packaging method of this embodiment includes:

[0053] In step 100, before attaching the first encapsulating structure to the support plate, the process further includes:

[0054] In step 110, as shown in FIG3(a), a first chip to be packaged 11 is mounted on a carrier 3 via an adhesive layer, with the front surface 11a of the first chip to be packaged 11 facing the carrier 3 and the back surface 11b of the first chip to be packaged 11 facing upward. The first chip to be packaged 11 includes a front surface 11a with bonding pads and a back surface 11b disposed opposite the front surface 11a, so that the front surface 11a of the first chip to be packaged 11 has electrical leads.

[0055] The adhesive layer is used to bond the first chip to be packaged 11. The adhesive layer can be made of an easily peelable material so that the carrier 3 and the first chip to be packaged 11 can be peeled apart in subsequent processes. For example, a thermal separation material that can lose its viscosity by heating can be used.

[0056] In other embodiments, the adhesive layer may have a two-layer structure: a thermal separation material layer and a chip attachment layer. The thermal separation material layer is adhered to the carrier 3 and loses its adhesiveness when heated, allowing it to be peeled off from the carrier 3. The chip attachment layer, on the other hand, is a viscous material layer used to adhere the first chip to be packaged 11. After the first chip to be packaged 11 is peeled off from the carrier 3, the chip attachment layer can be removed by chemical cleaning. In one embodiment, the adhesive layer can be formed on the carrier 3 by lamination, printing, or other methods.

[0057] Optionally, a protective layer 13 is formed on the front side 11a of the first chip to be packaged 11, and a protective layer opening 131 is formed on the protective layer 13 at a position corresponding to the solder pad of the front side 11a of the chip to be packaged 11, and each protective layer opening 131 corresponds at least to the solder pad of the front side 11a of the first chip to be packaged 11 or the line led out from the solder pad, so that the solder pad of the front side 11a of the chip to be packaged 11 or the line led out from the solder pad is exposed from the protective layer opening 131.

[0058] In step 120, as shown in FIG3(b), the first encapsulation layer 14 is used to cover the entire carrier 3, that is, the first chip to be packaged 11 and the exposed portion of the carrier 3. The first chip to be packaged 11 is then plastic-encapsulated to form a first encapsulation structure 10. The first encapsulation structure 10 includes a first surface 10a and a second surface 10b that are oppositely disposed. The second surface 10b of the first encapsulation structure 10 is disposed opposite the carrier 3, is substantially flat, and is parallel to the surface of the carrier 3. The front surface 11a of the first chip to be packaged 11 corresponds to the first surface 10a of the first encapsulation structure 10.

[0059] The first encapsulation layer 14 may be formed by laminating an epoxy resin film or a molding film, or by injection molding, compression molding, or transfer molding an epoxy resin compound.

[0060] In step 130, as shown in FIG3(c), the carrier 3 is peeled off to expose the first surface 10a of the first encapsulation structure 10. The first surface 10a of the first encapsulation structure 10 exposes the protection layer 13 having the front surface 11a of the first chip 11 to be packaged.

[0061] Because the adhesive layer between carrier 3 and the first chip to be packaged is a thermal separation film, heating can be used to reduce the adhesive layer's viscosity, allowing carrier 3 to be peeled off. This method of peeling off carrier 3 by heating the adhesive layer minimizes damage to the first chip to be packaged 11 during the peeling process. In other embodiments, carrier 3 can also be peeled off directly mechanically.

[0062] After peeling off the carrier 3, a first encapsulation structure 10 is obtained, which includes the first chip to be packaged 11 and the first encapsulation layer 14 encapsulating the first chip to be packaged 11. On the formed first encapsulation structure 10, rewiring and packaging are continued.

[0063] Next, as shown in FIG. 3( d ), the first encapsulation structure 10 is mounted on the support plate 4 , with the second surface 10 b of the first encapsulation structure 10 facing the support plate 4 .

[0064] In step 200, as shown in FIG3(e), a first rewiring structure 50 is formed on the first surface 10a of the first encapsulation structure 10. The first rewiring structure 50 is electrically connected to the pads on the front surface 11a of the first chip to be packaged 11. The first rewiring structure 50 includes at least one first rewiring layer 51. In this embodiment, the first rewiring structure 50 includes a single first rewiring layer 51, but is not limited thereto. Multiple rewiring layers 51 may also be included based on design requirements, i.e., repeated rewiring may be performed on the first surface 10a of the first encapsulation structure 10. For example, more rewiring structures may be formed in the same manner, and adjustments may be made based on design requirements.

[0065] Since the protective layer opening 131 has been formed on the protective layer 13 , at least the protective layer opening 131 can be directly seen when forming the first redistribution layer 51 , so that the first redistribution structure 50 can be aligned more accurately when forming.

[0066] When forming the first redistribution structure 50, a conductive medium can be simultaneously filled into the protective layer opening 131 of the first chip to be packaged 11 to form the conductive studs 16. That is, the first redistribution layer 51 and the conductive studs 16 are formed in the same conductive layer formation process. The conductive studs 16 form a vertical connection structure in the protective layer opening 131, and the pads on the front surface 11a of the first chip to be packaged 11 are electrically connected through the conductive studs 16 and the first redistribution layer 51.

[0067] Preferably, the first redistribution structure 50 is formed above one end of the first chip to be packaged 11 , so as to leave a certain space for the second chip to be packaged 29 that needs to be partially stacked on the first chip to be packaged 11 in subsequent steps.

[0068] In order to correspond to the first rewiring structure 50 being formed above one end of the first chip to be packaged 11, when the pad position of the first chip to be packaged 11 is not within the positive projection of the first rewiring structure 50, a rewiring layer can be formed on the front side of the first chip to be packaged 11, thereby adjusting the position of the electrical connection point to meet the requirements of the electrical connection position.

[0069] In step 300, as shown in FIG3(f), a second chip 29 to be packaged is mounted on the first surface 10a of the first encapsulation structure 10, with the back surface of the second chip 29 facing the first surface 10a of the first encapsulation structure 10. The second chip 29 to be packaged is partially stacked on the first chip 11 to be packaged, that is, the second chip 29 to be packaged is partially stacked on the front surface 11a of the first chip 11 to be packaged, leaving space for electrical leads from the front surface 11a of the first chip 11 to be packaged. The second chip 29 to be packaged includes a front surface 29a with a bonding pad and a back surface 29b disposed opposite the front surface 29a, so that the front surface 29a of the second chip 29 has electrical leads.

[0070] In this embodiment, the second chip to be packaged 29 is attached to the first surface 10a of the first encapsulation structure 10 via an adhesive layer 30. The material of the adhesive layer 30 is a commercially available product.

[0071] In step 400, as shown in Figure 3(g), the first rewiring structure 50 and the second chip to be packaged 29 are covered with a second encapsulation layer 24, and the first rewiring structure 50 and the second chip to be packaged 29 are plastic-encapsulated to form a second encapsulation structure 20. The second encapsulation structure 20 includes a first surface 20a and a second surface 20b arranged opposite to each other, and the front side 29a of the second chip to be packaged 29 corresponds to the first surface 20a of the second encapsulation structure 20.

[0072] In this embodiment, the front surface 29a of the second chip to be packaged 29 is covered with a second encapsulation layer 24. The second encapsulation layer 24 can be formed by laminating an epoxy resin film or a molding film, or by injection molding, compression molding, or transfer molding an epoxy resin compound.

[0073] Before proceeding to step 400, as shown in FIG3(h), an opening 25 is formed on the first surface 20a of the second encapsulation structure 20. The position of the opening 25 corresponds to the bonding pad on the front surface 29a of the second chip to be packaged 29. A conductive pillar 26 is formed in the opening 25. The conductive pillar 26 is used to connect the bonding pad on the front surface 29a of the second chip to be packaged 29 to the second redistribution structure formed in a later step.

[0074] In step 400, as shown in FIG3(i), a second rewiring structure 60 is formed on the first surface 20a of the second encapsulation structure 20. The second rewiring structure 60 is electrically connected to the first rewiring structure 50 and the pads on the front surface of the second chip 29 to be packaged. The second rewiring structure 60 includes at least one second rewiring layer 69. In this embodiment, the second rewiring structure 60 includes a single second rewiring layer 69, but is not limited thereto. Multiple second rewiring layers 69 may also be included based on design requirements, i.e., repeated rewiring is performed on the first surface 20a of the second encapsulation structure 20. For example, more rewiring structures may be formed in the same manner, and this can be adjusted based on design requirements.

[0075] In this embodiment, since the opening 25 is formed on the first surface 20a of the second encapsulation structure 20, at least the opening 15 can be directly seen when forming the second redistribution layer 69, so the second redistribution structure 60 can be aligned more accurately when forming.

[0076] When forming the second rewiring structure 60, a conductive medium can be simultaneously filled into the openings 25 of the second encapsulation layer 24 to form conductive pillars 26. That is, the second rewiring layer 69 and the conductive pillars 26 are formed in the same conductive layer formation process. The conductive pillars 26 form a vertical connection structure in the openings 25, and the pads on the front surface 29a of the second chip to be packaged 29 are electrically connected through the conductive pillars 26 and the second rewiring layer 69. At the same time, the electrical connections of the first chip to be packaged 11 are also electrically connected through the second rewiring structure 60 and the first rewiring structure 50.

[0077] The final semiconductor package structure is electrically connected to the outside through the second redistribution structure 60 . Therefore, the second redistribution structure 60 , as the final electrical lead-out component, can be formed at any position above the second chip to be packaged 29 .

[0078] Optionally, as shown in FIG3(j), a dielectric layer 70 is formed on the second redistribution layer 69 (second redistribution structure 60), and the dielectric layer 70 is formed on the second redistribution layer 69 and the exposed first surface 20a of the second encapsulation structure 20. The dielectric layer 70 can be formed by molding film, or the dielectric layer 70 can be formed by lamination or printing. The dielectric layer 70 can be made of an insulating material, such as one or more of polyimide, epoxy resin, and PBO (Polybenzoxazole), preferably an epoxy compound. One end of the second redistribution layer 69 away from the second encapsulation structure 20 is exposed on a surface of the dielectric layer 70 away from the second encapsulation structure 20.

[0079] Next, in step 600 , as shown in FIG. 3( k ), the support plate 4 is peeled off to obtain a final semiconductor package structure.

[0080] Optionally, after step 600, as shown in FIG3(1), the process further includes thinning the second surface 10b of the first encapsulation structure 10. By grinding or polishing the second surface 10b of the first encapsulation structure 10 to reduce the thickness of the first encapsulation structure 10, the overall volume of the final semiconductor package structure can be further reduced.

[0081] In this way, the electrical lead-out of the front side 11a of the first chip to be packaged 11 and the front side 29a of the second chip to be packaged 29 are realized through the first rewiring structure 50 and the second rewiring structure 60. Compared with the prior art in which the electrical lead-out is completed through leads, the semiconductor packaging structure of this embodiment requires less space, especially the space in the thickness direction; and the layout of the rewiring structure is more free and flexible, and the connection is more reliable.

[0082] If multiple semiconductor package structures are packaged together, after the package is completed, the entire package structure is cut into multiple semiconductor package structures by laser or mechanical cutting. The structure diagram of the formed semiconductor package structure 1 is as follows Figure 4 shown.

[0083] like Figure 4 FIG. 1 is a schematic diagram of a semiconductor package structure 1 obtained by using the semiconductor packaging method according to this embodiment. The semiconductor package structure 1 includes a first encapsulation structure 10 encapsulating a first chip 11, a second encapsulation structure 20 encapsulating a first redistribution structure 50 and a second chip 29, and a second redistribution structure 60.

[0084] The first chip 11 includes a front surface 11 a provided with a bonding pad, and a back surface 11 b disposed opposite to the front surface 11 a , so that the front surface 11 a of the first chip 11 has electrical leads.

[0085] The first chip 11 is encapsulated with a first encapsulation layer 14 to form a first encapsulation structure 10. The first encapsulation structure 10 includes a first surface 10a and a second surface 10b disposed opposite each other. The front surface 11a of the first chip 11 corresponds to the first surface 10a of the first encapsulation structure 10. The first encapsulation layer 14 can be formed by laminating an epoxy resin film or a molding film, or by injection molding, compression molding, or transfer molding an epoxy resin compound.

[0086] Optionally, a protective layer 13 is formed on the front side 11a of the first chip 11, and a protective layer opening 131 is formed on the protective layer 13 at a position corresponding to the solder pad of the front side 11a of the chip 11, and each protective layer opening 131 corresponds at least to the solder pad of the front side 11a of the first chip 11 or the line led out from the solder pad, so that the solder pad of the front side 11a of the chip 11 or the line led out from the solder pad is exposed from the protective layer opening 131.

[0087] The second chip 29 includes a front surface 29a with bonding pads and a back surface 29b disposed opposite the front surface 29a, thereby providing electrical leads to the front surface 29a of the second chip 29. The second chip 29 is partially stacked on the front surface 11a of the first chip 11, leaving space for the electrical leads to the front surface 11a of the first chip 11. Conductive bumps 16 are formed within the openings 131 in the protective layer of the first chip 11.

[0088] An adhesive layer 30 is provided between the back surface 29b of the second chip 29 and the first surface 10a of the first encapsulation structure 10 . Thus, the second chip 29 is attached to the first surface 10a of the first encapsulation structure 10 via the adhesive layer 30 .

[0089] The first redistribution structure 50 is electrically connected to the bonding pads on the front surface 11a of the first chip 11. The first redistribution structure 50 includes at least one first redistribution layer 51. In this embodiment, the first redistribution structure 50 includes only one first redistribution layer 51, but is not limited thereto. Multiple redistribution layers 51 may be included as needed, i.e., repeated redistribution may be performed on the first surface 10a of the first encapsulation structure 10. For example, more redistribution structures may be formed in the same manner, and this may be adjusted based on design requirements.

[0090] When forming the first redistribution structure 50, a conductive medium can be simultaneously filled into the protective layer openings 131 of the first chip 11 to form conductive studs 16. That is, the first redistribution layer 51 and the conductive studs 16 are formed in the same conductive layer formation process. The conductive studs 16 form a vertical connection structure in the protective layer openings 131, and the pads on the front surface 11a of the first chip 11 are electrically connected through the conductive studs 16 and the first redistribution layer 51.

[0091] The first redistribution structure 50 and the second chip 29 are encapsulated by a second encapsulation layer 24 to form a second encapsulation structure 20. The second encapsulation structure 20 includes a first surface 20a and a second surface 20b disposed opposite each other. The front surface 29a of the second chip 29 corresponds to the first surface 20a of the second encapsulation structure 20. The front surface 29a of the second chip 29 is covered with the second encapsulation layer 24. The second encapsulation layer 24 can be formed by laminating an epoxy resin film or a molding film, or by injection molding, compression molding, or transfer molding an epoxy resin compound.

[0092] An opening 25 is formed on the first surface 20a of the second encapsulation structure 20. The opening 25 corresponds to the bonding pad on the front surface 29a of the second chip 29. A conductive pillar 26 is formed in the opening 25. The conductive pillar 26 is used to connect the bonding pad on the front surface 29a of the second chip 29 to the second redistribution structure 60.

[0093] A second rewiring structure 60 is formed on the first surface 20a of the second encapsulation structure 20. The second rewiring structure 60 is electrically connected to the first rewiring structure 50 and the pads on the front surface of the second chip 29. The second rewiring structure 60 includes at least one second rewiring layer 69. In this embodiment, the second rewiring structure 60 includes a single second rewiring layer 69, but is not limited thereto. Multiple second rewiring layers 69 may also be included based on design requirements, i.e., repeated rewiring may be performed on the first surface 20a of the second encapsulation structure 20. For example, more rewiring structures may be formed in the same manner, and this can be adjusted based on design requirements.

[0094] When forming the second rewiring structure 60, a conductive medium can be simultaneously filled into the openings 25 of the second encapsulation layer 24 to form conductive pillars 26. That is, the second rewiring layer 69 and the conductive pillars 26 are formed in the same conductive layer formation process. The conductive pillars 26 form a vertical connection structure in the openings 25, and the pads on the front surface 29a of the second chip 29 are electrically connected through the conductive pillars 26 and the second rewiring layer 69. At the same time, the electrical connections of the first chip 11 are also electrically connected through the second rewiring structure 60 and the first rewiring structure 50.

[0095] Preferably, the first redistribution structure 50 is formed above one end of the first chip 11 to leave a certain space for the second chip 29 that needs to be partially stacked on the first chip 11 .

[0096] Optionally, in order to correspond to the first rewiring structure 50 being formed above one end of the first chip 11, when the pad position of the first chip 11 is not within the positive projection of the first rewiring structure 50, a rewiring layer can be formed on the front side of the first chip 11, thereby adjusting the position of the electrical connection point to meet the requirements of the electrical connection position.

[0097] The semiconductor package structure 1 is electrically connected to the outside through the second redistribution structure 60 . Therefore, the second redistribution structure 60 , as the final electrical lead-out component, can be formed at any position above the second chip 29 .

[0098] Optionally, the semiconductor packaging structure 1 further includes a dielectric layer 70. The dielectric layer 70 is formed on the second redistribution layer 69, the second chip 29, and the exposed first surface 20a of the second encapsulation structure 20. The dielectric layer 70 can be formed by molding film, or the dielectric layer 70 can be formed by lamination or printing. The dielectric layer 70 can be made of an insulating material, such as one or more of polyimide, epoxy resin, and PBO (Polybenzoxazole), preferably an epoxy compound. The second redistribution layer 69 is away from one end of the second encapsulation structure 20, and is exposed on a surface of the dielectric layer 70 away from the second encapsulation structure 20.

[0099] The semiconductor packaging structure provided in this embodiment addresses the structural fragility of ultra-thin chips by separately packaging the first and second chips. Each layer of chips is packaged with support, eliminating the limitation of the number of chip stacking layers and forming a structure in which the chips and connecting circuits are continuously interconnected and stacked. Furthermore, a rewiring structure is used to achieve electrical leads from the front of the first and second chips. Compared to the conventional prior art method of achieving electrical connections through wires, the rewiring structure requires less space, particularly in the thickness direction. Furthermore, the rewiring structure provides more flexible layout and more reliable connections.

[0100] Example 2

[0101] The contents of the semiconductor packaging method of this embodiment are substantially the same as those of the semiconductor packaging method of Embodiment 1, except that, in the semiconductor packaging method of this embodiment, before entering step S600, steps S300 to S500 are repeated to obtain N layers of stacked second encapsulation structures and N layers of stacked second redistribution structures, where N is an integer greater than 2, wherein:

[0102] The first layer of the second encapsulation structure encapsulates the first redistribution structure and the second chip to be packaged in the first layer of the second encapsulation structure, and the Nth layer of the second encapsulation structure encapsulates the N-1th layer of the second redistribution structure and the second chip to be packaged in the Nth layer of the second encapsulation structure;

[0103] The second chip to be packaged in the second encapsulation structure of the first layer is partially stacked on the first chip to be packaged, and the second chip to be packaged in the second encapsulation structure of the Nth layer is partially stacked on the second chip to be packaged in the second encapsulation structure of the N-1th layer;

[0104] The second rewiring structure of the first layer is electrically connected to the front surface of the second chip to be packaged in the second encapsulation structure of the first layer and the first rewiring structure, and the second rewiring structure of the Nth layer is electrically connected to the front surface of the second chip to be packaged in the second encapsulation structure of the Nth layer and the second rewiring structure of the N-1th layer.

[0105] In this embodiment, the number of layers of the second encapsulation structure and the number of layers of the second redistribution structure are both 7. The 7 layers of the second encapsulation structure are respectively the first second encapsulation structure 31, the second second encapsulation structure 32, the third second encapsulation structure 33, the fourth second encapsulation structure 34, the fifth second encapsulation structure 35, the sixth second encapsulation structure 36, and the seventh second encapsulation structure 37; and the 7 layers of the second redistribution structure are respectively the first second redistribution structure 61, the second second redistribution structure 62, the third second redistribution structure 63, the fourth second redistribution structure 64, the fifth second redistribution structure 65, the sixth second redistribution structure 66, and the seventh second redistribution structure 67.

[0106] Specifically, after completing steps 300 to S500 for the first time, as shown in Figure 5(a), the obtained structure encapsulates the first redistribution structure 50 and the second chip to be packaged 291 in the first layer of the second encapsulation structure 31; the second chip to be packaged 291 in the first layer of the second encapsulation structure 31 is partially stacked on the first chip to be packaged 11; the first layer of the second redistribution structure 61 is electrically connected to the front side 291a of the second chip to be packaged 291 in the first layer of the second encapsulation structure 31, and the first redistribution structure 50.

[0107] Furthermore, the second chip to be packaged 291 in the first layer of the second encapsulation structure 31 is attached to the first surface 10 a of the first encapsulation structure 10 through the adhesive layer 30 .

[0108] After repeating steps 300 to S500 six times, as shown in FIG5(b), in the obtained structure, the 7th-layer second encapsulation structure 37 encapsulates the 6th-layer second redistribution structure 56 and the second chip to be packaged 296 in the 6th-layer second encapsulation structure 36; similarly, the 6th-layer second encapsulation structure 36 encapsulates the 5th-layer second redistribution structure 65 and the second chip to be packaged 295 in the 5th-layer second encapsulation structure 35, and so on.

[0109] In addition, the second chip to be packaged 292 in the second-layer second encapsulation structure 32 is mounted on the first surface 31a of the first-layer second encapsulation structure 31 through the adhesive layer 30, and the second chip to be packaged 293 in the third-layer second encapsulation structure 33 is mounted on the first surface 32a of the second-layer second encapsulation structure 32 through the adhesive layer 30, and so on.

[0110] The second chip to be packaged 297 in the 7th layer of the second encapsulation structure 37 is partially stacked on the second chip to be packaged 296 in the 6th layer of the second encapsulation structure 36; similarly, the second chip to be packaged 296 in the 6th layer of the second encapsulation structure is partially stacked on the second chip to be packaged 295 in the 5th layer of the second encapsulation structure 35, and so on.

[0111] The 7th-layer second rewiring structure 67 is electrically connected to the front side 297a of the second chip to be packaged 297 in the 7th-layer second encapsulation structure 37 and the 6th-layer second rewiring structure 66; similarly, the 6th-layer second rewiring structure 56 is electrically connected to the front side 296a of the second chip to be packaged 296 in the 6th-layer second encapsulation structure 36 and the 5th-layer second rewiring structure 65, and so on.

[0112] Preferably, the first redistribution structure 50 is formed above one end of the first chip to be packaged 11, so as to leave a certain space for the second chip to be packaged 291 in the first layer second encapsulation structure 31 which needs to be partially stacked on the first chip to be packaged 11 in the subsequent steps; for the same purpose, the first layer second redistribution structure 61 is formed above one end of the second chip to be packaged 291 in the first layer second encapsulation structure 31, the second layer second redistribution structure 62 is formed above one end of the second chip to be packaged 292 in the second layer second encapsulation structure 32, and so on, until the sixth layer second redistribution structure 66 is formed above one end of the second chip to be packaged 296 in the sixth layer second encapsulation structure 36. Among them, the positions of one end of the first chip to be packaged 11 and one end of the second chip to be packaged in the second encapsulation structure of each of the six layers except the 7th layer (the last layer) correspond to each other, that is, the first redistribution structure 50 and the second redistribution structure of each layer (except the second redistribution structure of the last layer) are located above one end of the corresponding position of the stacked first chip to be packaged 11 and each second chip to be packaged, forming a stepped redistribution structure connected in sequence, and concentrated on the same side of all stacked chips to be packaged (including the first chip to be packaged 11 and multiple second chips to be packaged).

[0113] In order to correspond to the first rewiring structure 50 being formed above one end of the first chip to be packaged 11, when the solder pad position of the first chip to be packaged 11 is not within the positive projection of the first rewiring structure 50, a rewiring layer (not shown in the figure) can be formed on the front side of the first chip to be packaged 11, thereby adjusting the position of the electrical connection point to meet the requirements of the electrical connection position.

[0114] Similarly, in order to correspond to the second rewiring structure of the upper layer formed above one end of the second chip to be packaged of the second encapsulation structure of the lower layer, when the pad position of the second chip to be packaged of the second encapsulation structure of the lower layer is not within the positive projection of the second rewiring structure of the upper layer, a rewiring layer (not shown in the figure) can be formed on the front of the second chip to be packaged, thereby adjusting the position of the electrical connection point to meet the requirements of the electrical connection position.

[0115] Optionally, as shown in FIG5(c), a dielectric layer 70 is formed on the last layer of the second redistribution structure (i.e., the seventh layer of the second redistribution structure 67). That is, the dielectric layer 70 is formed on the seventh layer of the second redistribution structure 67 and the first surface 37a of the exposed seventh layer of the second encapsulation structure 37. The dielectric layer 70 can be formed by molding film, or the dielectric layer 70 can be formed by lamination or printing. The dielectric layer 70 can be made of an insulating material, such as one or more of polyimide, epoxy resin, and PBO (Polybenzoxazole), preferably an epoxy compound. The end of the seventh layer of the second redistribution structure 67 away from the seventh layer of the second encapsulation structure 37 is exposed on a surface of the dielectric layer 70 away from the seventh layer of the second encapsulation structure 37.

[0116] The final semiconductor packaging structure is electrically connected to the outside through the last layer of the second redistribution structure (i.e., the 7th layer of the second redistribution structure 67). Therefore, the last layer of the second redistribution structure (i.e., the 7th layer of the second redistribution structure 67) serves as the final electrical lead-out component and can be formed at any position above the second chip to be packaged (the second chip to be packaged 297) in the last layer of the second encapsulation structure (the 7th layer of the second encapsulation structure 37).

[0117] Optionally, before proceeding to step 600, as shown in FIG5(d), the process further includes thinning the second surface 10b of the first encapsulation structure 10. By grinding or polishing the second surface 10b of the first encapsulation structure 10 to reduce the thickness of the first encapsulation structure 10, the overall volume of the final semiconductor package structure can be further reduced.

[0118] Next, in step 600, as shown in FIG5(e), the support plate 4 is peeled off to obtain the final semiconductor package structure as shown in FIG5(e). Figure 6 shown.

[0119] like Figure 6 As shown, this embodiment also provides a semiconductor structure 1 manufactured by the above-mentioned semiconductor packaging method. The overall structure of the semiconductor structure 1 of this embodiment is basically the same as that of the structure in Example 1, except that the semiconductor packaging structure includes N layers of the second encapsulation structure and N layers of the second redistribution structure, where N is an integer greater than 2, wherein:

[0120] The first second encapsulation structure of the first layer encapsulates the first redistribution structure and the second chip in the first second encapsulation structure; the second encapsulation structure of the Nth layer encapsulates the second redistribution structure of the Nth layer and the second chip in the Nth second encapsulation structure;

[0121] The second chip in the second encapsulation structure of the first layer is partially stacked on the first chip, and the second chip in the second encapsulation structure of the Nth layer is partially stacked on the second chip in the second encapsulation structure of the N-1th layer;

[0122] The second rewiring structure of the first layer is electrically connected to the front surface of the second chip in the second encapsulation structure of the first layer and the first rewiring structure, and the second rewiring structure of the Nth layer is electrically connected to the front surface of the second chip in the second encapsulation structure of the Nth layer and the second rewiring structure of the N-1th layer.

[0123] As described above, in this embodiment, the number of layers of the second encapsulation structure and the number of layers of the second redistribution structure are both 7 layers.

[0124] The first-layer second encapsulation structure 31 encapsulates the first redistribution structure 50 and the second chip 291 in the first-layer second encapsulation structure 31; the seventh-layer second encapsulation structure 37 encapsulates the sixth-layer second redistribution structure 56 and the second chip 296 in the sixth-layer second encapsulation structure 36; similarly, the sixth-layer second encapsulation structure 36 encapsulates the fifth-layer second redistribution structure 65 and the second chip 295 in the fifth-layer second encapsulation structure 35, and so on.

[0125] The second chip 291 in the first-layer second encapsulation structure 31 is partially stacked on the first chip 11; the second chip 297 in the seventh-layer second encapsulation structure 37 is partially stacked on the second chip 296 in the sixth-layer second encapsulation structure 36; similarly, the second chip 296 in the sixth-layer second encapsulation structure is partially stacked on the second chip 295 in the fifth-layer second encapsulation structure 35, and so on.

[0126] The first-layer second redistribution structure 61 is electrically connected to the front surface 291a of the second chip to be packaged 291 in the first-layer second encapsulation structure 31 and the first redistribution structure 50; the seventh-layer second redistribution structure 67 is electrically connected to the front surface 297a of the second chip to be packaged 297 in the seventh-layer second encapsulation structure 37 and the sixth-layer second redistribution structure 66; similarly, the sixth-layer second redistribution structure 56 is electrically connected to the front surface 296a of the second chip to be packaged 296 in the sixth-layer second encapsulation structure 36 and the fifth-layer second redistribution structure 65, and so on.

[0127] In addition, the second chip 291 in the first-layer second encapsulation structure 31 is mounted on the first surface 10a of the first encapsulation structure 10 through the adhesive layer 30; the second chip 292 in the second-layer second encapsulation structure 32 is mounted on the first surface 31a of the first-layer second encapsulation structure 31 through the adhesive layer 30, and the second chip 293 in the third-layer second encapsulation structure 33 is mounted on the first surface 32a of the second-layer second encapsulation structure 32 through the adhesive layer 30, and so on.

[0128] Preferably, the first redistribution structure 50 is formed above one end of the first chip 11 to leave a certain space for the second chip 291 in the first-layer second encapsulation structure 31, which needs to be partially stacked on the first chip 11 in subsequent steps; for the same purpose, the first-layer second redistribution structure 61 is formed above one end of the second chip 291 in the first-layer second encapsulation structure 31, the second-layer second redistribution structure 62 is formed above one end of the second chip 292 in the second-layer second encapsulation structure 32, and so on, until the sixth-layer second redistribution structure 66 is formed above one end of the second chip 296 in the sixth-layer second encapsulation structure 36. Among them, the positions of one end of the first chip 11 and one end of the second chip in the second encapsulation structure of each of the six layers except the seventh layer correspond to each other, that is, the first redistribution structure 50 and the second redistribution structure of each layer (except the second redistribution structure of the last layer) are located above one end of the corresponding position of the stacked first chip 11 and each second chip, forming a stepped redistribution structure connected in sequence, and concentrated on the same side of all stacked chips to be packaged (including the first chip to be packaged 11 and multiple second chips to be packaged).

[0129] The final semiconductor packaging structure is electrically connected to the outside through the last layer of the second redistribution structure (i.e., the 7th layer of the second redistribution structure 67). Therefore, the last layer of the second redistribution structure (i.e., the 7th layer of the second redistribution structure 67) serves as the final electrical lead-out component and can be formed at any position above the second chip (second chip 297) in the last layer of the second encapsulation structure (the 7th layer of the second encapsulation structure 37).

[0130] In order to correspond to the first rewiring structure 50 being formed above one end of the first chip 11, when the pad position of the first chip 11 is not within the positive projection of the first rewiring structure 50, a rewiring layer (not shown in the figure) can be formed on the front side of the first chip 11, thereby adjusting the position of the electrical connection point to meet the requirements of the electrical connection position.

[0131] Similarly, in order to correspond to the second rewiring structure of the upper layer formed above one end of the second chip of the lower second encapsulation structure, when the pad position of the second chip of the lower second encapsulation structure is not within the positive projection of the second rewiring structure of the upper layer, a rewiring layer (not shown in the figure) can be formed on the front of the second chip, thereby adjusting the position of the electrical connection point to meet the requirements of the electrical connection position.

[0132] Optionally, the semiconductor package structure 1 further includes a dielectric layer 70. The dielectric layer 70 is formed on the last layer of the second redistribution structure (i.e., the 7th layer of the second redistribution structure 67), that is, the dielectric layer 70 is formed on the 7th layer of the second redistribution structure 67 and the first surface 37a of the exposed 7th layer of the second encapsulation structure 37. The dielectric layer 70 can be formed by molding film, or the dielectric layer 70 can be formed by lamination or printing. The dielectric layer 70 can be made of an insulating material, such as one or more of polyimide, epoxy resin, and PBO (Polybenzoxazole), preferably an epoxy compound. The end of the 7th layer of the second redistribution structure 67 away from the 7th layer of the second encapsulation structure 37 is exposed on a surface of the dielectric layer 70 away from the 7th layer of the second encapsulation structure 37.

[0133] The semiconductor packaging method and structure provided in this embodiment address the structural fragility of ultra-thin chips by separately packaging the first chip and each layer of the multi-layer second chip. Each layer of chips is packaged with support, thus eliminating the limitation of the number of chip stacking layers and forming a structure in which the chips and connecting circuits are continuously interconnected and stacked. Furthermore, a rewiring structure is used to achieve electrical connection from the front of the first and second chips. Compared to the conventional prior art method of achieving electrical connection through wires, the rewiring structure requires less space, particularly in the thickness direction. Furthermore, the rewiring structure provides more flexible layout and more reliable connection.

[0134] In this application, the structural embodiments and method embodiments may complement each other if they do not conflict.

[0135] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A packaging method for a semiconductor packaging structure, characterized in that: It includes the following steps: S1: Providing a first encapsulation structure and attaching the first encapsulation structure to a support plate, wherein the first encapsulation structure encapsulates a first chip to be packaged, the first chip to be packaged comprising a front surface and a back surface opposite to each other, and is encapsulated by a first encapsulation layer, the first encapsulation structure comprising a first surface and a second surface opposite to each other, the front surface of the first chip to be packaged corresponding to the first surface of the first encapsulation structure, and the second surface of the first encapsulation structure facing the support plate; S2: forming a first redistribution structure on the first surface of the first encapsulation structure, wherein the first redistribution structure is electrically connected to the front surface of the first chip to be packaged; The first redistribution structure is partially stacked on the first chip to be packaged; S3: Mounting a second chip to be packaged on the first surface of the first encapsulation structure, with the back surface of the second chip to be packaged facing the first surface of the first encapsulation structure, and the second chip to be packaged partially overlapping the first chip to be packaged; The distance between the second chip to be packaged and the surface away from the first encapsulation structure is smaller than the distance between the first redistribution structure and the surface away from the first encapsulation structure. S4: Covering the first redistribution structure and the second chip to be packaged with a second encapsulation layer, and plastic-encapsulating the first redistribution structure and the second chip to be packaged to form a second encapsulation structure, wherein the second encapsulation structure includes a first surface and a second surface opposite to each other, and the front surface of the second chip to be packaged corresponds to the first surface of the second encapsulation structure; S5: forming a second redistribution structure on the first surface of the second encapsulation structure, wherein the second redistribution structure is electrically connected to the first redistribution structure and the front surface of the second chip to be packaged; S6: peeling off the support plate.

2. The packaging method of the semiconductor packaging structure according to claim 1, wherein: Before entering step S6, repeat steps S3 to S5 to obtain N layers of stacked second encapsulation structures and N layers of stacked second redistribution structures, where N is an integer greater than 2, wherein: The first layer of the second encapsulation structure encapsulates the first redistribution structure and the second chip to be packaged in the first layer of the second encapsulation structure, and the Nth layer of the second encapsulation structure encapsulates the N-1th layer of the second redistribution structure and the second chip to be packaged in the Nth layer of the second encapsulation structure; The second chip to be packaged in the second encapsulation structure of the first layer is partially stacked on the first chip to be packaged, and the second chip to be packaged in the second encapsulation structure of the Nth layer is partially stacked on the second chip to be packaged in the second encapsulation structure of the N-1th layer; The second rewiring structure of the first layer is electrically connected to the front surface of the second chip to be packaged in the second encapsulation structure of the first layer and the first rewiring structure, and the second rewiring structure of the Nth layer is electrically connected to the front surface of the second chip to be packaged in the second encapsulation structure of the Nth layer and the second rewiring structure of the N-1th layer.

3. The packaging method of the semiconductor packaging structure according to claim 1 or 2, wherein: The front side of the second chip to be packaged is covered with the second encapsulation layer. Before step S5, the method further includes: forming an opening on the first surface of the second encapsulation structure, wherein the position of the opening corresponds to the front surface of the second chip to be packaged; A conductive pillar is formed in the opening, and the conductive pillar is used to connect the front surface of the second chip to be packaged and the second redistribution structure.

4. The packaging method of the semiconductor packaging structure according to claim 1, wherein: The first redistribution structure is formed above one end of the first chip to be packaged; the second redistribution structure can be formed at any position above the second chip to be packaged.

5. The packaging method of the semiconductor packaging structure according to claim 2, wherein: The second redistribution structure of the first layer is formed above one end of the second chip to be packaged in the second encapsulation structure of the first layer, the second redistribution structure of the N-1 layer is formed above one end of the second chip to be packaged in the second encapsulation structure of the N-1 layer, and the second redistribution structure of the N layer can be formed at any position above the second chip to be packaged in the second encapsulation structure of the N layer; wherein the positions of one end of the first chip to be packaged and one end of the second chip to be packaged in the second encapsulation structure of each layer in the N-1 layer correspond to each other.

6. A semiconductor packaging structure, characterized in that: It includes: a first encapsulation structure, the first encapsulation structure comprising a first surface and a second surface opposite to each other, the first encapsulation structure encapsulating a first chip via a first encapsulation layer, the front side of the first chip corresponding to the first surface of the first encapsulation structure; a second encapsulation structure, the second encapsulation structure comprising a first surface and a second surface, the second encapsulation structure encapsulating a first redistribution structure and a second chip via a second encapsulation layer, the first redistribution structure being electrically connected to a front surface of the first chip, the second chip being partially stacked on the first chip, the front surface of the second chip corresponding to the first surface of the second encapsulation structure; the first redistribution structure being partially stacked on the first chip; a distance from a surface of the second chip away from the first encapsulation structure to the first encapsulation structure being less than a distance from a surface of the first redistribution structure away from the first encapsulation structure to the first encapsulation structure; A second redistribution structure is formed on the first surface of the second encapsulation structure, and the second redistribution structure is electrically connected to the first redistribution structure and the front surface of the second chip.

7. The semiconductor package structure according to claim 6, wherein: The semiconductor package structure includes N stacked layers of the second encapsulation structure and N stacked layers of the second redistribution structure, where N is an integer greater than 2, wherein: The first second encapsulation structure of the first layer encapsulates the first redistribution structure and the second chip in the first second encapsulation structure; the second encapsulation structure of the Nth layer encapsulates the second redistribution structure of the Nth layer and the second chip in the Nth second encapsulation structure; The second chip in the second encapsulation structure of the first layer is partially stacked on the first chip, and the second chip in the second encapsulation structure of the Nth layer is partially stacked on the second chip in the second encapsulation structure of the N-1th layer; The second rewiring structure of the first layer is electrically connected to the front surface of the second chip in the second encapsulation structure of the first layer and the first rewiring structure, and the second rewiring structure of the Nth layer is electrically connected to the front surface of the second chip in the second encapsulation structure of the Nth layer and the second rewiring structure of the N-1th layer.

8. The semiconductor package structure according to claim 6 or 7, wherein: The front side of the second chip is covered with the second encapsulation layer, and the first surface of the second encapsulation structure is provided with an opening, the position of the opening corresponds to the front side of the second chip; a conductive column is formed in the opening, and the conductive column is used to connect the front side of the second chip and the second redistribution structure.

9. The semiconductor package structure according to claim 7, wherein: The first redistribution structure is located above one end of the first chip, and the second redistribution structure can be located at any position above the second chip.

10. The semiconductor package structure according to claim 8, wherein: The second redistribution structure of the first layer is located above one end of the second chip in the second encapsulation structure of the first layer, the second redistribution structure of the N-1 layer is located above one end of the second chip in the second encapsulation structure of the N-1 layer, and the second redistribution structure of the N layer can be located at any position above the second chip in the second encapsulation structure of the N layer; wherein the positions of one end of the first chip and one end of the second chip in the second encapsulation structure of each layer in the N-1 layer correspond to each other.

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