A packaging method for a heterogeneous coplanar integrated chip

Abstract

The present invention relates to a packaging method for heterogeneous coplanar integrated chips. In a packaging method for heterogeneous coplanar integrated chips, a plurality of bare chips made of different materials and with different manufacturing processes are adhesively fixed on the front surface of a glass substrate with a temporary bonding adhesive on their front sides (bonding pad surfaces). The chips are arranged according to certain rules. A blue film is attached to the back surface of the glass substrate, and through processing by a grinding machine or a thinning machine and optimizing process parameters, coplanar thinning is achieved to the target thickness. Subsequently, debonding is performed to obtain discrete chips with consistent thickness. The discrete chips are pasted on a high thermal conductivity housing, and then coplanar ball planting is carried out, and they are welded at the corresponding bonding pads of a multi-layer wiring substrate through an FC flip chip bonding process to form heterogeneous coplanar integrated chips. The present invention has advantages such as being applicable to product research and development of multiple varieties and small batches, high automation degree, and low cost, and can provide important technical support for the subsequent miniaturization development of three-dimensional heterogeneous integration systems.

Description

Technical Field

[0001] The present invention relates to a packaging method for heterogeneous coplanar integrated chips, and in particular to a preparation method for heterogeneous coplanar integrated chips that realizes flexible panel splicing with the characteristics of multi-variety and small-batch products, which can provide important technical support for the subsequent development of three-dimensional heterogeneous integration packaging. Background Art

[0002] With the development of the miniaturization of integrated circuits, two-dimensional integration technology can no longer meet future application requirements and is gradually turning to three-dimensional integration technology. However, the high R & D cost has made the development of three-dimensional integration technology progress slowly. Re-developing chips and re-modeling the process line will cost huge resources. To reduce the R & D cost, Chinese Patent Publication No. CN111564429A, with a publication date of August 21, 2020, and a title of "A Three-Dimensional Heterogeneous Integrated Chip and Packaging Method for Integrated Circuits" discloses a method of integrating different IC devices together by using processes such as temporary bonding, thinning, and via wiring. This method uses two auxiliary substrates to achieve heterogeneous integration. Although it is feasible, its disadvantages are as follows: The auxiliary substrate on the temporary bonding surface is not a whole and is not removed in the subsequent processing, resulting in an increase in the total thickness; Another auxiliary substrate and a temporary bonding layer are added, and finally transferred to the final substrate layer, and the process is relatively complex; In short, it mainly relies on silicon-based processes, the process is too cumbersome, and the manufacturing cost is high. Summary of the Invention

[0003] The technical problem solved by the present invention is: To overcome the deficiencies of the prior art, provide a low-cost development method for packaging three-dimensional heterogeneous coplanar integrated chips, simplify the process of three-dimensional heterogeneous integration, and optimize the stacking structure.

[0004] The solution to the technical problem of the present invention is: A packaging method for heterogeneous coplanar integrated chips, the method comprising the following steps:

[0005] S1. Bond and fix the solder pads of multiple bare chips with different materials and different manufacturing processes on the front surface of a glass wafer substrate with a temporary bonding adhesive, and cure;

[0006] S2. Stick a blue film on the back surface of the glass substrate, and strengthen the bonding strength by baking;

[0007] S3. Process by a grinding machine or a thinning machine to thin the back surface of the chips to the target thickness, so that multiple bare chips with different materials and different manufacturing processes are coplanar;

[0008] S4. Debond multiple bare chips with different materials and different manufacturing processes to obtain discrete chips with the same thickness;

[0009] S5. Patch the back surface of the discrete chips after debonding on the housing, and cure;

[0010] S6. Perform coplanar and unified ball mounting on the front side of the discrete chips to obtain a heterogeneous integrated chip;

[0011] S7. Flip-chip solder the ball-mounted heterogeneous integrated chip at the corresponding pads of the multi-layer wiring substrate to form a heterogeneous coplanar integrated chip;

[0012] S8. Fill and cure the heterogeneous coplanar integrated chip with underfill adhesive.

[0013] Preferably, in step S1, the chips are arranged according to certain rules, specifically:

[0014] The chips are distributed on the concentric circles centered on the center of the substrate from the inside out in ascending order of material hardness. The chip with the smallest hardness is placed in the innermost circle, and as the concentric circles extend outwards, the outermost circle has the chip with the largest hardness.

[0015] Preferably, the minimum gap between adjacent chips ≥ 1 mm.

[0016] Preferably, the baking temperature in step S2 is 60 - 80 °C, and the time is 10 - 30 min.

[0017] Preferably, the specific operation in step S3 is:

[0018] Place the glass substrate with blue film on a thinning machine or a polishing machine, fix it by vacuum adsorption, and adjust the parameters to thin it at high speed to the target thickness, and the target thickness is 50 - 300 um.

[0019] Preferably, the specific operation in step S4 is:

[0020] Debond the glass wafer substrate and clean it with a cleaning solution to remove the excess.

[0021] Preferably, the housing material of the step is aluminum carbide, diamond copper, aluminum nitride or silicon aluminum alloy.

[0022] Preferably, in step S6, ball mounting is performed by reflow soldering, gold wire ball bonding or laser ball mounting.

[0023] Preferably, the flip-chip soldering in step S7 is one of the three processes of flip-chip reflow soldering, ultrasonic thermocompression bonding, and thermocompression diffusion bonding.

[0024] Preferably, the multi-layer wiring board is a multi-layer printed board, an HTCC ceramic package or a thin film RDL multi-layer wiring substrate.

[0025] The beneficial effects of the present invention compared with the prior art are:

[0026] (1). The present invention can achieve the integration of chips with different materials or different processes, has a wide material compatibility and strong universality.

[0027] (2) The thermal matching problem between heterogeneous materials in the present invention is balanced by the matching degree between the cavity and the internal materials, the metal buffer layer, the filling layer, and the metal balls (columns) in a multi-stage manner, and the three-dimensional structure is stable.

[0028] (3) In the present invention, the chip is directly connected to the high thermal conductivity packaging shell, and the heat is directly exported from the shell, improving the thermal conductivity efficiency.

[0029] (4) The operation process of the present invention is simple, the manufacturing process is short, and it can be achieved under existing industrial conditions. The development cost is low. It is especially suitable for customized production with multiple varieties and small batches, and is also applicable to large-scale industrial production. Brief Description of the Drawings

[0030] Figure 1 It is a flowchart of a packaging method for a three-dimensional heterogeneous coplanar integrated chip in an embodiment of the present invention;

[0031] Figure 2 It is a schematic diagram of the specific embodiment process of step S1;

[0032] Figure 3 It is a schematic diagram of the specific embodiment process of step S2;

[0033] Figure 4 It is a schematic diagram of the specific embodiment process of step S3;

[0034] Figure 5 It is a schematic diagram of the specific embodiment process of step S5;

[0035] Figure 6 It is a schematic diagram of the specific embodiment process of step S6;

[0036] Figure 7 It is a schematic diagram of the specific embodiment process of step S7;

[0037] Figure 8 It is a schematic diagram of the specific embodiment process of step S8. Detailed Embodiment

[0038] The present invention will be further described below in conjunction with embodiments.

[0039] Heterogeneous coplanar integrated chips are distributed on a glass wafer substrate in a partitioned manner, and all chips of the same layer in the same integrated unit are placed in one area. The preparation method of heterogeneous coplanar integrated chips can not only enable chips with different materials and different manufacturing processes to be ball-mounted together, facilitating subsequent flip-chip soldering, but also flexibly adjust the layout for different products, improving efficiency. The present invention uses commercially available bare chips to provide a new solution for the low-cost development of three-dimensional heterogeneous integration technology.

[0040] Such as Figure 1As shown in the figure, the present invention provides a packaging method for a heterogeneous coplanar integrated chip, and the method includes the following steps:

[0041] S1. Bond and fix the solder pads of multiple bare chips with different materials and different manufacturing processes on the front side of a glass wafer substrate using a temporary bonding adhesive, and cure it.

[0042] In the step S1, the chips are arranged according to certain rules, specifically:

[0043] The chips are distributed from the inside to the outside on concentric circles centered on the center of the substrate in the order of increasing material hardness. The chip with the smallest hardness is placed in the innermost circle, and as the concentric circles extend outwards, the outermost circle is the chip with the largest hardness. The minimum gap between adjacent chips ≥ 1 mm. As Figure 2 shown.

[0044] S2. Stick a blue film on the back side of the glass wafer substrate, and strengthen the bonding strength by baking, as Figure 3 shown; the baking temperature is 60 - 80 °C, and the time is 10 - 30 min.

[0045] S3. Through processing by a grinding machine or a thinning machine, thin the back side of the chips to the target thickness, so that multiple bare chips with different materials and different manufacturing processes are coplanar, as Figure 4 shown;

[0046] The specific operation is:

[0047] Place the glass substrate with the blue film on a thinning machine or a polishing machine, fix it by vacuum adsorption, and adjust the parameters to thin it at high speed to the target thickness. The target thickness is 50 - 300 um.

[0048] S4. Debond multiple bare chips with different materials and different manufacturing processes to obtain discrete chips with the same thickness.

[0049] The specific operation of debonding is:

[0050] Debond the glass wafer substrate, and clean it with a cleaning solution to remove the excess.

[0051] S5. Solder the back side of the discrete chips after debonding on the housing and cure it, as Figure 5 shown;

[0052] In this step, an automatic chip mounter is used to bond it to a preset position on a high - thermal - conductivity housing through a conductive adhesive or an insulating adhesive, and cure it.

[0053] For the housing material in the step, packaging materials such as aluminum carbide silicon, diamond copper, or silicon aluminum alloy with high mechanical strength, high thermal conductivity, a thermal expansion coefficient relatively matched with the active chip material, and excellent processing characteristics are selected, so that the composite equivalent thermal conductivity of the entire integrated chip is greater than or equal to 150 W / mK, and the thermal resistance is less than or equal to 0.1 °C / W.

[0054] S6. Perform coplanar ball implantation on the front side (bonding pad surface) of the discrete chip to obtain a heterogeneous integrated chip; use reflow soldering, gold ball bonding or laser ball implantation methods for unified ball implantation, as Figure 6 shown.

[0055] S7. Flip-chip solder the ball-implanted heterogeneous integrated chip at the corresponding bonding pads of the multi-layer wiring substrate to form a heterogeneous coplanar integrated chip, as Figure 7 shown.

[0056] The flip-chip soldering can adopt one of the three processes of flip-chip reflow soldering, ultrasonic thermocompression soldering, and thermocompression diffusion soldering.

[0057] S8. Fill and pattern the heterogeneous coplanar integrated chip with underfill glue, as Figure 8 shown.

[0058] The multi-layer wiring board is a multi-layer printed board, an HTCC ceramic package or a thin film RDL multi-layer wiring substrate.

[0059] The present invention solves the thermal matching problem between heterogeneous materials by the multi-level buffer balance of the matching degree between the cavity and the internal materials, the metal buffer layer, the filling layer, and the metal balls (columns), and has a stable three-dimensional structure; the chip is directly connected to the high thermal conductivity package housing, and the heat is directly exported from the housing, improving the thermal conductivity efficiency.

[0060] Although the present invention has been disclosed above with preferred embodiments, it is not used to limit the present invention. Any person skilled in the art can make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the technical solution of the present invention all belong to the protection scope of the technical solution of the present invention.

Claims

1. A packaging method for a heterogeneous coplanar integrated chip, characterized in that it includes the following steps: S1. Bond and fix the solder pads of multiple bare chips with different materials and different manufacturing processes on the front side of a glass wafer substrate using a temporary bonding adhesive, and cure it; S2. Attach a blue film to the back side of the glass substrate, and strengthen the bonding strength through baking; S3. Through processing by a grinding machine or a thinning machine, thin the back side of the chips to a target thickness, so that multiple bare chips with different materials and different manufacturing processes are coplanar; S4. Debond multiple bare chips with different materials and different manufacturing processes to obtain discrete chips with the same thickness; S5. Solder the back sides of the debonded discrete chips onto a high thermal conductivity packaging housing, and cure it; S6. Perform coplanar and unified ball planting on the front sides of the discrete chips to obtain a heterogeneous integrated chip; S7. Flip-chip solder the ball-planted heterogeneous integrated chip to the corresponding solder pads on a multi-layer wiring substrate to form a heterogeneous coplanar integrated chip; S8. Fill the heterogeneous coplanar integrated chip with an underfill adhesive and cure it.

2. The packaging method for a heterogeneous coplanar integrated chip according to claim 1, characterized in that the chips in step S1 are arranged according to a certain rule, specifically: The chips are distributed from the inside to the outside on concentric circles centered on the center of the substrate in ascending order of material hardness. The chip with the smallest hardness is placed in the innermost circle, and as the concentric circles extend outwards, the outermost circle is the chip with the largest hardness.

3. The packaging method for a heterogeneous coplanar integrated chip according to claim 2, characterized in that The minimum gap between adjacent chips ≥ 1 mm.

4. The packaging method for a heterogeneous coplanar integrated chip according to claim 1, characterized in that The baking temperature in step S2 is 60 - 80 °C, and the time is 10 - 30 min.

5. The packaging method for a heterogeneous coplanar integrated chip according to claim 1, characterized in that The specific operation of step S3 is: Place the glass substrate with the blue film on a thinning machine or a polishing machine, fix it by vacuum adsorption, and adjust the parameters to thin it at high speed to the target thickness, and the target thickness is 50 - 300 um.

6. The packaging method for a heterogeneous coplanar integrated chip according to claim 1, characterized in that The specific operation of step S4 is: Debond the glass wafer substrate, and clean it with a cleaning solution to remove the residues.

7. The packaging method for a heterogeneous coplanar integrated chip according to claim 1, characterized in that The material of the housing in the step is aluminum carbide, diamond copper, aluminum nitride or silicon aluminum alloy.

8. The packaging method for a heterogeneous coplanar integrated chip according to claim 1, characterized in that The ball planting in step S6 is carried out by reflow soldering, gold wire ball bonding or laser ball planting.

9. The packaging method for a heterogeneous coplanar integrated chip according to claim 1, characterized in that The flip-chip soldering in step S7 is one of the three processes of flip-chip reflow soldering, ultrasonic thermocompression soldering, and thermocompression diffusion soldering.

10. The packaging method for a heterogeneous coplanar integrated chip according to claim 1, characterized in that The multi-layer wiring substrate is a multi-layer printed circuit board, an HTCC ceramic package or a thin film RDL multi-layer wiring substrate.

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