Method of monitoring wafer impurities

Abstract

The application provides a method for monitoring wafer impurities, comprising: connecting all N-type well regions in series; connecting all P-type well regions in series; applying a test voltage to the P-type well regions, grounding the N-type well regions, measuring the current of the P-type well regions, or applying a test voltage to the N-type well regions, grounding the P-type well regions, measuring the current of the N-type well regions; if the current of the N-type well regions or the current of the P-type well regions measured suddenly changes, the wafer is considered to contain impurities. Compared with the prior art, the method for detecting wafer impurities of the application can detect whether the wafer contains impurities after the P-type well regions and the N-type well regions are made, so that defective products can be found in advance, the early death of products can be prevented, and meanwhile, the defective products can be found in advance, so that the waste time can be reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor testing, and in particular to a method for monitoring impurities in a wafer. BACKGROUND

[0002] In the manufacturing process of a wafer, due to control problems, one or more metal impurities may be left in the wafer, such as Na ions, Fe ions and Cr ions, etc., but are not cleaned before delivery, and even one or more metal impurities may be present. Thus, in the process of making a transistor in a downstream wafer factory, due to the presence of metal impurities, small square bumps may be found in the active area or in the shallow trench isolation structure.

[0003] In the prior art, the problem of metal impurities is found through slicing or other functional testing only after the entire device is manufactured or after the process behind the gate oxide layer, but at this time, a lot of time is wasted, and the product may be prematurely dead. SUMMARY

[0004] The present application aims to provide a method for monitoring impurities in a wafer, which can monitor the impurities in the wafer in time, select defective products for processing in advance, reduce wasted time, and prevent the product from being prematurely dead.

[0005] To achieve the above-mentioned purpose, the present application provides a method for monitoring impurities in a wafer, the wafer having N-type well regions, P-type well regions and an isolation structure between the N-type well regions and the P-type well regions, comprising:

[0006] connecting all the N-type well regions in series;

[0007] connecting all the P-type well regions in series;

[0008] applying a test voltage to the P-type well regions, the N-type well regions being grounded, measuring the current of the P-type well regions, or applying a test voltage to the N-type well regions, the P-type well regions being grounded, measuring the current of the N-type well regions;

[0009] If the current of the N-type well regions or the current of the P-type well regions measured suddenly changes, and the test voltage at this time is greater than the set voltage, it is considered that the wafer contains impurities.

[0010] Optionally, in the method for monitoring impurities in the wafer, the method for connecting all the P-type well regions in series comprises connecting all the P-type well regions in series through a first metal layer.

[0011] Optionally, in the method for monitoring impurities in the wafer, the method for connecting all the N-type well regions in series comprises connecting all the N-type well regions in series through a second metal layer.

[0012] Optionally, in the method for monitoring the impurities of the wafer, the method for applying the test voltage to the P-type well region comprises: arranging a first test pad in communication with the first metal layer; and applying the test voltage to the first test pad.

[0013] Optionally, in the method for monitoring the impurities of the wafer, the method for applying the test voltage to the N-type well region comprises: arranging a second test pad in communication with the second metal layer; and applying the test voltage to the second test pad.

[0014] Optionally, in the method for monitoring the impurities of the wafer, the test voltage applied to the P-type well region is a sweep voltage.

[0015] Optionally, in the method for monitoring the impurities of the wafer, the test voltage applied is less than -12V.

[0016] Optionally, in the method for monitoring the impurities of the wafer, the test voltage applied to the N-type well region is a sweep voltage.

[0017] Optionally, in the method for monitoring the impurities of the wafer, the test voltage applied is less than -12V.

[0018] Optionally, in the method for monitoring the impurities of the wafer, the impurities comprise metal particles attached to the N-type well region or the P-type well region and located in the isolation structure.

[0019] In the method for monitoring the impurities of the wafer, all the N-type well regions are connected in series, all the P-type well regions are connected in series, a test voltage is applied to the P-type well region, the N-type well region is grounded, the current of the P-type well region is measured, or a test voltage is applied to the N-type well region, the P-type well region is grounded, and the current of the N-type well region is measured; if the current of the N-type well region or the current of the P-type well region changes suddenly, it is considered that the wafer contains impurities. Compared with the prior art, the method for monitoring the impurities of the wafer can detect whether the wafer contains impurities after the P-type well region and the N-type well region are manufactured, so that defective products can be found in advance, the early death of products can be prevented, and the waste of time can be reduced. BRIEF DESCRIPTION OF DRAWINGS

[0020] Figure 1 is a structural schematic diagram of a device wafer of an embodiment of the present application;

[0021] Figure 2 is a flowchart of a method for monitoring the impurities of a wafer of an embodiment of the present application;

[0022] Figure 3is a schematic diagram of monitoring wafer impurities according to an embodiment of the present application;

[0023] Figure 4 is a curve of testing current according to an embodiment of the present application;

[0024] In the figure: 110-first P-type well region, 120-second P-type well region, 130-first metal layer, 140-first test pad, 210-first N-type well region, 220-second N-type well region, 230-second metal layer, 240-second test pad, 310-isolation structure, 320-gate oxide layer. DETAILED DESCRIPTION

[0025] The specific embodiments of the present application will be described in detail below with reference to the accompanying drawings. The advantages and features of the present application will be more apparent from the following description. It should be noted that the drawings are very simplified and all use non-precise proportions, only to facilitate, clear and assist in the purpose of illustrating the embodiments of the present application.

[0026] In the following, the terms "first", "second", etc. are used to distinguish between similar elements, and are not necessarily used to describe a particular order or time sequence. It is understood that these terms as used can be replaced under appropriate circumstances. Similarly, if the method described herein includes a series of steps, and the order of these steps presented herein is not necessarily the only order in which these steps can be performed, and some of the steps described can be omitted and / or some other steps not described herein can be added to the method.

[0027] The wafer has N-type well regions, P-type well regions and isolation structures between the N-type well regions and P-type well regions, the wafer includes a plurality of N-type well regions and a plurality of P-type well regions, even a plurality of N-type well regions and a plurality of P-type well regions, one N-type well region corresponds to one P-type well region, and the N-type well regions are separated by P-type well regions, and similarly, the P-type well regions are separated by N-type well regions, and each P-type well region and N-type well region are separated by an isolation structure. Specifically, please refer to Figure 1 Taking two P-type well regions and two N-type well regions as an example, the figure includes a first P-type well region 110, a first N-type well region 210, a second P-type well region 120 and a second N-type well region 220, and a gate oxide layer on the surface of the first P-type well region 110, the first N-type well region 210, the second P-type well region 120 and the second N-type well region 220, the first P-type well region 110 and the first N-type well region 210 are separated by an isolation structure 310, the first N-type well region 210 and the second P-type well region 120 are separated by an isolation structure 310, and the second P-type well region 120 and the second N-type well region 220 are separated by an isolation structure 310.

[0028] Please refer to Figure 2The application provides a method for monitoring wafer impurities, comprising:

[0029] connecting all N-type well regions in series;

[0030] connecting all P-type well regions in series;

[0031] applying a test voltage to the P-type well region, grounding the N-type well region, measuring the current of the P-type well region, or applying a test voltage to the N-type well region, grounding the P-type well region, and measuring the current of the N-type well region;

[0032] if the current of the N-type well region or the current of the P-type well region changes suddenly, and the test voltage at this time is greater than the set voltage, it is considered that the wafer contains impurities.

[0033] Specifically, please refer to Figure 3 Still taking two P-type well regions and two N-type well regions as an example, the method for connecting all P-type well regions in series comprises: connecting all P-type well regions in series through the first metal layer 130, that is, connecting the first P-type well region 110 and the second P-type well region 120 in communication through the first metal layer 130, so as to realize the series connection of the first P-type well region 110 and the second P-type well region 120. The method for connecting all N-type well regions in series comprises: connecting all N-type well regions in series through the second metal layer 230, that is, connecting the first N-type well region 210 and the second N-type well region 220 in communication through the second metal layer 230, so as to realize the series connection of the first N-type well region 210 and the second N-type well region 220. If there are more P-type well regions and N-type well regions in other embodiments of the application, the method is also used to connect all P-type well regions in series and connect all N-type well regions in series.

[0034] Further, the method of applying a test voltage to the P-type well region includes: providing a first test pad 140, the first test pad 140 being in communication with the first metal layer 130, the first test pad 140 can be provided anywhere on the first metal layer 130 or electrically connected to the first metal layer 130, the test voltage can be conveniently applied through the test pad; applying a test voltage to the first test pad 140. The method of applying a test voltage to the N-type well region includes: providing a second test pad 240, the second test pad 240 being in communication with the second metal layer 230; applying a test voltage to the second test pad 240. The specific test method can be: applying a test voltage to the first test pad 140, the second test pad 240 is grounded, a capacitor is formed between all P-type well regions and all N-type well regions, the isolation structure 310 is the insulating layer of the capacitor, the series structure of the P-type well region is equivalent to the upper plate, and the series structure of the N-type well region is equivalent to the lower plate. The test current on the N-type well region under the corresponding working test voltage is measured. If the test current is greater than the set breakdown current, the wafer has failed due to other reasons and is a defective product. If the test current is less than the set breakdown current, the test voltage starts to rise uniformly from the set working voltage until the isolation structure 310. With the steady increase of the test voltage, the test current should also increase steadily, but if the test current suddenly changes, it means that the isolation structure 310 is broken down. The breakdown voltage at this time is checked. If the breakdown voltage is lower than the set voltage, when the breakdown voltage of the test sample is lower than the set voltage standard, it is considered that it is caused by the defects (intrinsic defects or impurity defects) existing in the isolation structure 310, and it is determined to be failed. Similarly, the test voltage can also be applied to the second test pad 240, and the first test pad 140 is grounded. The test current on the P-type well region under the corresponding working test voltage is measured. With the steady increase of the test voltage, the test current should also increase steadily, but if the test current suddenly changes, it means that the isolation structure 310 is broken down. The breakdown voltage at this time is checked. If the breakdown voltage is lower than the set voltage, it is considered that it is caused by the defects (intrinsic defects or impurity defects) existing in the isolation structure 310. For example, Figure 4 A graph of the test current can be seen that the test current increases steadily in the first half and suddenly changes in the second half.

[0035] Further, the test voltage applied to the P-type well region is a sweep voltage. The applied test voltage is less than -12V. Similarly, the test voltage applied to the N-type well region is a sweep voltage. The applied test voltage is less than -12V.

[0036] In the embodiment of the present application, the impurities include metal particles attached to the N-type well region or the P-type well region and located in the isolation structure. If the metal particles are attached to the N-type well region or the P-type well region and located in the isolation structure, generally, the metal particles may be because the wafer contains particles before, and the particles enter the N-type well region or the P-type well region or the isolation structure when the N-type well region or the P-type well region and the isolation structure are subsequently formed, so the wafer whether contains impurities can be detected through detection of the N-type well region or the P-type well region and the isolation structure.

[0037] In summary, in the method for monitoring wafer impurities provided by the embodiment of the present application, all N-type well regions are connected in series, all P-type well regions are connected in series, a test voltage is applied to the P-type well region, the N-type well region is grounded, the current of the P-type well region is measured, or a test voltage is applied to the N-type well region, the P-type well region is grounded, and the current of the N-type well region is measured, and if the current of the N-type well region or the current of the P-type well region measured suddenly changes, it is considered that the wafer contains impurities. Compared with the prior art, the method for detecting wafer impurities of the present application can detect whether the wafer contains impurities after the P-type well region and the N-type well region are manufactured, so that defective products can be found in advance, and the early death of products can be prevented. At the same time, the defective products are found in advance, and the wasted time can be reduced.

[0038] The above is only the preferred embodiment of the present application, and does not limit the present application in any way. Any person skilled in the art can make any form of equivalent replacement, modification or change to the technical solutions and technical contents disclosed by the present application without departing from the scope of the technical solutions of the present application, and such changes still belong to the protection scope of the present application.

Claims

1. A method for monitoring wafer impurities, wherein the wafer has an N-type well region, a P-type well region, and an isolation structure located between the N-type well region and the P-type well region, characterized in that, The method for connecting all P-type well regions in series comprises connecting all P-type well regions in series through a first metal layer. The method for connecting all N-type well regions in series comprises connecting all N-type well regions in series through a second metal layer. The method for applying a test voltage to the P-type well regions comprises providing a first test pad in communication with the first metal layer and applying a test voltage to the first test pad. The method for applying a test voltage to the N-type well regions comprises providing a second test pad in communication with the second metal layer and applying a test voltage to the second test pad. The test voltage applied to the P-type well regions is a sweep voltage. The applied test voltage is less than -12V.

2. The method of claim 1, wherein the step of monitoring the wafer for impurities is performed by a method comprising: The test voltage applied to the N-type well regions is a sweep voltage.

3. The method of claim 1, wherein the step of monitoring the wafer for impurities is performed by a method comprising: The applied test voltage is less than -12V.

4. The method of claim 2, wherein the step of monitoring the wafer for impurities is performed by a method comprising: The test voltage applied to the P-type well regions is a sweep voltage.

5. The method of claim 3, wherein the step of monitoring the wafer for impurities comprises the step of: The applied test voltage is less than -12V. ​ 6. The method of claim 1, wherein the step of monitoring the wafer for impurities is performed by a method comprising: The test voltage applied to the N-type well regions is a sweep voltage.

7. The method for monitoring wafer impurities as described in claim 1, characterized in that, The applied test voltage is less than -12V.

8. The method for monitoring wafer impurities as described in claim 1, characterized in that, The test voltage applied to the P-type well regions is a sweep voltage.

9. The method for monitoring wafer impurities as described in claim 1, characterized in that, The applied test voltage is less than -12V. The test voltage applied to the N-type well regions is a sweep voltage. The applied test voltage is less than -12V. The test voltage applied to the P-type well regions is a sweep voltage. The applied test voltage is less than -12V. The test voltage applied to the N-type well regions is a sweep voltage. The applied test voltage is less than -12V. The test voltage applied to the P-type well regions is a sweep voltage. The applied test voltage is less than -12V. The test voltage applied to the N-type well regions is a sweep voltage. The applied test voltage is less than -12V. The test voltage applied to the P-type well regions is a sweep voltage. The applied test voltage is less than -12V. The test voltage applied to the N-type well regions is a sweep voltage. The applied test voltage is less than -12V. The test voltage applied to the P-type well regions is a sweep voltage. The applied test voltage is less than -12V. The test voltage applied to the N-type well regions is a sweep voltage. The applied test voltage is less than -12V. The test voltage applied to the P-type well regions is a sweep voltage. The applied test voltage is less than -12V. The test voltage applied to the N-type well regions is a sweep voltage. The applied test voltage is less than -12V. The test voltage applied to the P-type well regions is a sweep voltage. The applied test voltage is less than -12V. The test voltage applied to the N-type well regions is a sweep voltage. The applied test voltage is less than -12V. The test voltage applied to the P-type well regions is a sweep voltage. The applied test voltage is less than -12V. The test voltage applied to the N-type well regions is a sweep voltage. The applied test voltage is less than -12V. The test voltage applied to the P-type well regions is a sweep voltage. The applied test voltage is less than -12V. The test voltage applied to the N-type well regions is a sweep voltage. The applied test voltage is less than -12V. The test voltage applied to the P-type well regions is a sweep voltage. The applied test voltage is less than -12V. The test voltage applied to the N-type well regions is a sweep voltage. The applied test voltage is less than -12V. The test voltage applied to the P-type well regions is a sweep voltage. The applied test voltage is less than -12V. The test voltage applied to the N-type well regions is a sweep voltage. The applied test voltage is less than -12V. The test voltage applied to the P-type well regions is a sweep voltage. The applied test voltage is less than -12V. The test voltage applied

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