NMOS Structure, Preparation Method and Semiconductor Device

Abstract

The present invention provides an NMOS structure, a preparation method and a semiconductor device. The preparation method includes providing a substrate; forming a plurality of fin structures on the substrate; forming a gate oxide layer on the surface of the fin structures, depositing an isolation layer between the fin structures, and forming a gate material layer above the isolation layer and the gate oxide layer of the fin structures; patterning the gate material layer to form a plurality of gate lines, forming a gate spacer trench between adjacent gate lines, and forming a sidewall isolation layer on the surface of the obtained structure; forming an opening area; sequentially forming a nucleation region layer and a high-phosphorus doped region layer inside the opening area, and removing the impurity layer on the surface of the high-phosphorus doped region layer to form a source or a drain. The present invention improves the stress of the NMOS channel, reduces the bulk resistance and contact resistance of the NMOS source-drain region, and improves the product yield.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit manufacturing, and particularly to an NMOS structure, a preparation method and a semiconductor device. Background Art

[0002] As microelectronics technology develops towards higher performance, the complementary metal oxide semiconductor (CMOS) integration process technology has introduced many new technologies. Among them, the strained silicon technology is introduced at the 90nm node, and the strained silicon technology has become a technology that can effectively improve the performance of transistors in the field of integrated circuits. As is well known, introducing tensile strain into the channel of an N-type metal-oxide-semiconductor (NMOS) and compressive strain into the channel of a P-type metal-oxide-semiconductor (PMOS) can increase the carrier mobility in the channel, thereby improving the transistor performance. The common way to introduce strain is to grow SiGe in the source and drain regions of PMOS devices and grow SiC (or SiP) in the source and drain regions of NMOS devices, so as to introduce strain into their respective channel regions.

[0003] As the technology node develops downward into 3D fin field-effect transistor (FinFET) devices, in order to improve the performance of FinFET devices, it is required to increase the doping concentrations of Ge and B in the source and drain regions of PMOS devices to provide more compressive stress for the PMOS channel and reduce the resistance of the source and drain regions; at the same time, it is required to continuously increase the phosphorus doping concentration in the source and drain regions of NMOS devices to provide more tensile stress for the NMOS channel while effectively reducing the inherent resistance and contact resistance of the source and drain regions. Currently, below the 10nm node, the highest doping concentration of silicon phosphorus in the source and drain regions of NMOS is 2E21 atom / cm -3 , and even reaches 3E21 atom / cm -3 and above. At the same time, theoretical simulations prove that in order to improve the performance of NMOS devices, the phosphorus concentration of silicon phosphorus in the source and drain regions will be continuously increased.

[0004] However, during the preparation of high phosphorus concentration, a high phosphorus source partial pressure will bring side reactions. That is, after the reaction ends, the excess phosphorus will not be removed but deposited on the upper surface of the silicon phosphorus layer, forming a phosphorus-rich silicon phosphorus amorphous layer, which will increase the number of particles in the manufacturing process of product wafers and is not conducive to improving the yield of product wafers. At the same time, the presence of a silicon phosphorus amorphous layer on the surface of the source and drain regions will affect the device performance.

[0005] Therefore, it is necessary to provide a new type of NMOS structure, manufacturing method and semiconductor device to solve the above problems existing in the prior art. Summary of the Invention

[0006] The purpose of the present invention is to provide an NMOS structure, manufacturing method and semiconductor device, which improve the stress of the NMOS channel, reduce the bulk resistance and contact resistance of the NMOS source-drain region, and improve the product yield.

[0007] To achieve the above purpose, the manufacturing method of the NMOS structure of the present invention includes:

[0008] Provide a substrate;

[0009] Form a plurality of fin structures on the substrate;

[0010] Form a gate oxide layer on the surface of the fin structure, deposit an isolation layer between the fin structures, and form a gate material layer above the isolation layer and the gate oxide layer of the fin structure;

[0011] Pattern the gate material layer to form a plurality of gate lines, form a gate spacer trench between adjacent gate lines, and form a sidewall isolation layer on the surface of the obtained structure;

[0012] Etch the sidewall isolation layer, the gate oxide layer and part of the fin structure located on the upper surface of the gate oxide layer along the gate spacer trench to form an opening area;

[0013] Form a nucleation region layer and a high-phosphorus doped region layer in sequence from bottom to top inside the opening area, and remove the impurity layer formed on the surface of the high-phosphorus doped region layer to form a source or drain.

[0014] The beneficial effect of the manufacturing method of the NMOS structure of the present invention is that: by forming a nucleation region layer and a high-phosphorus doped region layer inside the opening area to form a source or drain filled inside the opening area, and removing the impurity layer formed on the surface of the high-phosphorus doped region layer, a higher stress is provided for the NMOS channel, and the bulk resistance and contact resistance of the NMOS source-drain region are reduced. Moreover, by removing the impurity layer on the surface of the high-phosphorus doped region layer, the influence of the impurity layer on the performance of the subsequent formed semiconductor device is avoided, and the yield of the product wafer is effectively improved.

[0015] Optionally, the removing of the impurity layer formed on the surface of the high-phosphorus doped region layer includes:

[0016] Introduce an etching gas and a carrier gas into the surface of the high-phosphorus doped region layer inside the opening area, and perform in-situ etching on the surface of the high-phosphorus doped region layer until the impurity layer on the surface of the high-phosphorus doped region layer is completely removed.

[0017] Optionally, a dry etching or wet cleaning process is used to remove the impurity layer on the surface of the high phosphorus doped region layer.

[0018] Optionally, the formation process of the nucleation region layer includes:

[0019] Introduce a first growth gas source and a first doping gas source into the opening region, adjust the partial pressure ratio of the first doping gas source in the current reaction gas source to a first threshold value, and control the reaction temperature and reaction pressure to form the nucleation region layer on the inner wall of the opening region;

[0020] Continuously introduce the first growth gas source and the first doping gas source until the thickness of the nucleation region layer reaches 2 cm, and then stop introducing the first growth gas source and the first doping gas source.

[0021] Optionally, the formation process of the high phosphorus doped region layer includes:

[0022] Introduce a second growth gas source and a second doping gas source into the opening region where the nucleation region layer is formed, control the partial pressure ratio of the second doping gas source in the current reaction gas source to a second threshold value, and the second threshold value is greater than the first threshold value;

[0023] To form a high phosphorus doped region layer on the surface of the nucleation region layer, and form a vertical slit groove at the middle position of the high phosphorus doped region layer;

[0024] Continuously introduce the second growth gas source and the second doping gas source until the growth rate of the upper surface of the high phosphorus doped region layer decreases to the growth threshold, and then stop introducing the second growth gas source and the second doping gas source.

[0025] Optionally, the reaction temperature during the preparation process of the high phosphorus doped region layer is 550 - 700 degrees Celsius, the reaction pressure is 200 - 600 Torr, the second doping gas source is phosphine gas, and the concentration of the phosphine gas in the second growth gas source is 2E21 - 8E21 atom cm -3 , the partial pressure of the second growth gas source is 30 - 160 Torr, and the partial pressure of the phosphine gas is 15 - 80 Torr.

[0026] Optionally, after removing the impurity layer formed on the surface of the high phosphorus doped region layer, the method further includes performing a high temperature treatment on the surface of the high phosphorus doped region layer to repair the slit groove on the high phosphorus doped region layer.

[0027] Optionally, the method further includes forming a covering region layer on the surface of the high phosphorus doped region layer after removing the impurity layer, and the formation process of the covering region layer includes:

[0028] Gas purge is performed on the surface of the highly phosphorus-doped region layer, and a third growth gas source and a third doping gas source are continuously introduced onto the surface of the highly phosphorus-doped region layer, and the partial pressure ratio of the third doping gas source in the current reaction gas source is adjusted to a third threshold value;

[0029] The reaction pressure is reduced to grow a funnel-shaped covering region layer inside the slit groove and on the surface of the highly phosphorus-doped region layer;

[0030] The third growth gas source and the third doping gas source are continuously introduced until the grown covering region layer completely covers the surface of the highly phosphorus-doped region layer.

[0031] The present invention also provides an NMOS structure, including:

[0032] A substrate;

[0033] A fin structure disposed above the substrate;

[0034] A gate disposed above the fin structure;

[0035] A source electrode disposed at the top region of the fin structure and on one side of the gate;

[0036] A drain electrode disposed at the top region of the fin structure and on the other side of the gate

[0037] Wherein, the source electrode and / or the drain electrode include a nucleation region layer and a highly phosphorus-doped region layer which are sequentially disposed from bottom to top.

[0038] The present invention also provides a semiconductor device including the above NMOS structure.

[0039] The beneficial effect of the preparation method of the NMOS structure according to the present invention is that: by forming a nucleation region layer and a highly phosphorus-doped region layer inside the opening region to form a source electrode or a drain electrode filled inside the opening region, and removing the impurity layer formed on the surface of the highly phosphorus-doped region layer, higher stress can be provided for the NMOS channel, and the bulk resistance and contact resistance of the NMOS source-drain region can be reduced. Moreover, by removing the impurity layer on the surface of the highly phosphorus-doped region layer, the influence of the impurity layer on the performance of the subsequent formed semiconductor device can be avoided, effectively improving the yield of the product wafer. Description of the Drawings

[0040] Figure 1 It is a flowchart of the preparation method of the NMOS structure according to the embodiment of the present invention;

[0041] Figure 2 It is a schematic structural diagram of the preparation method of the NMOS structure according to the embodiment of the present invention after forming the isolation layer;

[0042] Figure 3Schematic diagram of the structure obtained after completing step S103 in the manufacturing method of the NMOS structure according to the embodiment of the present invention;

[0043] Figure 4 Schematic cross-sectional view of the fin structure along the vertical direction of the structure obtained after completing step S104 in the manufacturing method of the NMOS structure according to the embodiment of the present invention;

[0044] Figure 5 Schematic cross-sectional view of the fin structure along the vertical direction of the structure obtained after completing step S105 in the manufacturing method of the NMOS structure according to the embodiment of the present invention;

[0045] Figure 6 Schematic cross-sectional view of the fin structure along the vertical direction of the structure obtained after forming the nucleation region layer and the high phosphorus doped region layer in the manufacturing method of the NMOS structure according to the embodiment of the present invention;

[0046] Figure 7 In the manufacturing method of the NMOS structure according to the embodiment of the present invention Figure 6 Schematic cross-sectional view of the raw material opening region in the vertical direction of the structure;

[0047] Figure 8 In the manufacturing method of the NMOS structure according to the embodiment of the present invention, after removing the impurity layer from the structure Figure 6 Schematic cross-sectional view of the fin structure along the vertical direction of the obtained structure;

[0048] Figure 9 In the manufacturing method of the NMOS structure according to the embodiment of the present invention Figure 8 Schematic cross-sectional view of the fin structure along the vertical direction of the structure;

[0049] Figure 10 In the manufacturing method of the NMOS structure according to the embodiment of the present invention Figure 9 Schematic cross-sectional view of the fin structure along the vertical direction of the obtained structure after forming the covering region layer on the surface of the high phosphorus doped region layer;

[0050] Figure 11 In the manufacturing method of the NMOS structure according to the embodiment of the present invention Figure 2 Magnified schematic diagram of B in; Detailed implementation manners

[0051] To make the objectives, technical solutions, and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the present invention. Apparently, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts fall within the scope of protection of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein shall have the ordinary meanings understood by those of ordinary skill in the art to which the present invention pertains. The words such as "including" used herein mean that the elements or items appearing before this word cover the elements or items listed after this word and their equivalents, without excluding other elements or items.

[0052] In view of the problems existing in the prior art, embodiments of the present invention provide a method for preparing an NMOS structure, referring to Figure 1 , including:

[0053] S101 Provide a substrate.

[0054] Among them, the substrate may be a silicon substrate or a silicon substrate doped with a part of germanium element. In this embodiment, the silicon substrate is used as the substrate.

[0055] S102. Form a plurality of fin structures on the substrate.

[0056] Specifically, the substrate is etched to form a plurality of fin structures on the substrate. By etching the substrate, a plurality of uniformly arranged fin structures are formed on the surface of the substrate. The etching method includes multiple photolithographies and multiple etching steps. The multiple photolithographies include Self-aligned Double Patterning (SADP), Self-Aligned Quadruple Patterning (SAQP), and Litho-Etch-Litho-Etch (LELE).

[0057] In some embodiments, as Figure 11 shown, the protrusion height H of the fin structure is 800 nm to 1600 nm, and the critical dimension L of the fin structure located at the topmost layer is 3 nm to 20 nm.

[0058] S103. Form a gate oxide layer on the surface of the fin structure, deposit an isolation layer between the fin structures, and form a gate material layer above the isolation layer and the gate oxide layer of the fin structure.

[0059] Specifically, a gate oxide layer is formed on the surface of the substrate and the surface of the fin structure, and an isolation layer is deposited between adjacent fin structures. The isolation layer covers the gate oxide layer on the upper surface of the substrate layer, and a gate material layer and a first dielectric layer are sequentially covered on the surface of the isolation layer. Among them, the gate material layer covers the surface of the fin structure and the upper surface of the isolation layer.

[0060] In this embodiment, referring to Figure 2 , after forming a plurality of convex fin structures 101 on the surface of the substrate 100, a gate oxide layer 160 is formed on the upper surface of the substrate 100 and the surface of the fin structure 101.

[0061] Specifically, after depositing a gate oxide material on the surface of the fin structure 101 and the surface of the substrate 100, a gate oxide layer 160 that completely covers the upper surface of the substrate 100 and the outer surface of the fin structure 101 is formed. Among them, the gate oxide material used for the gate oxide layer 160 includes any one or a plurality of composite materials of SiO2, SiON, SiHfO, HfO2, or ZrO2.

[0062] After forming the gate oxide layer 160, referring to Figure 2 , a silicon oxide compound is filled between adjacent fin structures 101, so as to form an isolation layer 102 on the surface of the gate oxide layer 160 on the upper surface of the substrate 100, so as to isolate adjacent fin structures 101 from each other.

[0063] It should be noted that in this solution, the isolation layer 102 is mainly used to isolate the fin structures 101. This solution is not limited to silicon oxide compound materials, and other materials can also be used, which will not be elaborated here.

[0064] Figure 3 This is a schematic diagram of the structure obtained after the preparation method of the NMOS structure of the present invention completes step S103. Referring to Figure 3 , after forming the isolation layer 102, a gate material layer 103 is formed on the surface of the isolation layer 102 by means of deposition and exposure patterning etching, and a first dielectric layer 140 is formed on the surface of the gate material layer 103, so that the gate material layer 130 completely covers the surface of the fin structure 101 and the upper surface of the isolation layer 102. The obtained structure is as Figure 3 shown.

[0065] Specifically, the gate material layer 130 is a doped polysilicon material or a metal gate material. The metal gate material includes any one of TiN, TiAl, TiSiN, and TiAlC. The height of the gate region 130 above the fin structure 101 is 30-80 nm.

[0066] The first dielectric layer 140 is made of a hard mask material, including silicon oxide or silicon nitride material, or a stack of the two materials, as well as a stack of these compounds.

[0067] S104. Pattern the gate material layer to form a plurality of gate lines, form gate spacer grooves between adjacent gate lines, and form a sidewall isolation layer on the surface of the obtained structure.

[0068] In some embodiments, the first dielectric layer is a multi-layer stack. First, pattern the first dielectric layer, and then use the patterned first dielectric layer as a mask to pattern and etch the gate material layer until the gate oxide layer is exposed to form a plurality of gate lines, and form gate spacer grooves between adjacent gate lines.

[0069] Forming a layer of sidewall isolation layer above the obtained structure includes:

[0070] Form a layer of sidewall isolation layer on the surface of the gate lines and the inner walls of the gate spacer grooves, so that the sidewall isolation layer covers the side surfaces of the gate lines, the top of the first dielectric layer, the side walls of the gate spacer grooves, and the gate oxide layer on the top surface of the fin structure.

[0071] Reference Figure 4 , for Figure 3 Perform multiple photolithography and etching operations on the first dielectric layer 140 and the gate material layer 130 in the obtained structure until the gate oxide layer 160 is exposed, thereby forming a plurality of gate lines (not labeled in the figure), where the length direction of the gate lines is perpendicular to the length direction of the fin structure, part of the gate lines are located above the fin structure, part are located above the isolation layer 102, form gate spacer grooves 170 between adjacent gate lines, and then form a sidewall isolation layer 150 covering the side walls of the gate spacer grooves 170, the upper surface of the gate oxide layer 160 inside the gate spacer grooves 170, and the top of the first dielectric layer 140.

[0072] In this embodiment, the second dielectric layer 150 includes any one of SiCON, SiN, and SiO2.

[0073] In still other embodiments, after etching to obtain a plurality of gate spacer grooves 170, the spacing between adjacent gate regions 130 is 10 - 120 nm.

[0074] S105. Etch the sidewall isolation layer on the upper surface of the gate oxide layer, the gate oxide layer, and part of the fin structure along the gate spacer grooves to form an opening region.

[0075] Reference Figure 5 , in Figure 4On the basis of the obtained structure, the sidewall isolation layer 150, the gate oxide layer 160, and a part of the fin structure 101 located above the gate oxide layer 160 inside the gate spacer trench 170 are etched along the gate spacer trench 170, so as to form an opening region 110 above the fin structure 101. The opening region 110 includes a source opening region and a drain opening region, so as to facilitate the deposition of source and drain materials in the opening region 110 respectively to form source and drain regions 120 as the source or the drain.

[0076] In some embodiments, during the process of etching the sidewall isolation layer 150, the sidewall isolation layer 150 covering the top end of the first dielectric layer 140 is etched and removed simultaneously, so that the upper surface of the first dielectric layer 140 is exposed, thereby reducing the size of the formed structure.

[0077] In some embodiments, the depth of the opening region 110 is 30 nm to 60 nm.

[0078] The depth of the opening region 110 is the same as or 2 - 6 nm more than the height of the fin structure 101 above the channel, thereby effectively improving the mobility of the channel within the control range of the gate region 130.

[0079] The width of the fin structure 101 at the bottom of the opening region 110 is 3 - 16 nm, and the height of the second dielectric layer 150 on both sides of the fin structure 101 at the bottom of the opening region 101 is 0 - 15 nm.

[0080] S106: A nucleation region layer and a high - phosphorus doping region layer are sequentially formed from bottom to top inside the opening region, and the impurity layer formed on the surface of the high - phosphorus doping region layer is removed to form the source or the drain.

[0081] It should be noted that the source or the drain of the NMOS device structure can also be fabricated by different processes to obtain different concentrations or film structures.

[0082] Optionally, the formation process of the opening region can be obtained by using the method in this solution or the preparation method in the prior art. The opening region in this solution can be either a single opening region for fabricating the source or the drain, or two opening regions for fabricating the source and the drain respectively.

[0083] After the opening region of the NMOS structure is covered with a nucleation region layer and a high-phosphorus doped region layer to form a source electrode, the drain electrode of the NMOS structure can be fabricated using existing processes. For example, using more than two photomasks, first pattern the source opening region of the NMOS, and form the source electrode by sequentially forming a nucleation region layer and a high-phosphorus doped region layer from bottom to top inside the opening region; then pattern the drain opening region, and the drain opening region can be fabricated using other processes, or adjust the process steps and process parameters to achieve a drain electrode with a different concentration and film layer structure from the source electrode. After the drain opening region of the NMOS structure is covered with a nucleation region layer and a high-phosphorus doped region layer to form a drain electrode, the source electrode of the NMOS structure can be fabricated using existing processes, and its content is basically the same as the above content, which will not be elaborated here.

[0084] It should be noted that after fabricating the opening region by the above NMOS structure fabrication method, after forming one of the source electrode or the drain electrode of the NMOS structure by sequentially forming a nucleation region layer and a high-phosphorus doped region layer from bottom to top inside the opening region, other fabrication methods of the existing technology can be used to fabricate the other opening region of the NMOS structure, and the drain electrode or the source electrode can be fabricated inside the opening region by existing processes, which will not be elaborated here.

[0085] Optionally, in this solution, the source opening region and the drain opening region of the NMOS structure can also be simultaneously covered with a nucleation region layer and a high-phosphorus doped region layer to form a source electrode and a drain electrode, and then the NMOS structure is obtained, which will not be elaborated here.

[0086] In some embodiments, the formation process of the nucleation region layer is obtained by epitaxial growth. The nucleation region layer is a single-crystalline silicon-based material doped with a small amount of impurity elements, including any one of Si:P, Si:C, Si:As, Si:As(P), Si:C(P). The thickness of the nucleation region layer is 2 to 10 nm. The formation process of the nucleation region layer includes:

[0087] Introduce a first growth gas source and a first doping gas source into the opening region, and adjust the partial pressure ratio of the first doping gas source in the current reaction gas source to a first threshold; wherein, the first growth gas source is used as a silicon source, including any one of DCS, SiH4, Si2H6, TCS, or a mixed gas source composed of multiple of the above gases, and the first doping gas source includes PH3, C2H6, AsH3, or a mixed impurity gas source composed of multiple of the above gases.

[0088] Among them, the partial pressure ratio of the first doping gas source in the reaction gas is the volume ratio of the gas volume of the first doping gas source to the gas volume of all reaction gases during the reaction process of forming the nucleation region layer. The reaction gas includes a carrier gas, a first growth gas source, a first doping gas source, and other gases. In this embodiment, the first threshold is 0.1% - 4%, so that the concentration of the doped impurity material in the nucleation region layer 121 obtained subsequently reaches 1E18 - 5E20 atom cm -3 .

[0089] Control the reaction temperature to be 500 - 800 degrees Celsius, the reaction pressure to be 100 - 600 Torr, select H2 or N2, or a mixed gas source of both as the carrier gas; according to the selected reaction temperature, reaction pressure, and the type of the first growth gas source, control the flow rates of the first growth gas source and the first doping gas source to be 20 - 100 sccm to form the nucleation region layer on the inner wall surface of the opening region.

[0090] Continuously introduce the first growth gas source and the first doping gas source until the thickness of the nucleation region layer reaches 2 cm, and then stop introducing the first growth gas source and the first doping gas source. In this embodiment, it also includes stopping introducing the first growth gas source and the first doping gas source when the area of the nucleation region layer covering the inner wall surface of the opening region reaches more than 70%, and completing the preparation process of the nucleation region layer.

[0091] Refer to Figure 6 , the nucleation region layer 121 is a low-concentration buffer zone of a silicon-based material doped with a small amount of impurity elements, including at least one of Si:C, Si:P, Si:C(P), Si:As(P), and the doping concentration of its doping elements is 1E18 - 5E20 atom cm -3 ; with a thickness of 2 - 10 nm, the nucleation region layer 121 formed by preparation provides a buffer for the subsequent growth of the high-concentration high-phosphorus doped region layer 122, and at the same time reduces or blocks the diffusion of impurities in the high-phosphorus doped region layer 122 to the channel region of the device, playing a protective role.

[0092] In some embodiments, during the process of introducing the growth gas source and the doping gas into the opening region, an etching gas is introduced to improve the reaction selectivity. In this embodiment, the etching gas is HCl.

[0093] In some embodiments, refer to Figure 6 , after the nucleation region layer 121 is prepared, phosphine gas is selected as the second doping gas source, and the second growth gas source and phosphine gas are continuously introduced into the opening region 110. The second growth gas source is a silicon source, including any one of DCS, SiH4, Si2H6, TCS, or a mixed gas source composed of multiple of the above gases.

[0094] In this embodiment, the second threshold is 3% - 12%. Adjust the partial pressure ratio of the phosphine gas in the second growth gas source to be 3% - 12%, so that the concentration of the impurity material doped in the high-phosphorus doped region layer 122 obtained subsequently in the single-crystalline silicon-based material reaches 2E21 - 8E21 atom cm -3 , control the reaction temperature to 550 - 700 degrees Celsius, and the reaction pressure to 200 - 600 Torr. Among them, the partial pressure of the second growth gas source is 30 - 160 Torr, and the partial pressure of the phosphine gas is 15 - 80 Torr.

[0095] As the width of the fin structure 101 becomes smaller and smaller, even reaching 3 nm, that is, the growth single-crystalline substrate provided for epitaxy becomes smaller and smaller. At the same time, the depth of the source / drain region increases with the increase in the height of the fin structure 101, even up to 50 nm, and the opening width of the opening region 110 is 15 - 100 nm. On such a small epitaxial growth substrate, in the opening region 110, the part growing upward from the bottom of the opening region 110 will eventually merge with the silicon-doped material growing out from the side walls on both sides of the opening region 110. And due to the different crystal planes of the epitaxial single-crystalline materials growing from the side walls of the two fin structures 101 on both sides, they cannot be completely fused together, and a slit groove 180 will be formed in the middle. Among them, the width of the slit groove 180 is 0.5 - 2 nm.

[0096] While growing upward epitaxially in the opening region, it will also grow toward both sides parallel to the gate direction, as Figure 7 shown. In order to prevent the epitaxial fusion of adjacent opening regions from causing device failure, the growth width of the source / drain region 120 along the gate length direction is controlled, which in turn will also affect the growth of the source / drain region 120 in the height direction. When the top critical dimension width of the fin structure 101 is less than 10 nm and the height of the fin structure 101 is greater than 40 nm, the high-phosphorus doped region layer 122 of the source / drain region 120 cannot completely fill the source / drain region 120, thus forming a triangular groove at the top of the high-concentration doped region.

[0097] And due to the epitaxial growth characteristics of SiP and SiC, as the doping concentration of the source / drain region 120 continues to increase, the growth rate difference of the materials on different crystal planes during epitaxy becomes larger, showing a growth rate: crystal plane

[100] > crystal plane

[110] > crystal plane

[11] . When the outermost surface of the source / drain region mostly becomes the crystal plane

[111] , the growth rate of the source / drain region drops to the growth threshold, and finally the upper surface of the formed high-phosphorus doped region layer 122 stays on this crystal plane. Therefore, in this embodiment, an included angle α is formed between the upper surface of the high-phosphorus doped region layer 122 and the upper surface of the substrate 100, as Figure 6 shown, where the angle of the included angle α is 40 - 70 degrees.

[0098] It should be noted that the thickness of the highly phosphorus-doped region layer 122 is 20 to 60 nm, and its lattice parameter is 5.3 to 5.43 Å, which is smaller than that of silicon. The highly phosphorus-doped region layer 122 provides tensile stress for the channel region and reduces the resistance of the source / drain regions 120 at the same time.

[0099] In the process of forming the highly phosphorus-doped region layer 122, since the silicon-phosphorus epitaxial reaction adopted is a balanced critical reaction with mutual competition and also a balanced reaction of growing and etching simultaneously, increasing the partial pressure of the phosphorus source during the reaction is helpful for more phosphorus to be doped into silicon-phosphorus. During the epitaxial reaction, the intermediate products will decompose and participate in the formation of single-crystal phosphorus-silicon, but they cannot be evacuated with the carrier gas during the purging and cooling steps at the end of the reaction, and finally an amorphous phosphorus-rich silicon-phosphorus layer is formed on the upper surface of the highly doped region. The thickness of the amorphous silicon-phosphorus layer is related to the partial pressure of phosphine. The higher the partial pressure, the thicker the amorphous silicon layer, and the thickness is 1 to 4 nm.

[0100] Therefore, in this solution, by removing the impurity layer 124 formed on the surface of the highly phosphorus-doped region layer 122, the source / drain regions 120 that fill the inside of the opening region 110 are formed, thereby avoiding the influence of the impurity layer 124 on the performance of the finally formed semiconductor device and improving the product yield.

[0101] In this embodiment, any one of in-situ etching, dry etching, and wet cleaning is used to remove the impurity layer located on the surface of the highly phosphorus-doped region layer.

[0102] In some embodiments, removing the impurity layer formed on the surface of the highly phosphorus-doped region layer includes:

[0103] Continuously introducing an etching gas and a carrier gas to the surface of the highly phosphorus-doped region layer inside the opening region, and performing in-situ etching on the surface of the highly phosphorus-doped region layer until the impurity layer on the surface of the highly phosphorus-doped region layer is completely removed.

[0104] In some embodiments, referring to Figure 8 , after the epitaxial reaction for forming the highly phosphorus-doped region layer 122 ends, the impurity layer 124 of amorphous phosphorus-rich silicon-phosphorus on the surface of the highly phosphorus-doped region layer 122 is etched off by using an in-situ etching method. The reaction temperature of the in-situ etching is 550 to 750 degrees Celsius, the reaction pressure is 5 to 50 Torr, the partial pressure of the etching gas is 0.05 to 0.2 Torr, the carrier gas is H2 or N2, and the reaction partial pressure of the etching gas HCl is 0.05 to 0.2 Torr. Since the thickness of the amorphous silicon-phosphorus layer is relatively thin, by reducing the flow rate and partial pressure of the etching gas HCl, the situation of over-etching is effectively avoided.

[0105] In some other embodiments, a dry etching process is used to remove the impurity layer 124 on the surface of the highly phosphorus-doped region layer 122. During the dry etching process, since the etching rates of halogen gases containing bromine or chlorine on single-crystalline silicon and amorphous silicon are different, by controlling the proportion of dry etching gases or using a cycle method of etching / evacuating / etching, such as atomic layer etching method, the etching amount can be more precisely controlled to etch away the amorphous silicon phosphorus on the upper surface of the single-crystalline silicon phosphorus, so as to remain on the single-crystalline silicon phosphorus.

[0106] In some other embodiments, a wet cleaning method can also be used to clean the impurity layer 124 of amorphous phosphorus-rich silicon phosphorus on the surface of the highly phosphorus-doped region layer 122, so as to obtain the highly phosphorus-doped region layer 12 with a high phosphorus doping concentration. In the wet cleaning process, a mixed solution of low-concentration ammonia water / hydrogen peroxide / water is selected as the wet cleaning solution, and the ratio of ammonia water to hydrogen peroxide is 1:1 to 1:3, and the ratio of the ammonia water-hydrogen peroxide mixture to water is 1:500 to 1:1000. By controlling the cleaning time, the impurity layer 124 of amorphous phosphorus-rich silicon phosphorus on the surface of the highly phosphorus-doped region layer 122 is removed.

[0107] In some embodiments, after removing the impurity layer 124 formed on the surface of the highly phosphorus-doped region layer 122, the method further includes performing high-temperature annealing on the surface of the highly phosphorus-doped region layer 122, referring to Figure 9 , on the one hand, repairing the crystal plane damage caused by the above in-situ etching, dry etching and wet cleaning, and on the other hand, repairing the slit grooves 180 on the surface of the highly phosphorus-doped region layer 122.

[0108] In this embodiment, the reaction temperature of the high-temperature annealing is 650 to 750 degrees Celsius, the reaction pressure is 5 to 50 Torr, and the annealing time is 5 to 30 s.

[0109] In some embodiments, the method further includes forming a covering layer on the surface of the highly phosphorus-doped region layer after removing the impurity layer. The formation process of the covering layer includes:

[0110] Referring to Figure 10 , gas purging is performed on the surface of the highly phosphorus-doped region layer, and a third growth gas source and a third doping gas source are continuously introduced into the surface of the highly phosphorus-doped region layer. The third growth gas source is used as a silicon source and includes any one of DCS, SiH4, Si2H6, TCS, or a mixed gas source composed of multiple of the above gases. The third growth gas source is composed of a mixture of DCS and SiH4, and the proportion of SiH4 in the third growth gas source is 5% to 30%. Since the molecular size of SiH4 is smaller, it is more conducive to penetrating into the slit grooves 180 for nuclear growth. At the same time, to improve the reaction selectivity of the epitaxial reaction on silicon / silicon oxide or silicon nitride, while adding the etching gas HCl, the chlorine-containing component DCS is still used as the third growth gas source to provide the silicon source.

[0111] Adjust the partial pressure ratio of the third doping gas source in the current reaction gas source to a third threshold value, so that the concentration of the doping element in the covering region layer 123 obtained subsequently reaches 1E18 - 5E20 atom / cm³ in the covering region layer 123. -3 The third threshold value is 0.2% - 0.6%. In this embodiment, the third threshold value is 0.4%.

[0112] Under the above reaction conditions, the covering region layer 123 is grown in a bottom-up growth mode, so that the covering region layer 123 starts to grow from the bottommost part of the high-phosphorus doped region layer 122, that is, from the surface of the high-phosphorus doped region layer 122, so as to grow a funnel-shaped covering region layer inside the slit groove and on the surface of the high-phosphorus doped region layer.

[0113] In this embodiment, the reaction pressure is 10 - 150 Torr. Since under low pressure conditions, the intermolecular collisions are reduced, the average free path of the molecules increases, and the reaction molecules are more likely to enter the bottom of the source-drain region for growth, so that the covering region layer 123 is more likely to grow along the surface of the high-phosphorus doped region layer 122. At the same time, increase the concentration of SiH4 in the third growth gas source to reduce the growth rate difference of the doping material on different crystal planes, so as to ensure that the covering region layer 123 can grow from bottom to top and form a funnel-shaped covering region layer 123. Since the phosphorus doping concentration of the covering region layer 123 is low, in order to reduce the influence of the phosphorus concentration reduction on the stress and resistance, control the growth thickness of the covering region layer 123 to be 2 - 20 nm.

[0114] Continuously introduce the third growth gas source and the third doping gas source until the grown covering region layer completely covers the surface of the high-phosphorus doped region layer.

[0115] After obtaining the high-phosphorus doped region layer 122, continue to form the covering region layer 123 on the surface of the high-phosphorus doped region layer 122 to obtain the final complete source-drain region 120.

[0116] After successively preparing the nucleation region layer 121, the high-phosphorus doped region layer 122 and the covering region layer 123, fill the opening region 110 through the nucleation region layer 121, the high-phosphorus doped region layer 122 and the covering region layer 123 to form the source-drain region 120, so that the source-drain regions 120 located on both sides of the gate region 130 are respectively used as the source electrode and the drain electrode to form an NMOS structure.

[0117] During the process of the above preparation method, a nucleation region layer and a highly phosphorus-doped region layer are formed inside the opening region to form source and drain regions filled inside the opening region, and an impurity layer formed on the surface of the highly phosphorus-doped region layer is removed, thereby providing higher stress for the NMOS channel, reducing the bulk resistance and contact resistance of the NMOS source and drain regions, and moreover, by removing the impurity layer on the surface of the highly phosphorus-doped region layer, the influence of the impurity layer on the performance of the semiconductor device formed subsequently is avoided, effectively improving the yield of the product wafer.

[0118] The present invention also provides an NMOS structure, including:

[0119] A substrate 100;

[0120] A fin structure 101, disposed above the substrate 100;

[0121] A gate 130, disposed above the fin structure 101;

[0122] A source 111, disposed in the top region of the fin structure 101 and on one side of the gate 130;

[0123] A drain 112, disposed in the top region of the fin structure 101 and on the other side of the gate 130;

[0124] Wherein, the source 111 and / or the drain 112 include a nucleation region layer 121 and a highly phosphorus-doped region layer 122 which are sequentially disposed from bottom to top.

[0125] In some embodiments, a covering region layer 123 is further disposed on the surface of the highly phosphorus-doped region layer 122.

[0126] In some other embodiments, the included angle between the hypotenuse where the upper surface of the highly phosphorus-doped region layer 122 is located and the horizontal plane is 40° to 70°.

[0127] Since the above NMOS structure is obtained according to the preparation method of the foregoing NMOS structure, it will not be elaborated here.

[0128] The present invention also discloses a semiconductor device, including the above NMOS structure.

[0129] The semiconductor device adopting the above NMOS structure provides higher stress for the NMOS channel, reduces the bulk resistance and contact resistance of the NMOS source and drain regions, and improves the performance of the semiconductor device.

[0130] Although the embodiments of the present invention have been described in detail above, it will be apparent to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations are all within the scope and spirit of the present invention as described in the claims. Moreover, the present invention described herein can have other embodiments and can be implemented or realized in various ways.

Claims

1. A method for preparing an NMOS structure, characterized in that, Including: Providing a substrate; Forming a plurality of fin structures on the substrate; Forming a gate oxide layer on the surface of the fin structures, depositing an isolation layer between the fin structures, and forming a gate material layer above the isolation layer and the gate oxide layer of the fin structures; Patterning the gate material layer to form a plurality of gate lines, forming a gate spacer trench between adjacent gate lines, and forming a sidewall isolation layer on the surface of the obtained structure; Etching the sidewall isolation layer on the upper surface of the gate oxide layer, the gate oxide layer, and a part of the fin structures along the gate spacer trench to form an opening region; Sequentially forming a nucleation region layer and a highly phosphorus-doped region layer from bottom to top inside the opening region, and removing an impurity layer formed on the surface of the highly phosphorus-doped region layer to form a source or a drain, wherein the formation process of the highly phosphorus-doped region layer includes: Introducing a second growth gas source and a second doping gas source into the opening region where the nucleation region layer is formed, and adjusting the partial pressure ratio of the second doping gas source in the current reaction gas source to a second threshold value to form a highly phosphorus-doped region layer on the surface of the nucleation region layer; Continuously introducing the second growth gas source and the second doping gas source until the growth rate on the upper surface of the highly phosphorus-doped region layer decreases to a growth threshold value; Among them, the second doping gas source is phosphine gas, and the concentration of the doping element in the second doping gas source in the high phosphorus doping region layer is 2E21 - 8E21 atom cm -3 .

2. The manufacturing method of the NMOS structure according to claim 1, characterized in that, The removing the impurity layer formed on the surface of the highly phosphorus-doped region layer includes: Introducing an etching gas and a carrier gas onto the surface of the highly phosphorus-doped region layer inside the opening region, and in-situ etching the surface of the highly phosphorus-doped region layer until the impurity layer on the surface of the highly phosphorus-doped region layer is completely removed.

3. The manufacturing method of the NMOS structure according to claim 1, wherein, Removing the impurity layer on the surface of the highly phosphorus-doped region layer by using a dry etching or wet cleaning process.

4. The manufacturing method of the NMOS structure according to any one of claims 1 to 3, characterized in that, The formation process of the nucleation region layer includes: Introducing a first growth gas source and a first doping gas source into the opening region, adjusting the partial pressure ratio of the first doping gas source in the current reaction gas source to a first threshold value, and controlling the reaction temperature and reaction pressure to form the nucleation region layer on the inner wall of the opening region; Continuously introducing the first growth gas source and the first doping gas source until the thickness of the nucleation region layer reaches 2 cm.

5. The manufacturing method of the NMOS structure according to claim 4, characterized in that, The formation process of the highly phosphorus-doped region layer includes: Introducing a second growth gas source and a second doping gas source into the opening region where the nucleation region layer is formed, adjusting the partial pressure ratio of the second doping gas source in the current reaction gas source to a second threshold value, and the second threshold value is greater than the first threshold value, to form a highly phosphorus-doped region layer on the surface of the nucleation region layer, and forming a vertical slit trench at the middle position of the highly phosphorus-doped region layer.

6. The manufacturing method of the NMOS structure according to claim 1, wherein, The reaction temperature during the preparation process of the highly phosphorus-doped region layer is 550 to 700 degrees Celsius, the reaction pressure is 200 to 600 Torr, the partial pressure of the second growth gas source is 30 to 160 Torr, and the partial pressure of the phosphine gas is 15 to 80 Torr.

7. The manufacturing method of the NMOS structure according to claim 5, characterized in that, After removing the impurity layer formed on the surface of the highly phosphorus-doped region layer, the method further includes performing high-temperature annealing on the surface of the highly phosphorus-doped region layer to repair the slit trench on the highly phosphorus-doped region layer, and the reaction temperature of the high-temperature annealing is 650 to 750 degrees Celsius.

8. The manufacturing method of the NMOS structure according to claim 5, characterized in that, The method further includes forming a covering region layer on the surface of the high-phosphorus doped region layer after removing the impurity layer, and the formation process of the covering region layer includes: Performing gas purging on the surface of the high-phosphorus doped region layer, continuously introducing a third growth gas source and a third doping gas source to the surface of the high-phosphorus doped region layer, and adjusting the partial pressure ratio of the third doping gas source in the current reaction gas source to a third threshold value; Reducing the reaction pressure to grow a funnel-shaped covering region layer inside the slit groove and on the surface of the high-phosphorus doped region layer; Continuously introducing the third growth gas source and the third doping gas source until the grown covering region layer completely covers the surface of the high-phosphorus doped region layer.

9. An NMOS structure obtained by manufacturing using the manufacturing method of the NMOS structure according to any one of claims 1 to 8, characterized in that, Comprising: A substrate; A fin structure disposed above the substrate; A gate disposed above the fin structure; A source electrode disposed in the top region of the fin structure and on one side of the gate; A drain electrode disposed in the top region of the fin structure and on the other side of the gate Wherein, the source electrode and / or the drain electrode includes a nucleation region layer and a high-phosphorus doped region layer sequentially arranged from bottom to top.

10. A semiconductor device, characterized in that, Comprising the NMOS structure described in claim 9.

Images