NMOS Structure, Manufacturing Method and Semiconductor Device

Abstract

The present invention provides an NMOS structure, a manufacturing method and a semiconductor device. The manufacturing method includes: providing a substrate; forming a plurality of fin structures on the substrate; forming a gate oxide layer on the surface of the fin structures, depositing an isolation layer between the fin structures, and forming a gate material layer above the isolation layer and the gate oxide layer of the fin structures; patterning the gate material layer to form a plurality of gate lines, forming a gate spacer trench between adjacent gate lines, and forming a sidewall isolation layer on the surface of the obtained structure; forming an opening region; sequentially forming a nucleation region layer, a highly doped region layer and a covering region layer from bottom to top inside the opening region to form a source or a drain. The NMOS structure obtained by the manufacturing method of the present invention improves the stress of the source-drain region and reduces the resistance, and effectively reduces the problems of slits and uneven growth in the source-drain region.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit manufacturing technologies, and in particular, to an NMOS structure, a manufacturing method, and a semiconductor device. Background Art

[0002] As microelectronics technology develops towards higher performance, many new technologies have been introduced into the complementary metal oxide semiconductor (CMOS) integrated process technology. Among them, the strained silicon technology was introduced at the 90nm node, and the strained silicon technology has become a technology that can effectively improve the performance of transistors in the field of integrated circuits. As is well known, introducing tensile strain into the channel of an N-type metal-oxide-semiconductor (NMOS) and compressive strain into the channel of a P-type metal-oxide-semiconductor (PMOS) can increase the carrier mobility in the channel, thereby improving the performance of the transistor. A common way to introduce strain is to grow SiGe in the source and drain regions of PMOS devices and grow SiC (or SiP) in the source and drain regions of NMOS devices, thereby introducing strain into their respective channel regions.

[0003] As the technology node develops downward and enters the 3D fin field-effect transistor (FinFET) device, in order to improve the performance of the FinFET device, the height of the fin is getting higher and higher. In order to improve the control force of the gate on the channel, that is, it is required that the depth of the source and drain regions is getting deeper and deeper; at the same time, the width of the fin is getting narrower and narrower. It becomes more and more difficult to grow SiGe or Si:C(P) by epitaxial process to fill the source and drain regions on such a narrow fin substrate. Once the source and drain regions are not fully grown, on the one hand, the unfilled source and drain regions will further lose in the subsequent wet processing, resulting in vacancies in the source and drain regions and a decrease in transistor performance; on the other hand, when the growth height of the source and drain regions is very small, in the subsequent silicide contact process, it may be impossible to contact the source and drain or directly punch through the source and drain, resulting in an open circuit or short circuit of the transistor device.

[0004] Therefore, it is necessary to provide a novel NMOS structure, a manufacturing method, and a semiconductor device to solve the above problems existing in the prior art. Summary of the Invention

[0005] The purpose of the present invention is to provide an NMOS structure, a manufacturing method, and a semiconductor device, which can improve the stress of the source and drain regions, reduce the resistance, and effectively reduce the problems of slits and uneven growth in the source and drain regions.

[0006] To achieve the above object, the manufacturing method of the NMOS structure of the present invention includes:

[0007] Providing a substrate;

[0008] Forming a plurality of fin structures on the substrate;

[0009] Forming a gate oxide layer on the surface of the fin structure, depositing an isolation layer between the fin structures, and forming a gate material layer above the isolation layer and the gate oxide layer of the fin structure;

[0010] Pattern etching the gate material layer to form a plurality of gate lines, forming a gate spacer groove between adjacent gate lines, and forming a sidewall isolation layer on the surface of the obtained structure;

[0011] Etching the sidewall isolation layer on the upper surface of the gate oxide layer, the gate oxide layer and a part of the fin structure along the gate spacer groove to form an opening area;

[0012] Forming a nucleation region layer, a highly doped region layer and a covering region layer in sequence from bottom to top inside the opening area to form a source or a drain.

[0013] The beneficial effect of the manufacturing method of the NMOS structure of the present invention is that: by using the nucleation region layer, the highly doped region layer and the covering region layer to jointly form the source and / or drain of the NMOS structure, while achieving at least one of high stress and low resistance of the NMOS source and drain, effectively improving the growth height of the source and drain doping materials, effectively reducing the phenomenon of too little material growth in the source and drain, thereby reducing the process risks of source or drain missing, unable to contact the source and drain, and punching through the source and drain regions in the subsequent silicide connection process.

[0014] Optionally, the formation process of the nucleation region layer includes:

[0015] Introducing a first growth gas source and a first doping gas source into the opening area, adjusting the partial pressure ratio of the first doping gas source in the current reaction gas source to a first threshold value, and controlling the reaction temperature and reaction pressure to form the nucleation region layer on the inner wall of the opening area;

[0016] Continuously introducing the first growth gas source and the first doping gas source until the thickness of the nucleation region layer reaches 2 cm, and then stopping introducing the growth gas source and the doping gas source. Its beneficial effect is that: ensuring that the formed nucleation region layer can fully cover the inner wall of the opening area, avoiding too little material growth in the subsequent formed source and drain regions.

[0017] Optionally, in the formation process of the nucleation region layer, the reaction temperature is 600 - 700 degrees Celsius, and the reaction pressure is 100 - 600 Torr.

[0018] Optionally, the formation process of the highly doped region layer includes:

[0019] Introduce a second growth gas source and a second doping gas source into the opening region where the nucleation region layer is formed, and control the partial pressure ratio of the second doping gas source in the current reaction gas source to be from the first threshold to a second threshold, where the second threshold is greater than the first threshold;

[0020] Control the reaction temperature and reaction pressure to form a highly doped region layer on the surface of the nucleation region layer, and form a vertical slit groove at the middle position of the highly doped region layer;

[0021] Continuously introduce the second growth gas source and the second doping gas source until the growth rate of the upper surface of the highly doped region layer decreases to the growth threshold, and then stop introducing the second growth gas source and the second doping gas source.

[0022] Optionally, the reaction temperature during the preparation process of the highly doped region layer is 550 - 650 degrees Celsius, the reaction pressure is 300 - 600 Torr, and the concentration of the doping element in the second doping gas source in the second growth gas source is 5E19 - 6E21 atom cm -3 .

[0023] Optionally, the formation process of the covering region layer includes:

[0024] Perform gas purging on the surface of the highly doped region layer, continuously introduce a third growth gas source and a third doping gas source to the surface of the highly doped region layer, and adjust the partial pressure ratio of the third doping gas source in the reaction gas source to a third threshold;

[0025] Reduce the reaction pressure to grow a funnel-shaped covering region layer inside the slit groove and on the surface of the highly doped region layer;

[0026] Continuously introduce the third growth gas source and the third doping gas source until the grown covering region layer completely covers the surface of the highly doped region layer.

[0027] Optionally, before successively forming a nucleation region layer, a highly doped region layer, and a covering region layer from bottom to top inside the opening region, the method further includes preprocessing the opening region, and the preprocessing process includes:

[0028] Process the inner surface of the opening region to remove carbon-containing and oxygen-containing materials on the surface of the opening region;

[0029] Perform lattice repair processing on the surface of the opening region.

[0030] The present invention provides an NMOS structure, including:

[0031] A substrate;

[0032] A fin structure is disposed above the substrate;

[0033] A gate is disposed above the fin structure;

[0034] A source is disposed at the top region of the fin structure and on one side of the gate;

[0035] A drain is disposed at the top region of the fin structure and on the other side of the gate;

[0036] Wherein, the source and / or the drain each include a nucleation region layer, a high-doping region layer, and a covering region layer which are sequentially arranged from bottom to top, and a slit groove is disposed inside the high-doping region layer.

[0037] Optionally, a slit groove is disposed at the center of the high-doping region layer, the covering region layer fills inside the slit groove and covers the upper surface of the high-doping region layer, and the covering region layer is in a funnel shape.

[0038] Optionally, the height of the fin structure is 800 to 1600 nm, and the height of the gate region is 30 to 80 nm.

[0039] The present invention also discloses a semiconductor device, including the above NMOS structure.

[0040] The beneficial effects of the NMOS structure of the present invention are as follows: By adopting the nucleation region layer, the high-doping region layer, and the covering region layer to jointly form at least one of the source and the drain of the NMOS structure, while achieving at least one of high stress and low resistance of the NMOS source and drain, the growth height of at least one doping material of the source and the drain is effectively increased, and the phenomena that too little material grows in at least one of the source and the drain and the source-drain region is lost in subsequent processing are reduced, thereby reducing the process risks of source-drain region missing, unable to contact the source-drain, and punching through the source-drain region that may occur in the subsequent silicide connection process. Description of the Drawings

[0041] Figure 1 It is a flowchart of the manufacturing method of the NMOS structure according to the embodiment of the present invention;

[0042] Figure 2 It is a schematic structural diagram of the manufacturing method of the NMOS structure according to the embodiment of the present invention after forming the isolation layer;

[0043] Figure 3 It is a schematic structural diagram of the structure obtained after completing step S103 in the manufacturing method of the NMOS structure according to the embodiment of the present invention;

[0044] Figure 4Schematic cross-sectional structure diagram of the fin structure along the vertical direction of the structure obtained after completing step S104 in the manufacturing method of the NMOS structure according to the embodiment of the present invention;

[0045] Figure 5 Schematic cross-sectional structure diagram of the fin structure along the vertical direction of the structure obtained after completing step S105 in the manufacturing method of the NMOS structure according to the embodiment of the present invention;

[0046] Figure 6 Schematic cross-sectional structure diagram of the fin structure along the vertical direction of the structure obtained after completing step S106 in the manufacturing method of the NMOS structure according to the embodiment of the present invention;

[0047] Figure 7 Schematic cross-sectional structure diagram of the source opening region or the drain opening region along the vertical direction of the structure obtained by the manufacturing method of the NMOS structure according to the embodiment of the present invention;

[0048] Figure 8 Of the manufacturing method of the NMOS structure according to the embodiment of the present invention Figure 2 Magnified structure diagram of A therein. Detailed implementation manners

[0049] To make the objectives, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings of the present invention. Obviously, the described embodiments are some but not all of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein shall have the ordinary meanings understood by those of ordinary skill in the art in the field to which the present invention belongs. The terms such as "including" used herein mean that the elements or items appearing before this word cover the elements or items listed after this word and their equivalents, without excluding other elements or items.

[0050] In view of the problems existing in the prior art, embodiments of the present invention provide a manufacturing method of an NMOS structure, as Figure 1 shown, including the following steps:

[0051] S101. Provide a substrate.

[0052] Wherein, the substrate may be a silicon substrate or a silicon substrate doped with a part of germanium element. In this embodiment, the silicon substrate is used as the substrate.

[0053] S102. Form a plurality of fin structures on the substrate.

[0054] Specifically, the substrate is etched to form a plurality of fin structures on the substrate. By etching the substrate, a plurality of uniformly arranged fin structures are formed on the surface of the substrate. The etching method includes multiple photolithography and multi-step etching. The multiple photolithography includes Self-aligned Double Patterning (SADP), Self-Aligned Quadruple Patterning (SAQP), and Litho-Etch-Litho-Etch (LELE).

[0055] In some embodiments, as Figure 8 shown, the protrusion height H of the fin structure is 800 nm to 1600 nm, and the critical dimension L at the top of the fin structure is 5 nm to 20 nm.

[0056] S103. A gate oxide layer is formed on the surface of the fin structure, and an isolation layer is deposited between the fin structures. A gate material layer is formed above the isolation layer and the gate oxide layer of the fin structure.

[0057] In some embodiments, the depositing an isolation layer between the fin structures and forming a gate material layer above the isolation layer and the gate oxide layer of the fin structure includes:

[0058] An isolation layer covering the gate oxide layer is formed between adjacent fin structures.

[0059] A gate material layer and a first dielectric layer are sequentially covered on the surface of the isolation layer, wherein the gate material layer covers the surface of the fin structure and the surface of the isolation layer.

[0060] Specifically, after a layer of gate oxide layer is formed on the surface of the fin structure, an isolation layer is deposited between adjacent fin structures. The isolation layer covers the gate oxide layer on the upper surface of the substrate layer, and a gate material layer and a first dielectric layer are sequentially covered on the surface of the isolation layer, wherein the gate material layer covers the surface of the fin structure and the upper surface of the isolation layer.

[0061] In this embodiment, referring to Figure 2 , after a plurality of protruding fin structures 101 are formed on the surface of the substrate 100, a layer of gate oxide layer 160 is formed on the upper surface of the substrate 100 and the surface of the fin structures 101.

[0062] Specifically, after depositing a layer of gate oxide material on the surface of the fin structure 101 and the surface of the substrate 100, a gate oxide layer 160 that completely covers the upper surface of the substrate 100 and the surface of the fin structure 101 is formed. Among them, the gate oxide material used in the gate oxide layer 160 includes any one or a combination of SiO2, SiON, SiHfO, HfO2, or ZrO2.

[0063] After forming the gate oxide layer 160, referring to Figure 2 , a layer of silicon oxide is filled between adjacent fin structures 101, so as to form an isolation layer 102 on the surface of the gate oxide layer 160 on the upper surface of the substrate 100, so as to isolate adjacent fin structures 101 from each other.

[0064] It should be noted that in this solution, the isolation layer 102 is mainly used to isolate the fin structures 101. This solution is not limited to silicon oxide materials, and other materials can also be used, which will not be elaborated here.

[0065] Figure 3 FIG. is a schematic diagram of the structure obtained after the manufacturing method of the NMOS structure of the present invention completes step S103. Referring to Figure 3 , after forming the isolation layer 102, a gate material layer 130 is formed on the surface of the isolation layer 102 by deposition, and a first dielectric layer 140 is formed on the surface of the gate material layer 103, so that the gate material layer 130 completely covers the surface of the fin structure 101 and the upper surface of the isolation layer 102. The obtained structure is as shown in Figure 3 . Specifically, the gate material layer 130 is a doped polysilicon material or a metal gate material. The metal gate material includes any one of TiN, TiAl, TiSiN, and TiAlC. The height of the gate material layer 130 above the fin structure 101 is 30-80 nm.

[0066] The first dielectric layer 140 uses a hard mask material, including silicon oxide or silicon nitride material, or a stack of the two materials, and a stack of these compounds.

[0067] S104. Pattern the gate material layer to form a plurality of gate lines, and a gate interval groove is formed between adjacent gate lines, and a sidewall isolation layer is formed on the surface of the obtained structure.

[0068] In some embodiments, the first dielectric layer is a multi-layer stack. First, the first dielectric layer is patterned, and then the patterned first dielectric layer is used as a mask to pattern and etch the gate material layer until the gate oxide layer is exposed to form a plurality of gate lines, and a gate interval groove is formed between adjacent gate lines.

[0069] A sidewall isolation layer is formed above the obtained structure, including:

[0070] A sidewall isolation layer is formed on the surface of the gate line and the inner wall of the gate spacer trench, so that the sidewall isolation layer covers the side of the gate line, the top of the first dielectric layer, the sidewall of the gate spacer trench, and the gate oxide layer on the top surface of the fin structure.

[0071] Reference Figure 4 , for Figure 3 The first dielectric layer 140 and the gate material layer 130 in the obtained structure are subjected to multiple photolithography and etching processes until the gate oxide layer 160 is exposed, thereby forming a plurality of gate lines (not labeled in the figure). The length direction of the gate lines is perpendicular to the length direction of the fin structure. Part of the gate lines is located above the fin structure, and part is located above the isolation layer 102. A gate spacer trench 170 is formed between adjacent gate lines. Then, a sidewall isolation layer 150 is formed to cover the sidewall of the gate spacer trench 170, the upper surface of the gate oxide layer 160 inside the gate spacer trench 170, and the top of the first dielectric layer 140.

[0072] In this embodiment, the sidewall isolation layer 150 includes any one of SiCON, SiN, and SiO2.

[0073] In some other embodiments, after etching to obtain a plurality of gate spacer trenches 170, the distance between adjacent gate regions 130 is 10 - 120 nm.

[0074] S105, Anisotropically etch the sidewall isolation layer on the upper surface of the gate oxide layer, the gate oxide layer, and part of the fin structure along the gate spacer trench to form an opening region.

[0075] Reference Figure 5 , in Figure 4 Based on the obtained structure, etch the sidewall isolation layer 150 above the gate oxide layer 160 inside the gate spacer trench 170, the gate oxide layer 160, and part of the fin structure 101 along the gate spacer trench 170, so as to form an opening region 110 above the fin structure 101. The opening region 110 includes a source opening region and a drain opening region, so as to facilitate depositing source-drain materials in the opening region 110 respectively to form a source electrode and a drain electrode.

[0076] In some embodiments, during the process of etching the sidewall isolation layer 150, the sidewall isolation layer 150 covering the top of the first dielectric layer 140 is etched and removed simultaneously, so that the upper surface of the first dielectric layer 140 is exposed, thereby reducing the size of the formed structure.

[0077] In some embodiments, the depth of the source opening region and the drain opening region is 30 nm to 60 nm.

[0078] The depths of the source opening region and the drain opening region are the same as or 2 - 6 nm more than the height of the fin structure 101 above the isolation layer 120, thereby effectively improving the control of the gate region 130 over the fin structure channel and the channel mobility.

[0079] The width of the fin structure 101 corresponding to the bottom positions of the source opening region and the drain opening region is 3 - 16 nm, and the height of the sidewall isolation layer 150 on both sides of the fin structure 101 at the bottoms of the source opening region and the drain opening region is 0 - 15 nm.

[0080] S106. Form a nucleation region layer, a high - doping region layer, and a covering region layer in sequence from bottom to top in the opening region to form a source electrode or a drain electrode.

[0081] It should be noted that the source electrode or the drain electrode of the NMOS device structure can also be fabricated by different processes to obtain different concentrations or film layer structures.

[0082] Optionally, the formation process of the opening region can be obtained by using the method in this solution or the manufacturing method in the prior art. The opening region in this solution can be either a single opening region for fabricating a source electrode or a drain electrode, or two opening regions respectively for fabricating a source electrode and a drain electrode.

[0083] After the opening region of the NMOS structure is covered with a nucleation region layer, a high - doping region layer, and a covering region layer to form a source electrode, the drain electrode of the NMOS structure can be fabricated by the existing process. For example, using more than two photomasks, first pattern - form the source opening region of the NMOS, and fabricate the source electrode by forming a nucleation region layer, a high - doping region layer, and a covering region layer in sequence from bottom to top inside the opening region; then pattern - form the drain opening region, and the drain opening region can be fabricated by other processes, or adjust the process steps and process parameters to achieve a drain electrode with different concentrations and film layer structures from the source electrode. After the drain opening region of the NMOS structure is covered with a nucleation region layer, a high - doping region layer, and a covering region layer to form a drain electrode, the source electrode of the NMOS structure can be fabricated by the existing process, and its content is basically the same as the above content and will not be elaborated here.

[0084] It should be noted that after fabricating the opening region by the manufacturing method of the above - mentioned NMOS structure in this solution, after forming one of the source electrode or the drain electrode of the NMOS structure by forming a nucleation region layer, a high - doping region layer, and a covering region layer in sequence from bottom to top inside the opening region, other processes of the prior art can be used to fabricate the other opening region of the NMOS structure, and the drain electrode or the source electrode can be fabricated inside the opening region by the existing process, which will not be elaborated here.

[0085] Optionally, in this solution, the source opening region and the drain opening region of the NMOS structure can also be simultaneously covered with a nucleation region layer, a highly doped region layer, and a covering region layer to form a source electrode and a drain electrode, and then the NMOS structure is obtained. Details are not described herein again.

[0086] In some embodiments, a nucleation region layer, a highly doped region layer, and a covering region layer are sequentially formed from bottom to top inside the opening region. The method further includes preprocessing the opening region, and the preprocessing process includes:

[0087] Processing the inner surface of the opening region to remove carbon-containing and oxygen-containing materials on the surface of the opening region;

[0088] Performing a lattice repair treatment on the surface of the opening region.

[0089] Through the above processing process, it is convenient to improve the film quality and preparation efficiency of the subsequent nucleation region layer, highly doped region layer, and covering region layer, reduce lattice defects, and control the growth rate of each surface of the opening region.

[0090] In this embodiment, during the process of processing the inner surface of the opening region, baking treatment or surface reaction treatment is used to remove carbon and oxygen materials on the surface of the opening region.

[0091] Specifically, when baking treatment is used, low-pressure and high-temperature baking is adopted, and the reaction gas used is hydrogen.

[0092] When surface reaction treatment is used, sub-high-temperature reaction is adopted, and the reaction gas is a mixed gas of hydrogen and HCl gas, or a mixed gas of hydrogen / HCl / DCS.

[0093] After processing the inner surface of the opening region to remove carbon and oxygen materials on its surface, lattice repair is performed on the surface of the source-drain region to facilitate the subsequent formation of a nucleation region layer, a highly doped region layer, and a covering region layer in sequence.

[0094] It should be noted that the partial pressure ratio of the gas is the volume ratio of the current gas volume to the total volume of all mixed gases in the current mixed gas.

[0095] In some embodiments, the formation process of the nucleation region layer includes:

[0096] Introducing a first growth gas source and a first doping gas source into the opening region, and adjusting the partial pressure ratio of the first doping gas source in all reaction gases to a first threshold. Wherein, the partial pressure ratio of the first doping gas source in the reaction gases is the volume ratio of the gas volume of the first doping gas source to the gas volume of all reaction gases. The reaction gases include a carrier gas, a growth gas source, a first doping gas source, and other gases. Control the reaction temperature and reaction pressure to form the nucleation region layer on the inner wall of the opening region;

[0097] Continuously introduce the first growth gas source and the first doping gas source until the thickness of the nucleation region layer on each inner wall surface reaches more than 2 nm, and then stop introducing the first growth gas source and the first doping gas source. In this embodiment, it also includes stopping introducing the first growth gas source and the first doping gas source when the area of the inner wall surface of the opening region covered by the nucleation region layer reaches more than 70%, thus completing the preparation process of the nucleation region layer.

[0098] In some embodiments, during the process of introducing the first growth gas source and the first doping gas source into the opening region, an etching gas is introduced to improve the reaction selectivity. In this embodiment, the etching gas is HCl.

[0099] In this embodiment, referring to Figure 6 , the nucleation region layer is a single crystal silicon-based material doped with a small amount of impurity elements, including any one of Si:P, Si:C, Si:As, Si:As(P), Si:C(P). The thickness of the nucleation region layer is 2 to 10 nm, and the first threshold is 0.1% - 4%, so that the doping elements in the subsequently obtained nucleation region layer 121 reach a concentration of 1E18 - 5E20 atom cm in the nucleation region layer -3 .

[0100] In some embodiments, the nucleation region layer is grown by an epitaxial process. The reaction temperature is 600 - 700 degrees Celsius, the reaction pressure is 100 - 600 Torr, the carrier gas source can be H2 or N2, or a mixed gas source of both; the first growth gas source serves as a silicon source, including any one of DCS, SiH4, Si2H6, TCS, or a mixed gas source composed of multiple of the above gases; the first doping gas source includes PH3, C2H6, AsH3, or any one of a mixed impurity gas source composed of multiple of the above gases; control the flow rate of the first growth gas source to be 100 - 500 sccm, and the flow rate of the first doping gas source to be 20 - 100 sccm.

[0101] The nucleation region layer 121 formed by preparation can provide a buffer for the subsequent growth of the high-concentration highly doped region layer 122, and at the same time reduce or block the diffusion of impurities in the highly doped region layer 122 to the channel region of the device, playing a protective role.

[0102] In some embodiments, referring to Figure 6 , after the nucleation region layer 121 is prepared, continue to introduce the second growth gas source and the second doping gas source into the opening region 110. The first growth gas source serves as a silicon source, including any one of DCS, SiH4, Si2H6, TCS, or a mixed gas source composed of multiple of the above gases.

[0103] Adjust the partial pressure ratio of the second doping gas source in all the reaction gases to 1% - 12%, so that the concentration of the doped impurity material in the high-doped region layer 122 obtained subsequently in the single-crystalline silicon-based material reaches 5E19 - 6E21 atom cm -3 , control the reaction temperature to 550 - 650 degrees Celsius and the reaction pressure to 300 - 600 Torr. Compared with the process of forming the nucleation region layer 121, by reducing the reaction temperature, increasing the reaction pressure, and increasing the volume ratio of the second doping gas source in the reaction gases, the doping element concentration in the prepared high-doped region layer is increased.

[0104] As the width of the fin structure 101 becomes smaller and smaller, even reaching 3 nm, the depth of the source-drain region increases with the increase in the height of the fin, even up to 50 nm, while the opening width of the opening region is 15 - 100 nm. On such a small epitaxial growth substrate, the part growing upward from the bottom of the opening region will eventually merge with the silicon-doped material growing from the side walls on both sides of the opening region. And due to the different crystal planes of the epitaxial single-crystalline materials growing from the side walls of the two fins 101, they cannot be completely fused together, and a slit groove 180 will be formed in the middle. Among them, the width of the slit groove 180 is 0.2 - 2 nm, and the height is 5 - 40 nm.

[0105] While growing upward epitaxially in the opening region, it will also grow in the direction of the gate extension, as Figure 7 shown. In order to prevent the epitaxial fusion of adjacent opening regions from causing device failure, it is necessary to control the growth width of the source-drain region 120 in the direction of the gate extension, which in turn will also affect the growth of the source-drain region 120 in the height direction. When the top critical dimension width of the fin structure 101 is less than 10 nm and the height of the fin structure 101 is greater than 40 nm, the high-doped region layer 122 of the source-drain region 120 cannot completely fill the source-drain region 120, thus forming a triangular groove on the top of the high-concentration doping region. And due to the epitaxial growth characteristics of SiP and SiC, the top surface of the high-concentration doping region where the triangular groove is formed forms an acute angle α with the upper surface of the substrate 100.

[0106] Specifically, due to the continuous increase in the doping concentration of the source-drain region 120, the growth rate difference of the materials on different crystal planes during epitaxy becomes larger, manifested as the growth rate: crystal plane

[100] > crystal plane

[110] > crystal plane

[111] . When the outermost surface of the source-drain region mostly becomes the crystal plane

[111] , the growth rate of the source-drain region drops to the growth threshold, and the upper surface of the finally formed high-doped region layer 122 stays on this crystal plane. Thus, in this embodiment, an acute angle α is formed between the upper surface of the high-doped region layer 122 and the upper surface of the substrate 100, where the angle of the acute angle α is 40 - 70 degrees.

[0107] It should be noted that the thickness of the highly doped region layer 122 is 20 to 50 nm, and its lattice parameter is 5.3 - 5.43 Å, which is smaller than that of silicon. The highly doped region layer 122 provides tensile stress for the channel region and simultaneously reduces the resistance of the source / drain regions 120.

[0108] In some embodiments, by performing gas purging on the surface of the highly doped region layer 122 and continuously introducing a third growth gas source and a third doping gas source to the surface of the highly doped region layer 122, and simultaneously adjusting the partial pressure ratio of the third doping gas source in all reaction gases to be 0.2% - 0.6%, so that the concentration of the doped impurity material in the single-crystalline silicon-based material in the subsequent obtained covering region layer 123 reaches 1E18 - 5E20 atom cm -3 , and simultaneously reducing the reaction pressure, so that the covering region layer 123 is formed in a growth mode from bottom to top, so that the covering region layer 123 starts to grow from the bottommost part of the highly doped region layer 122, that is, from the surface of the highly doped region layer 122.

[0109] The third growth gas source of the covering region layer 123 is mainly composed of a mixture of DCS and SiH4, and the proportion of SiH4 in the third growth gas source is 5% - 30%; since the molecular size of SiH4 is smaller, it is more conducive to penetrating into the inside of the slit groove 180 for nucleation growth. At the same time, to improve the reaction selectivity of the epitaxial reaction on silicon / silicon oxide or silicon nitride, while adding the etching gas HCl, DCS containing a chlorine component is still used as the third growth gas source to provide a silicon source. At the same time, the epitaxial reaction of this layer is carried out under low pressure, and the reaction pressure is 10 - 150 Torr. Since under low pressure, the collisions between molecules are reduced, the mean free path of molecules increases, and the reaction molecules are more likely to enter the bottom of the source / drain regions for growth, so that the covering region layer 123 is more likely to grow along the surface of the highly doped region layer 122. At the same time, increasing the volume ratio of SiH4 in the third growth gas source to reduce the growth rate difference of the doped material on different crystal planes, so as to ensure that the covering region layer 123 can grow from bottom to top and form a funnel-shaped covering region layer 123. Since the phosphorus doping concentration of the covering region layer 123 is low, in order to reduce the influence of the phosphorus concentration reduction on stress and resistance, the growth thickness of the covering region layer 123 is controlled to be 2 - 20 nm.

[0110] After successively preparing the nucleation region layer 121, the highly doped region layer 122, and the covering region layer 123, the opening region 110 is filled by the nucleation region layer 121, the highly doped region layer 122, and the covering region layer 123 to form the source / drain regions 120, so that by using the source / drain regions 120 on both sides of the gate region 130 as the source electrode and the drain electrode respectively, an NMOS structure is formed.

[0111] The NMOS structure prepared through the above process steps effectively fills the source / drain regions of the NMOS and uses a nucleation region layer, a high-doping region layer, and a covering region layer to form the source and drain regions. While achieving high stress and low resistance in the source and drain regions of the NMOS, the growth height of the doping material in the source and drain regions is increased as much as possible, reducing the source and drain region gaps and the source and drain region length being too short, thereby reducing the process risks of missing the source and drain regions, the middle section metal not being able to contact the source and drain, or the source and drain regions being penetrated when preparing the middle section metal in the subsequent wet process.

[0112] The present invention also discloses an NMOS structure, comprising:

[0113] substrate 100;

[0114] The fin structure 101 is disposed above the substrate 100;

[0115] A gate 130 is disposed above the fin structure 101;

[0116] The source electrode 111 is disposed in the top region of the fin structure 101 and is located on one side of the gate electrode 130 ;

[0117] The drain 112 is disposed in the top region of the fin structure 101 and is located on the other side of the gate 130 ;

[0118] The source 111 and / or drain 112 includes a nucleation region layer 121 , a high-doping region layer 122 and a covering region layer 123 arranged in sequence from bottom to top, and a slit groove 180 is provided inside the high-doping region layer 123 .

[0119] In the above-mentioned NMOS structure, since the source 111 and the drain 112 are both composed of a nucleation region layer 121, a high-doping region layer 122 and a covering region layer 123 stacked together, while achieving high stress and low resistance in the source 111 and the drain 112 of the NMOS structure, the growth height of the doping material of the source 111 and the drain 112 can be increased to reduce the phenomenon of too little growth material in the source 111 and the drain 112, thereby reducing the process risks in subsequent processes that may cause the source and drain regions to be missing, the source and drain regions to be out of contact, and the source and drain regions to be penetrated.

[0120] In some embodiments, a slit groove 180 is provided in the middle of the highly doped region layer 122 , the covering region layer 123 fills the slit groove 180 and covers the upper surface of the highly doped region layer 122 , and the covering region layer 123 is funnel-shaped.

[0121] In some embodiments, the angle between the hypotenuse of the upper surface of the highly doped region layer 122 and the horizontal plane is 40° to 70°, that is, the angle between the upper surface of the highly doped region layer 122 and the upper surface of the substrate 100 is 40° to 70°.

[0122] In some embodiments, the height of the fin structure 101 is 80 to 160 nm, and the height of the gate region 130 is 30 to 80 nm.

[0123] A first dielectric layer 140 is disposed above the gate 130, and a sidewall isolation layer 150 is disposed on the sidewalls of the gate 130.

[0124] Since the above NMOS structure is obtained according to the manufacturing method of the foregoing NMOS structure, it will not be elaborated here.

[0125] The present invention further provides a semiconductor device, including the above-mentioned NMOS structure.

[0126] By adopting the above NMOS structure, the semiconductor device effectively improves the performance of the semiconductor device. While achieving high stress and low resistance in the source / drain regions of the NMOS, it can increase the growth height of the doping material in the source / drain regions.

[0127] Although the embodiments of the present invention have been described in detail above, it is obvious to those skilled in the art that various modifications and changes can be made to these embodiments. However, it should be understood that such modifications and changes fall within the scope and spirit of the present invention described in the claims. Moreover, the present invention described herein can have other embodiments and can be implemented or realized in various ways.

Claims

1. A manufacturing method of an NMOS structure, characterized in that, Including: Providing a substrate; Forming a plurality of fin structures on the substrate; Forming a gate oxide layer on the surface of the fin structures, depositing an isolation layer between the fin structures, and forming a gate material layer above the isolation layer and the gate oxide layer of the fin structures; Patterning the gate material layer to form a plurality of gate lines, forming a gate spacer trench between adjacent gate lines, and forming a sidewall isolation layer on the surface of the obtained structure; Etching the sidewall isolation layer on the upper surface of the gate oxide layer, the gate oxide layer and a part of the fin structures along the gate spacer trench to form an opening region; Sequentially forming a nucleation region layer, a highly doped region layer and a covering region layer from bottom to top inside the opening region to form a source or a drain, wherein the formation process of the highly doped region layer includes: Introducing a second growth gas source and a second doping gas source into the opening region where the nucleation region layer is formed, and controlling the partial pressure ratio of the second doping gas source in the current reaction gas source to a second threshold; Controlling the reaction temperature and reaction pressure to form a highly doped region layer on the surface of the nucleation region layer; Continuously introducing the second growth gas source and the second doping gas source until the growth rate of the upper surface of the highly doped region layer decreases to a growth threshold, and then stopping introducing the second growth gas source and the second doping gas source; Among them, the concentration of the doping element in the second doping gas source in the high-doping region layer is 5E19 to 6E21 atom / cm -3 .

2. The manufacturing method of the NMOS structure according to claim 1, characterized in that, The formation process of the nucleation region layer includes: Introducing a first growth gas source and a first doping gas source into the opening region, adjusting the partial pressure ratio of the first doping gas source in the current reaction gas source to a first threshold, and controlling the reaction temperature and reaction pressure to form the nucleation region layer on the inner wall of the opening region; Continuously introducing the first growth gas source and the first doping gas source until the thickness of the nucleation region layer reaches 2 cm, and then stopping introducing the first growth gas source and the first doping gas source.

3. The manufacturing method of the NMOS structure according to claim 2, characterized in that, During the formation process of the nucleation region layer, the reaction temperature is 600-700 degrees Celsius, and the reaction pressure is 100-600 Torr.

4. The manufacturing method of the NMOS structure according to claim 1 or 2, characterized in that, The formation process of the highly doped region layer includes: Introducing a second growth gas source and a second doping gas source into the opening region where the nucleation region layer is formed, controlling the partial pressure ratio of the second doping gas source in the current reaction gas source to a second threshold, the second threshold being greater than the first threshold; controlling the reaction temperature and reaction pressure to form a highly doped region layer on the surface of the nucleation region layer, and forming a vertical slit trench at the middle position of the highly doped region layer; 5. The manufacturing method of the NMOS structure according to claim 1, characterized in that The reaction temperature during the preparation process of the highly doped region layer is 550-650 degrees Celsius, and the reaction pressure is 300-600 Torr.

6. The manufacturing method of the NMOS structure according to claim 4, characterized in that, The formation process of the covering region layer includes: Performing gas purging on the surface of the highly doped region layer, continuously introducing a third growth gas source and a third doping gas source to the surface of the highly doped region layer, and adjusting the partial pressure ratio of the third doping gas source in the current reaction gas source to a third threshold; Reducing the reaction pressure to grow a funnel-shaped covering region layer inside the slit trench and on the surface of the highly doped region layer; Continuously introducing the third growth gas source and the third doping gas source until the grown covering region layer completely covers the surface of the highly doped region layer.

7. The manufacturing method of the NMOS structure according to claim 1, characterized in that, Before the nucleation region layer, the high-doping region layer, and the covering region layer are sequentially formed from bottom to top inside the opening region, the method further includes preprocessing the opening region, and the preprocessing process includes: Processing the inner surface of the opening region to remove carbon-containing and oxygen-containing materials on the surface of the opening region; Performing a lattice repair process on the surface of the opening region.

8. An NMOS structure, obtained by manufacturing using the manufacturing method of the NMOS structure according to any one of claims 1 to 7, characterized in that, Including: A substrate; A fin structure disposed above the substrate; A gate disposed above the fin structure; A source electrode disposed at the top region of the fin structure and on one side of the gate; A drain electrode disposed at the top region of the fin structure and on the other side of the gate; Wherein, the source electrode and / or the drain electrode include a nucleation region layer, a high-doping region layer, and a covering region layer sequentially disposed from bottom to top, and a slit groove is disposed inside the high-doping region layer.

9. The NMOS structure according to claim 8, wherein A slit groove is disposed at the middle position of the high-doping region layer, the covering region layer fills the inside of the slit groove and covers the upper surface of the high-doping region layer, and the covering region layer is funnel-shaped.

10. A semiconductor device, characterized in that, Including the NMOS structure according to claim 8 or 9.

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