Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same, the method comprising: forming a plurality of lower electrodes on a substrate, the lower electrodes comprising an annular wall and a petal-shaped wall extending in a direction perpendicular to the surface of the substrate, and the petal-shaped wall dividing the interior of the annular wall into a plurality of discrete first openings; forming a dielectric layer on the bottom and sidewalls of the first openings; forming an upper electrode in the first opening, the dielectric layer being located between the lower electrode and the upper electrode. The lower electrode of the present invention comprises an annular wall and a petal-shaped wall, so that the surface area of ​​the lower electrode is increased, and when a dielectric layer and a corresponding upper electrode are subsequently formed on the lower electrode, the surface area of ​​the dielectric layer and the upper electrode will also increase accordingly, thereby increasing the capacitance value of the formed semiconductor structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor memory device commonly used in computers, consisting of many repeated storage cells. Each storage cell usually includes a capacitor and a transistor. The gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor. The voltage signal on the word line can control the opening or closing of the transistor, and then read the data information stored in the capacitor through the bit line, or write the data information into the capacitor through the bit line for storage.

[0003] As the manufacturing process continues to evolve, DRAM integration continues to increase, component size continues to shrink, and the charge storage capacity of capacitors is also facing challenges. The capacitance value of capacitors needs to be improved urgently. Summary of the invention

[0004] The technical problem to be solved by the present invention is how to increase the capacitance value of the semiconductor structure.

[0005] The present invention provides a method for forming a semiconductor structure, comprising:

[0006] providing a substrate;

[0007] forming a plurality of lower electrodes on the substrate, wherein the lower electrodes include an annular wall and a petal-shaped wall extending in a direction perpendicular to the surface of the substrate, and the petal-shaped wall divides the interior of the annular wall into a plurality of discrete first openings;

[0008] forming a dielectric layer on a bottom and sidewalls of the first opening;

[0009] An upper electrode is formed in the first opening, and the dielectric layer is located between the lower electrode and the upper electrode.

[0010] Optionally, forming a plurality of lower electrodes on the substrate includes:

[0011] forming a first conductive layer on the substrate;

[0012] Etching the first conductive layer to form a plurality of first conductive pillars and second openings between the first conductive pillars;

[0013] forming a first dielectric layer filling the second opening;

[0014] Etching the first conductive column to form the annular wall and the third opening;

[0015] Filling the third opening with a second conductive layer to form a second conductive column;

[0016] forming a mask opening layer above the second conductive pillar to expose a portion of the second conductive pillar;

[0017] The second conductive pillar is etched using the mask opening layer to form the petal-shaped wall.

[0018] Optionally, before filling the third opening with a second conductive layer to form a second conductive column, the method further includes:

[0019] A barrier layer is formed on the surface of the annular wall.

[0020] Optionally, the mask opening layer has an opening pattern, and the opening pattern exposes portions of upper surfaces of a plurality of adjacent second conductive pillars.

[0021] Optionally, central axes of the first conductive pillar and the second conductive pillar coincide with each other.

[0022] Optionally, the opening pattern and the overlapping area of ​​the second conductive pillar are the same in shape and size.

[0023] Optionally, also include:

[0024] forming a contact pad on the substrate, wherein the contact pad has a convex portion protruding from a surface of the substrate;

[0025] The lower portion of the annular wall wraps around the side wall of the protrusion.

[0026] Optionally, also include:

[0027] removing the first dielectric layer;

[0028] forming the dielectric layer on the outer wall and the top surface of the annular wall;

[0029] The upper electrode is formed in the second opening, and the dielectric layer is located between the upper electrode and the outer wall of the annular wall.

[0030] The present invention also provides a semiconductor structure, comprising:

[0031] substrate;

[0032] A plurality of lower electrodes located on the substrate, the lower electrodes comprising an annular wall and a petal-shaped wall, the annular wall and the petal-shaped wall extending in a direction perpendicular to the surface of the substrate, and the petal-shaped wall dividing the interior of the annular wall into a plurality of discrete openings;

[0033] a dielectric layer disposed on the bottom and sidewalls of the opening;

[0034] An upper electrode fills the opening, and the dielectric layer is located between the lower electrode and the upper electrode.

[0035] Optionally, the annular wall and the petal-shaped wall are made of different materials.

[0036] Optionally, the material of the annular wall includes any one of a conductive semiconductor material, a conductive polymer material or a conductive amorphous material or any combination thereof, and the material of the petal-shaped wall includes a conductive material containing a metal element.

[0037] Optionally, the plurality of lower electrodes are arranged in a honeycomb shape, and the petal-shaped wall boundaries of the openings in adjacent lower electrodes are on the same circumference.

[0038] Optionally, the petal-shaped wall divides the interior of the annular wall into three separate openings.

[0039] Optionally, the dielectric layer is also located on the top and outer wall of the annular wall and the top of the petal-shaped wall.

[0040] Optionally, also include:

[0041] a contact pad disposed in the substrate, the contact pad having a protrusion protruding from a surface of the substrate;

[0042] The lower portion of the annular wall wraps around the side wall of the protrusion.

[0043] Optionally, a barrier layer is further included between the annular wall and the petal-shaped wall.

[0044] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0045] The method for forming a semiconductor structure of the present invention forms a plurality of lower electrodes on a substrate, wherein the lower electrodes include an annular wall and a petal-shaped wall extending in a direction perpendicular to the surface of the substrate, and the petal-shaped wall divides the interior of the annular wall into a plurality of discrete first openings; a dielectric layer is formed on the bottom and sidewalls of the first openings; and an upper electrode is formed in the first openings, wherein the dielectric layer is located between the lower electrode and the upper electrode. The lower electrode of the present invention includes an annular wall and a petal-shaped wall, so that the surface area of ​​the lower electrode is increased. When a dielectric layer and a corresponding upper electrode are subsequently formed on the lower electrode, the surface area of ​​the dielectric layer and the upper electrode will also increase accordingly, thereby increasing the capacitance value of the formed semiconductor structure.

[0046] Furthermore, the contact pad has a protrusion protruding from the surface of the substrate. When a lower electrode is subsequently formed on the contact pad, the lower portion of the annular wall of the lower electrode can wrap around the side wall of the protrusion, thereby making the lower electrode and the contact pad have a larger contact area, making it difficult for the lower electrode to tilt or shift in position.

[0047] Furthermore, before etching the second conductive pillars, a mask opening layer is formed on the second conductive pillars, the mask opening layer having an opening pattern, and the opening pattern exposes a portion of the upper surface of a plurality of adjacent second conductive pillars. Therefore, when performing the process of forming the mask opening layer (mask process), the size of the opening pattern formed in the mask opening layer will not be affected by the size (smaller size) of the portion to be removed in the second conductive pillars, thereby reducing the difficulty of the mask process. Even if the size of the portion to be removed in the second conductive pillars is smaller than the minimum feature size of photolithography, the second conductive pillars can be etched to form the petal-shaped walls through the aforementioned mask process.

[0048] In the semiconductor structure of the present invention, the lower electrode includes an annular wall and a petal-shaped wall, so that the surface area of ​​the lower electrode is increased. When a dielectric layer and a corresponding upper electrode are subsequently formed on the lower electrode, the surface area of ​​the dielectric layer and the upper electrode will also increase accordingly, thereby increasing the capacitance value of the formed semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1-14 It is a structural schematic diagram of the formation process of the semiconductor structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0050] As mentioned in the background art, the capacitance value of the existing semiconductor structure still needs to be improved.

[0051] To this end, the present invention provides a semiconductor structure and a method for forming the same, the method comprising: providing a substrate; forming a plurality of lower electrodes on the substrate, the lower electrodes comprising an annular wall and a petal-shaped wall extending in a direction perpendicular to the surface of the substrate, and the petal-shaped wall divides the interior of the annular wall into a plurality of discrete first openings; forming a dielectric layer on the bottom and sidewalls of the first openings; forming an upper electrode in the first opening, the dielectric layer being located between the lower electrode and the upper electrode. The lower electrode of the present invention comprises an annular wall and a petal-shaped wall, so that the surface area of ​​the lower electrode is increased, and when a dielectric layer and a corresponding upper electrode are subsequently formed on the lower electrode, the surface area of ​​the dielectric layer and the upper electrode will also increase accordingly, thereby increasing the capacitance value of the formed semiconductor structure.

[0052] In order to make the above-mentioned objects, features and advantages of the present invention more clearly understood, the specific embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. When describing the embodiments of the present invention in detail, for the sake of convenience, the schematic diagrams will not be partially enlarged according to the general proportion, and the schematic diagrams are only examples, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.

[0053] refer to Figure 1 , providing a substrate 201.

[0054] In one embodiment, the base 201 may include a semiconductor substrate and an interlayer dielectric layer located on the semiconductor substrate.

[0055] The material of the semiconductor substrate 201 can be silicon (Si), germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); it can also be silicon on insulator (SOI), germanium on insulator (GOI); or it can also be other materials, such as III-V group compounds such as gallium arsenide. In this embodiment, the semiconductor substrate is a silicon substrate.

[0056] The semiconductor substrate 201 has active regions and trench isolation structures for isolating the active regions. A semiconductor device may be formed on the active region of the semiconductor substrate 201, and the semiconductor device may include a planar transistor or a trench transistor.

[0057] An interlayer dielectric layer may also be formed on the semiconductor substrate 201. A connection line may be formed in the interlayer dielectric layer to connect the planar transistor or trench transistor to a subsequently formed semiconductor structure. The connection line includes one or a combination of metal plugs, metal wires, pads, and conductive connection structures (doped polysilicon). The interlayer dielectric layer may be a single-layer or multi-layer stacked structure. The material of the interlayer dielectric layer may be silicon oxide, silicon nitride, silicon oxynitride, FSG (fluorine-doped silicon dioxide), BSG (boron-doped silicon dioxide), PSG (phosphorus-doped silicon dioxide) or BPSG (boron-phosphorus-doped silicon dioxide), low dielectric constant materials, other suitable materials and / or combinations thereof.

[0058] In one embodiment, contact pads 202 are formed on the substrate 201. Specifically, the contact points 202 may be formed in the interlayer dielectric layer of the substrate 201. The contact pads 202 are used to connect to the lower electrode layer of the semiconductor structure formed subsequently. For example, the arrangement of the plurality of contact pads 202 may be the same as the arrangement of the lower electrode formed subsequently.

[0059] In one embodiment, the contact pad 202 has a protrusion protruding from the surface of the substrate. When a lower electrode is subsequently formed on the contact pad 202, the lower portion of the annular wall of the lower electrode can wrap around the side wall of the protrusion, so that the lower electrode and the contact pad 202 have a larger contact area, making it difficult for the lower electrode to tilt or shift in position.

[0060] The material of the contact pad 202 may be any one of W, Cu, Ti, Ni, Al, Co, TiN or metal silicide or any combination thereof. The contact point 202 may be formed by depositing a conductive layer and then etching the conductive layer, or by electroplating.

[0061] In one embodiment, a first barrier layer 203 is further formed on the surface of the substrate 201 and the contact pad 202. The first barrier layer 203 can be used to prevent the metal in the contact pad 202 from diffusing outward, reduce the contact resistance between the contact pad 202 and the subsequently formed lower electrode, and enhance the adhesion between the contact pad 202 and the subsequently formed lower electrode. The material of the first barrier layer 203 can be one or more of Ti, Ta, TiN, and TaN, and the formation process can include sputtering or deposition process.

[0062] refer to Figure 3 , a first conductive layer 204 is formed on the substrate 201 .

[0063] The first conductive layer 204 is subsequently used to form a first conductive column.

[0064] The material of the first conductive layer 204 includes any one of a conductive semiconductor material, a conductive polymer material, or a conductive amorphous material, or any combination thereof.

[0065] In one embodiment, the doped semiconductor material may be silicon or germanium doped with impurity ions, the impurity ions may be P-type impurity ions or N-type impurity ions, the P-type impurity ions may be one or more of boron ions, gallium ions or indium ions, and the N-type impurity ions may be phosphorus ions, arsenic ions or antimony ions.

[0066] In one embodiment, the conductive polymer may be a conductive carbon-containing main chain polymer, a hydrocarbon silicate-containing main chain polymer, a hydrocarbon silicate-containing main chain polymer, or a combination of a conductive carbon-containing main chain polymer and a hydrocarbon silicate-containing main chain polymer.

[0067] In one embodiment, the conductive amorphous material may be composed of from about 55% to about 70% carbon atoms, about 5% or less nitrogen, oxygen, sulfur, metal atoms and semi-metals (one or more of boron, silicon, arsenic, selenium, tellurium) and hydrogen.

[0068] refer to Figure 4 and Figure 5 , Figure 4 for Figure 5 The schematic cross-sectional structure diagram along the cutting line AB shows that the first conductive layer 204 is etched to form a plurality of first conductive pillars 215 and second openings 206 between the first conductive pillars 215 .

[0069] An anisotropic dry etching process, such as a plasma etching process, may be used to etch the first conductive layer 204. Before etching the first conductive layer 204, a patterned mask layer (not shown in the figure) may be formed on the surface of the first conductive layer 204, and the patterned mask layer exposes the area of ​​the first conductive layer 204 that needs to be etched and removed.

[0070] In one embodiment, the first conductive pillar 215 is formed on the contact pad 202, and the first conductive pillar 215 covers the top and sidewall of the convex portion of the contact portion 202, and the first barrier layer 203 is located between the first conductive pillar 215 and the contact pad 202. When etching the first conductive layer, the first barrier layer 203 exposed at the bottom of the second opening 206 is also cut off, so that adjacent first conductive pillars 215 are separated and have no electrical connection.

[0071] In this embodiment, the first conductive pillars 215 are cylindrical, and the first conductive pillars 215 are arranged in a honeycomb shape.

[0072] In one embodiment, the first conductive pillar 215 is in the shape of an elliptical column or a square column. Specifically, the cross section of the first conductive pillar 215 perpendicular to its extension direction is in the shape of an ellipse or a square. In other embodiments, the shape of the cross section is not limited and is selected according to actual process conditions.

[0073] refer to Figure 6 and Figure 7 , Figure 6 for Figure 7 Schematic diagram of the cross-sectional structure along the cutting line AB, etching the first conductive column 215 (refer to Figure 5 ) forms an annular wall 205 and a third opening 207.

[0074] In one embodiment, before etching the first conductive pillar 215, a first dielectric layer or sacrificial layer filling the second opening 206 may be formed, and the first dielectric layer or sacrificial layer may be removed after forming the annular wall 205 or subsequently forming the petal-shaped wall. In other embodiments, before etching the first conductive pillar 215, a mask layer serving as a mask for etching the first conductive pillar is formed on the first conductive pillar 215 and the surface of the substrate, and the mask layer fills the second opening 206.

[0075] The first conductive pillar 215 may be etched by an anisotropic dry etching process, such as a plasma etching process. For example, a mask opening is formed on the first conductive pillar 215, the mask opening exposes the central part of the first conductive pillar 215, and the central part of the first conductive pillar 215 is etched by the mask opening to form an annular wall 205 and a third opening 207. A portion of the first conductive pillar around the edge is retained as the annular wall 205, and the etched position in the first conductive pillar 215 forms the third opening 207. The thickness of the annular wall 205 may be 1 to 10 nm. When the central part of the first conductive pillar 215 is etched by the mask opening to form the third opening 207, the bottom of the formed third opening 207 may be the first barrier layer 203 or the contact portion 202, that is, the first barrier layer 203 or the contact portion 202 is used as an etching stop layer. In other embodiments, the bottom of the formed opening 207 may also be part of the first conductive column 215. For example, the etching time is controlled so that the thickness of the first conductive column 215 remaining at the bottom of the third opening 207 is controllable. Specifically, the thickness of the first conductive column 215 remaining at the bottom of the third opening 207 is the same as the thickness of the annular wall 205.

[0076] In this embodiment, the annular wall 205 is in a circular ring shape. In other embodiments, the annular wall 205 may be in an elliptical ring shape, a square ring shape, etc.

[0077] In one embodiment, reference Figure 8 Before filling the second conductive layer in the third opening to form the second conductive column, the method further includes: forming a second barrier layer 208 on the surface of the annular wall 205 .

[0078] The second barrier layer 208 can prevent the material of the second conductive column formed in the subsequent third opening from diffusing outward, or improve the contact resistance between the second conductive column and the annular wall, or improve the adhesion between the second conductive column and the annular wall, etc. The material of the second barrier layer 208 can be one or more of Ti, Ta, TiN, and TaN, and the formation process can be a sputtering or deposition process.

[0079] In one embodiment, when the second opening 206 is not filled with the first dielectric layer or the sacrificial layer, a second barrier layer 208 is also formed on the bottom and sidewalls of the second opening 206 .

[0080] refer to Fig. 9 , in the third opening 207 (reference Figure 8 ) is filled with a second conductive layer to form a second conductive column 219.

[0081] The second conductive pillar 219 is subsequently used to form a petal-shaped wall of the lower electrode. The formed second conductive pillar can coincide with the central axis of the first conductive pillar, which can reduce the difficulty of the mask process when etching the second conductive pillar, and make the shape of the petal-shaped wall in each lower electrode etched by the mask process consistent or slightly different.

[0082] The material of the second conductive column 219 is different from the material of the second barrier layer 208 and the annular wall 205. On the one hand, when the second conductive column 219 is subsequently etched to form a petal-shaped wall, the second conductive column 219 has a high etching selectivity relative to the second barrier layer 208 and the annular wall 205, so that the second barrier layer 208 and the annular wall 205 remain intact. On the other hand, the difficulty of the mask process before etching the second conductive column 219 can be reduced.

[0083] In one embodiment, the material of the second conductive pillar 219 includes a conductive material containing a metal element, such as W, Co, Ni, TiN or other suitable conductive materials.

[0084] In one embodiment, when the second opening is not filled by the first dielectric layer or the sacrificial layer, the second conductive layer further fills the second opening.

[0085] refer to Fig.10 and Fig.11 , Fig.10 for Fig.11 The schematic cross-sectional structure diagram along the cutting line CD direction, in the second conductive column 219 (reference Fig. 9 ) is formed above the second conductive pillar to expose a portion of the second conductive pillar (not shown in the figure); the second conductive pillar 219 is etched using the mask opening layer to form the petal-shaped wall 209.

[0086] The petal-shaped wall 209 divides the interior of the annular wall 205 into a plurality of discrete first openings 216. A plurality of lower electrodes are formed on the substrate 201. The lower electrode comprises an annular wall 205 and a petal-shaped wall 209 located inside the annular wall 205. The lower electrode of the present invention comprises a special structure of the annular wall 205 and the petal-shaped wall 209, so that the surface area of ​​the lower electrode is increased. When a dielectric layer and a corresponding upper electrode are subsequently formed on the lower electrode, the surface areas of the dielectric layer and the upper electrode will also increase accordingly, thereby increasing the capacitance value of the formed semiconductor structure.

[0087] Before etching the second conductive pillar 219, a mask opening layer needs to be formed on the second conductive pillar 219. The mask opening layer has an opening pattern, and the opening pattern exposes a portion of the upper surface of a plurality of adjacent second conductive pillars. For example, the opening pattern can be circular, and the circular opening pattern exposes a portion of the upper surface of three adjacent second conductive pillars. The mask opening layer only covers the surface of the portion of the second conductive pillar 219 that needs to be retained. Please refer to Fig.11 The area covered by the mask opening layer is the area corresponding to the petal-shaped wall 209, and other areas can be exposed. The mask opening layer has a circular opening pattern. Fig.11 The middle thick solid line shows the shape of a circular opening pattern 220, which exposes part of the upper surface of three adjacent second conductive pillars. The circular opening pattern 220 can also expose the surface of the material filled in the annular wall 205 and the second opening 206 between adjacent second conductive pillars (when etching the second conductive pillars, since the annular wall 205 is made of different materials from the second conductive pillars, the etching amount of the annular wall 205 is very small or negligible). Therefore, when performing the process of forming the mask opening layer (mask process), the size of the circular opening pattern 220 formed in the mask opening layer will not be affected by the size (smaller size) of the part to be removed in the second conductive pillar, thereby reducing the difficulty of the mask process. Even if the size of the part to be removed in the second conductive pillar is smaller than the minimum feature size of the photolithography, the second conductive pillar 219 can be etched through the aforementioned mask process to form the petal-shaped wall 209. The petal-shaped wall boundaries of the first opening 216 in the adjacent lower electrode formed by the circular opening pattern 220 are on the same circumference.

[0088] In one embodiment, the shape and size of the overlapping area of ​​the circular opening pattern and the second conductive column are the same. In this embodiment, the second conductive column can overlap with three circular opening patterns, so that the petal-shaped wall 209 formed divides the interior of the annular wall 205 into three first openings 216 of the same shape and size, which increases the surface area of ​​the lower electrode and facilitates and simplifies the mask process.

[0089] In one embodiment, when the material filled in the second opening 206 is a second conductive layer, the second conductive layer in the second opening can be removed simultaneously when etching the second conductive column, so that the second opening is exposed again, and a dielectric layer and an upper electrode layer can be subsequently formed in the second opening, so that a capacitor is also formed between the dielectric layer and the upper electrode in the second opening and the adjacent annular wall 205, thereby further improving the capacitance value of the formed semiconductor structure.

[0090] In one embodiment, when a second barrier layer 208 is formed on the inner wall of the annular wall 205, the second barrier layer 208 can be used as an etching stop layer when etching the second conductive pillar. After the petal-shaped wall 209 is formed, the surface of the petal-shaped wall 209 can be nitrided so that part of the surface material of the petal-shaped wall 209 is nitrided, and a metal nitride (such as tungsten nitride) is formed on the surface of the petal-shaped wall 209. The metal nitride can further prevent the metal in the petal-shaped wall 209 from diffusing into the dielectric layer to ensure the isolation performance of the dielectric layer.

[0091] refer to Fig.12 , a dielectric layer 211 is formed on the bottom and sidewalls of the first opening 216 .

[0092] The material of the dielectric layer 211 can be a high-K dielectric material to increase the capacitance value of the capacitor per unit area. The high-K dielectric material includes one of ZrOx, HfOx, ZrTiOx, RuOx, SbOx, AlOx, or a stack formed by two or more of the group consisting of the above materials.

[0093] In one embodiment, a dielectric layer 211 is also formed on the outer wall and top surface of the annular wall 205 and the top surface of the petal-shaped wall 209 .

[0094] refer to Fig.13 and Fig.14 , Fig.14 for Fig.13 The cross-sectional view of an annular wall and the interior thereof is shown in FIG. 2 , wherein an upper electrode 212 is formed in the first opening, and the dielectric layer 211 is located between the lower electrode and the upper electrode 212 .

[0095] The material of the upper electrode 212 can be one of tungsten, titanium, nickel, aluminum, platinum, titanium nitride, N-type polysilicon, P-type polysilicon, or a stack formed by two or more of the group consisting of the above materials. It can also include a compound formed by one or two of metal nitrides and metal silicides, such as titanium nitride (Titanium Nitride), titanium silicide (Titanium Silicide), nickel silicide (Titanium Silicide), titanium silicon nitride (TiSixNy), etc.

[0096] In one embodiment, the formed semiconductor structure includes an upper electrode 212 , a lower electrode, and a dielectric layer 211 located between the upper electrode 212 and the lower electrode. The upper electrode 212 is continuous, and a plurality of lower electrodes are separated.

[0097] In one embodiment, the second opening is also filled with an upper electrode 212 .

[0098] The present invention also provides a semiconductor structure, referring to Fig.13 and Fig.14 ,include:

[0099] Base 201;

[0100] A plurality of lower electrodes located on the substrate 201, the lower electrodes comprising an annular wall 205 and a petal-shaped wall 209, the annular wall 205 and the petal-shaped wall 209 extending in a direction perpendicular to the surface of the substrate 201, and the petal-shaped wall 209 divides the interior of the annular wall 205 into a plurality of discrete openings 216;

[0101] A dielectric layer 211, located on the bottom and sidewalls of the opening 216;

[0102] The upper electrode 212 fills the opening, and the dielectric layer 211 is located between the lower electrode and the upper electrode 212 .

[0103] In one embodiment, the materials of the annular wall 205 and the petal-shaped wall 209 are different. The material of the annular wall 205 includes any one of a conductive semiconductor material, a conductive polymer material, or a conductive non-crystalline material or any combination thereof, and the material of the petal-shaped wall 209 includes a conductive material containing a metal element. In one embodiment, the plurality of lower electrodes are arranged in a honeycomb shape, and the petal-shaped wall boundaries of the openings in adjacent lower electrodes are on the same circumference.

[0104] In one embodiment, the petal-shaped wall 209 divides the interior of the annular wall 205 into a plurality of separate openings, such as three separate openings.

[0105] In one embodiment, the dielectric layer 211 is also located on the top and outer wall of the annular wall and the top of the petal-shaped wall.

[0106] In one embodiment, the invention further comprises: a contact pad 202 located in the substrate 201, wherein the contact pad 202 has a convex portion protruding from the surface of the substrate 201;

[0107] The lower portion of the annular wall 205 wraps around the side wall of the protrusion.

[0108] In one embodiment, a barrier layer 208 is further included between the annular wall 205 and the petal-shaped wall 209 .

[0109] In one embodiment, there is a second opening between adjacent lower electrodes, the dielectric layer is also located on the outer wall and top surface of the annular wall 205 and the top surface of the petal-shaped wall 209 , and the upper electrode 212 is also located in the second opening.

[0110] It should be noted that the limitations or descriptions of the same or similar structures in this embodiment (semiconductor structure) and the aforementioned embodiments (formation process of semiconductor structure) are no longer repeated in this embodiment. Please refer to the limitations or descriptions of the corresponding parts in the aforementioned embodiments for details.

[0111] Although the present invention has been disclosed as above in the form of a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art may make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; forming a contact pad on the substrate, wherein the contact pad has a convex portion protruding from a surface of the substrate; forming a plurality of lower electrodes on the substrate, wherein the lower electrodes include an annular wall and a petal-shaped wall extending in a direction perpendicular to the surface of the substrate, and the petal-shaped wall divides the interior of the annular wall into a plurality of discrete first openings; forming a dielectric layer on a bottom and sidewalls of the first opening; forming an upper electrode in the first opening, the dielectric layer being located between the lower electrode and the upper electrode; The lower portion of the annular wall wraps around the side wall of the protrusion.

2. The method for forming a semiconductor structure according to claim 1, wherein: The step of forming a plurality of lower electrodes on the substrate comprises: forming a first conductive layer on the substrate; Etching the first conductive layer to form a plurality of first conductive pillars and second openings between the first conductive pillars; forming a first dielectric layer filling the second opening; Etching the first conductive column to form the annular wall and the third opening; Filling the third opening with a second conductive layer to form a second conductive column; forming a mask opening layer above the second conductive pillar to expose a portion of the second conductive pillar; The second conductive pillar is etched using the mask opening layer to form the petal-shaped wall.

3. The method for forming a semiconductor structure according to claim 2, wherein: Before the second conductive layer is filled in the third opening to form the second conductive column, the method further includes: A barrier layer is formed on the surface of the annular wall.

4. The method for forming a semiconductor structure according to claim 2, wherein: The mask opening layer has an opening pattern, and the opening pattern exposes a portion of the upper surfaces of a plurality of adjacent second conductive pillars.

5. The method for forming a semiconductor structure according to claim 4, wherein: The central axes of the first conductive pillar and the second conductive pillar coincide with each other.

6. The method for forming a semiconductor structure according to claim 5, wherein: The shape and size of the overlapping area of ​​the opening pattern and the second conductive pillar are the same.

7. The method for forming a semiconductor structure according to claim 2, wherein: Also includes: removing the first dielectric layer; forming the dielectric layer on the outer wall and the top surface of the annular wall; The upper electrode is formed in the second opening, and the dielectric layer is located between the upper electrode and the outer wall of the annular wall.

8. A semiconductor structure, characterized in that: include: substrate; A contact pad located in a substrate, the contact pad having a protrusion protruding from a surface of the substrate A plurality of lower electrodes located on the substrate, the lower electrodes comprising an annular wall and a petal-shaped wall, the annular wall and the petal-shaped wall extending in a direction perpendicular to the surface of the substrate, and the petal-shaped wall dividing the interior of the annular wall into a plurality of discrete openings; a dielectric layer disposed on the bottom and sidewalls of the opening; an upper electrode filling the opening, wherein the dielectric layer is located between the lower electrode and the upper electrode; The lower portion of the annular wall wraps around the side wall of the protrusion.

9. The semiconductor structure according to claim 8, characterized in that The annular wall and the petal-shaped wall are made of different materials.

10. The semiconductor structure according to claim 9, wherein: The material of the annular wall includes any one of a conductive semiconductor material, a conductive polymer material or a conductive amorphous material or any combination thereof, and the material of the petal-shaped wall includes a conductive material containing a metal element.

11. The semiconductor structure according to claim 8, wherein: The plurality of lower electrodes are arranged in a honeycomb shape, and the petal-shaped wall boundaries of the openings in adjacent lower electrodes are on the same circumference.

12. The semiconductor structure according to claim 11, wherein: The petal-shaped wall divides the interior of the annular wall into three separate openings.

13. The semiconductor structure according to claim 8, wherein: The dielectric layer is also located on the top and outer wall of the annular wall and the top of the petal-shaped wall.

14. The semiconductor structure according to claim 8, wherein: A barrier layer is further included between the annular wall and the petal-shaped wall.

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