Display substrate, manufacturing method and display device

Abstract

The invention provides a display substrate, a manufacturing method and a display device. The display substrate comprises a substrate body and at least two conductive layers arranged on one side of the substrate body. The display substrate comprises a display area and a peripheral area; the display substrate further comprises a driving circuit, and the driving circuit comprises a capacitor. The capacitor is arranged in the peripheral area; the capacitor comprises a first polar plate and a second polar plate; the orthographic projection of the first polar plate on the substrate and the orthographic projection of the second polar plate on the substrate are at least partially overlapped; at least one of the first polar plate and the second polar plate is in the same layer with the conductive layer; an insulating layer is arranged between the first pole plate and the second pole plate, and the thickness of the insulating layer is smaller than a first thickness threshold value; the first thickness threshold is greater than or equal to 800 angstroms and less than or equal to 1200 angstroms. The capacitance value of a unit area of the capacitor is large, the area of the polar plate of the capacitor is reduced, and a narrow frame can be realized.

Description

Technical Field

[0001] The present invention relates to the technical field, and in particular to a display substrate, a manufacturing method and a display device. Background Art

[0002] In the related technology, as the current market demand for display panels PPI (Pixels Per Inch, pixel density) continues to increase and the borders continue to narrow, the area and size of the GOA (Gate On Array, gate drive circuit set on the array substrate) circuit are required to be further reduced. Among them, the number of TFTs (thin film transistors) and the size of the capacitor are the two main reasons that restrict the area occupied by the drive circuit. At present, there are many existing technologies for optimizing and reducing the number of TFTs, and capacitors are essential as necessary storage units of the drive circuit. In addition, at least one capacitor is required and the size must be at least a few picofarads to dozens of picofarads, that is, the area usually occupied is from 1000μm 2 To 1000000μm 2 In conventional LCD (liquid crystal display) products, the first electrode plate included in the capacitor is formed on the gate metal layer, and the second electrode plate included in the capacitor is formed on the light-shielding metal layer (the light-shielding metal layer may be formed with a light-shielding metal pattern and a data line), and two insulating layers are provided between the gate metal layer and the light-shielding metal layer: a gate insulating layer and a buffer layer; the sum of the thickness of the gate insulating layer and the thickness of the buffer layer is relatively large, and the capacitance value per unit area of ​​the capacitor is limited, and the area of ​​the electrode plate of the capacitor is required to be relatively large, so the space occupied by the capacitor is relatively large, which is not conducive to achieving a narrow frame. Summary of the invention

[0003] The main purpose of the present invention is to provide a display substrate, a manufacturing method and a display device to solve the problem in the prior art that the capacitance value per unit area of ​​the capacitor is limited, the area of ​​the capacitor plate is required to be larger, and thus the capacitor occupies a larger space, which is not conducive to achieving a narrow frame.

[0004] An embodiment of the present invention provides a display substrate, comprising a substrate and at least two conductive layers arranged on one side of the substrate, wherein the at least two conductive layers are arranged along a direction perpendicular to the one side of the substrate; the display substrate comprises a display area and a peripheral area surrounding the display area; the display substrate further comprises a driving circuit arranged on the substrate, wherein the driving circuit comprises a capacitor; the capacitor is arranged in the peripheral area; the capacitor comprises a first electrode plate and a second electrode plate; the orthographic projection of the first electrode plate on the substrate at least partially overlaps with the orthographic projection of the second electrode plate on the substrate;

[0005] At least one of the first electrode plate and the second electrode plate is in the same layer as the conductive layer; an insulating layer is provided between the first electrode plate and the second electrode plate, and the thickness of the insulating layer is less than a first thickness threshold;

[0006] The first thickness threshold is greater than or equal to 800 angstroms and less than or equal to 1200 angstroms.

[0007] Optionally, the driving circuit further includes a transistor;

[0008] The first electrode plate and the second electrode plate are located at a side of the transistor away from the substrate.

[0009] Optionally, only one insulating layer is provided between the first electrode plate and the second electrode plate.

[0010] Optionally, the first electrode plate includes at least one electrode plate portion, and the second electrode plate includes at least one electrode plate portion; the electrode plate portions included in the first electrode plate and the electrode plate portions included in the second electrode plate are alternately arranged, an insulating layer is arranged between two adjacent electrode plate portions, and the thickness of the insulating layer between two adjacent electrode plate portions is less than the first thickness threshold.

[0011] Optionally, the first electrode plate includes at least two electrode plate portions, and the at least two electrode plate portions are electrically connected to each other; and / or,

[0012] The first electrode plate includes at least two electrode plate portions, and the at least two electrode plate portions are electrically connected to each other.

[0013] Optionally, the electrodes of the transistor include a gate, a first electrode and a second electrode;

[0014] The orthographic projection of the first electrode plate on the substrate at least partially overlaps with the orthographic projection of the electrode included in the transistor on the substrate;

[0015] The orthographic projection of the first electrode plate on the substrate at least partially overlaps with the orthographic projection of the active pattern of the transistor on the substrate;

[0016] The orthographic projection of the second electrode plate on the substrate at least partially overlaps with the orthographic projection of the electrode included in the transistor on the substrate;

[0017] An orthographic projection of the second electrode plate on the substrate at least partially overlaps with an orthographic projection of the active pattern of the transistor on the substrate.

[0018] Optionally, the display substrate further includes a sub-pixel and a first electrode disposed in the display area; the sub-pixel includes a second electrode;

[0019] The first electrode plate is disposed in the same layer as the first electrode, and the second electrode plate is disposed in the same layer as the second electrode.

[0020] Optionally, the display substrate includes a first insulating layer disposed between the capacitor and the transistor;

[0021] The thickness of the first insulating layer is greater than a second thickness threshold, and the second thickness threshold is greater than or equal to 0.8 μm and less than or equal to 1.2 μm.

[0022] Optionally, the display substrate includes a first insulating layer and a second insulating layer disposed between the capacitor and the transistor; the second insulating layer is disposed between the transistor and the first insulating layer;

[0023] The first insulating layer has a groove, and the first electrode plate is directly in contact with the second insulating layer through the groove;

[0024] At least a portion of the first electrode plate and at least a portion of the second electrode plate are disposed in the groove.

[0025] Optionally, the first electrode plate includes a first electrode plate portion and a second electrode plate portion electrically connected to each other;

[0026] The second electrode plate is disposed between the first electrode plate portion and the second electrode plate portion.

[0027] Optionally, the at least two conductive layers include: a first metal layer, a second metal layer and a first conductive layer; the first conductive layer is a transparent conductive layer; the first metal layer, the second metal layer and the first conductive layer are arranged in sequence along a direction away from the substrate;

[0028] A third insulating layer is provided between the first electrode portion and the second electrode portion, and a fourth insulating layer is provided between the second electrode portion and the second electrode portion;

[0029] The first electrode portion is formed on the first metal layer, the second electrode is formed on the second metal layer, and the second electrode portion is formed on the first conductive layer.

[0030] Optionally, the display substrate further includes a data line and a first electrode arranged in the display area;

[0031] The first plate portion is disposed in the same layer as the data line, the second plate portion is disposed in the same layer as the first electrode, and the second plate portion is disposed in the same layer as the gate of the transistor.

[0032] Optionally, the first electrode plate includes a first electrode plate portion and a second electrode plate portion electrically connected to each other, and the second electrode plate includes a third electrode plate portion and a fourth electrode plate portion electrically connected to each other;

[0033] The first electrode portion, the third electrode portion, the second electrode portion, and the fourth electrode portion are sequentially arranged along a direction away from the substrate.

[0034] Optionally, the at least two conductive layers include: a first metal layer, a second metal layer, a first conductive layer, and a second conductive layer arranged in sequence in a direction away from the substrate; the first conductive layer and the second conductive layer are transparent conductive layers;

[0035] The first electrode portion is formed on the first metal layer, the second electrode portion is formed on the first conductive layer, the third electrode portion is formed on the second metal layer, and the fourth electrode portion is formed on the second conductive layer.

[0036] Optionally, the display substrate further includes a data line, a sub-pixel and a first electrode arranged in the display area; the sub-pixel includes a second electrode;

[0037] The first plate portion is disposed in the same layer as the data line, the second plate portion is disposed in the same layer as the first electrode, the third plate portion is disposed in the same layer as the gate of the transistor, and the fourth plate portion is disposed in the same layer as the second electrode.

[0038] Optionally, the capacitor is a first capacitor included in the drive circuit; the drive circuit includes an output circuit, and the output circuit is used to control the connection between the drive signal output terminal and the first clock signal line under the control of the potential of the first node; the output circuit includes a third transistor; the gate of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the first clock signal line, and the second electrode of the third transistor is electrically connected to the drive signal output terminal;

[0039] The orthographic projection of the first electrode plate of the first capacitor on the substrate at least partially overlaps with the orthographic projection of the active pattern of the third transistor on the substrate;

[0040] An orthographic projection of the second plate of the first capacitor on the substrate at least partially overlaps with an orthographic projection of the active pattern of the third transistor on the substrate.

[0041] Optionally, the capacitor is a second capacitor included in the driving circuit; the driving circuit includes an output reset circuit and a second node reset circuit; the output reset circuit includes a fourth transistor; and the second node reset circuit includes an eighth transistor;

[0042] The output reset circuit is electrically connected to the second node, the drive signal output terminal and the low voltage line respectively, and is used to control the connection between the drive signal output terminal and the low voltage line under the control of the potential of the second node;

[0043] The second node reset circuit is electrically connected to the second node, the drive signal output terminal and the low voltage line respectively, and is used to control the second node to be connected to the low voltage line under the control of the drive signal provided by the drive signal output terminal;

[0044] The gate of the fourth transistor is electrically connected to the second node, the first electrode of the fourth transistor is electrically connected to the drive signal output terminal, and the second electrode of the fourth transistor is electrically connected to the low voltage line;

[0045] The gate of the eighth transistor is electrically connected to the driving signal output terminal, the first electrode of the eighth transistor is electrically connected to the second node, and the second electrode of the eighth transistor is electrically connected to the low voltage line;

[0046] The orthographic projection of the first electrode plate of the second capacitor on the substrate at least partially overlaps with the orthographic projection of the active pattern of the fourth transistor on the substrate;

[0047] The orthographic projection of the second electrode plate of the second capacitor on the substrate at least partially overlaps with the orthographic projection of the active pattern of the fourth transistor on the substrate;

[0048] The orthographic projection of the first electrode plate of the second capacitor on the substrate at least partially overlaps with the orthographic projection of the active pattern of the eighth transistor on the substrate;

[0049] An orthographic projection of the second plate of the second capacitor on the substrate at least partially overlaps with an orthographic projection of the active pattern of the eighth transistor on the substrate.

[0050] An embodiment of the present invention further provides a method for manufacturing a display substrate, which is applied to the above-mentioned display substrate. The method for manufacturing the display substrate includes:

[0051] At least two conductive layers are formed on one side of the substrate; the at least two conductive layers are arranged along a direction perpendicular to the one side of the substrate;

[0052] Performing a patterning process on at least one of the at least two conductive layers to form at least one plate portion included in the first plate; performing a patterning process on at least one of the at least two conductive layers except the at least one conductive layer to form at least one plate portion included in the second plate; and controlling the plate portions included in the first plate and the plate portions included in the second plate to be alternately arranged;

[0053] An insulating layer is provided between two adjacent electrode plates, and a thickness of the insulating layer is set to be less than a first thickness threshold;

[0054] The first thickness threshold is greater than or equal to 800 angstroms and less than or equal to 1200 angstroms.

[0055] Optionally, the method for manufacturing the display substrate includes:

[0056] Manufacturing a light-shielding metal layer on the substrate, and patterning the light-shielding metal layer to form a first electrode portion included in the first electrode plate;

[0057] A buffer layer, a semiconductor layer and a gate insulating layer are sequentially formed on a side of the light-shielding metal layer away from the substrate;

[0058] Coating a photoresist on a side of the gate insulating layer away from the substrate, and exposing the display substrate coated with the photoresist using a mask, wherein the mask includes a semi-transparent area and an opaque area;

[0059] Etching the exposed display substrate to remove the residual photoresist, wherein the gate insulating layer is etched away in the semi-transparent area;

[0060] Making a first connecting via hole penetrating the gate insulating layer and the buffer layer;

[0061] A gate metal layer is formed on a side of the gate insulating layer away from the substrate, and a patterning process is performed on the gate metal layer to form a third electrode portion included in the second electrode plate;

[0062] Sequentially forming a second passivation layer and an organic layer on a side of the gate metal layer away from the substrate;

[0063] Performing a drilling operation on the organic layer to form a second connecting via hole penetrating the organic layer;

[0064] forming a first electrode layer on a side of the organic layer away from the substrate, performing a patterning process on the first electrode layer to form a second electrode portion included in the first electrode plate, and making the second electrode portion directly contact the second passivation layer through the second connecting via hole;

[0065] Forming a first passivation layer on a side of the first electrode layer away from the substrate, and forming a third connection via hole penetrating the first passivation layer and a fourth connection via hole penetrating the first passivation layer and the second passivation layer;

[0066] A second electrode layer is formed on a side of the first passivation layer away from the substrate, and a patterning process is performed on the second electrode layer to form a conductive connection portion, so that the conductive connection portion is electrically connected to the second electrode portion through the third connection via hole, and the conductive connection portion is electrically connected to the first electrode portion through the second connection via hole and the fourth connection via hole;

[0067] The first electrode layer and the second electrode layer are made of metal oxide.

[0068] Optionally, the manufacturing method described in the embodiment of the present invention further includes:

[0069] While making a fourth connection via hole penetrating the first passivation layer and the second passivation layer, making a fifth connection via hole penetrating the first passivation layer and the second passivation layer;

[0070] While the second electrode layer is patterned to form the conductive connection portion, the fourth electrode portion included in the second electrode is formed, and the fourth electrode portion is electrically connected to the third electrode portion through the fifth connection via.

[0071] An embodiment of the present invention provides a display device, including the above-mentioned display substrate.

[0072] In the embodiment of the present invention, the thickness of the insulating layer between two adjacent plates is set to be relatively small, so that the capacitance value per unit area of ​​the capacitor is relatively large, the area of ​​the plates of the capacitor is reduced, and a narrow frame is achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0073] Figure 1A , Figure 1B is a cross-sectional view of a display substrate according to at least one embodiment of the present invention;

[0074] Figure 2 is a circuit diagram of at least one embodiment of a drive circuit;

[0075] Figure 3 yes Figure 2 At least a partial layout diagram of at least one embodiment of the driving circuit shown;

[0076] Figure 4 yes Figure 3 A layout diagram of a semiconductor layer in FIG.

[0077] Figure 5 yes Figure 3 A layout diagram of the gate metal layer in FIG.

[0078] Figure 6 yes Figure 3 Layout diagram of source and drain metal layers in FIG.

[0079] Figure 7 yes Figure 5 A layout diagram of a first conductive layer in;

[0080] Figure 8 yes Figure 5 A layout diagram of a second conductive layer in;

[0081] Fig.9A yes Figure 3 A layout diagram of the first capacitor C1 in FIG.

[0082] Fig. 9B and Fig. 9C yes Fig.9A A-A' cross-section diagram;

[0083] Fig.10 yes Fig.9A A layout diagram of a semiconductor layer in FIG.

[0084] Fig.11 yes Fig.9A A layout diagram of the gate metal layer in FIG.

[0085] Fig.12 yes Fig.9A Layout diagram of source and drain metal layers in FIG.

[0086] Fig.13 yes Fig.9A A layout diagram of a first conductive layer in;

[0087] Fig.14 yes Fig.9A A layout diagram of a second conductive layer in FIG.

[0088] Fig.15 yes Figure 3 A layout diagram of the second capacitor C2 in FIG.

[0089] Fig.16 yes Fig.15 A layout diagram of a semiconductor layer in FIG.

[0090] Fig.17 yes Fig.15 A layout diagram of the gate metal layer in FIG.

[0091] Fig.18 yes Fig.15 Layout diagram of source and drain metal layers in FIG.

[0092] Fig.19 yes Fig.15 A layout diagram of a first conductive layer in;

[0093] Fig. 20 yes Fig.15 A layout diagram of a second conductive layer in FIG.

[0094] Fig.21A , Fig.21B is a cross-sectional view of a display substrate according to at least one embodiment of the present invention;

[0095] Fig. 22 It includes Fig.21A A cross-sectional view of a substrate 10, a light-shielding metal layer 11, a buffer layer 12, a semiconductor layer 13, a gate insulating layer 14, a gate metal layer 15, a first passivation layer 16 and an organic layer 17;

[0096] Fig.23A , Fig. 23Bis a cross-sectional view of a display substrate according to at least one embodiment of the present invention;

[0097] Fig.23C In making Fig.23A , Fig. 23B In at least one embodiment of the display substrate shown in FIG. 1 , after a light-shielding metal layer 11, a buffer layer 12, a semiconductor layer 13 and a gate insulating layer 14 are sequentially formed on a substrate 10, a PR glue (photoresist) 230 is coated on a side of the gate insulating layer 14 away from the substrate 10, and exposure is performed through a mask MK;

[0098] Fig.24 It is a schematic diagram of providing a photoresist after sequentially forming a light-shielding metal layer 11, a buffer layer 12, a semiconductor layer 13 and a gate insulating layer 14 on a substrate 10;

[0099] Fig.25 is to Fig.24 The structure diagram of the display substrate after the display substrate is etched;

[0100] Fig.26 is the equivalent circuit diagram of a capacitor;

[0101] Fig.27A , Fig.27B is a cross-sectional view of a display substrate according to at least one embodiment of the present invention;

[0102] Fig.28 It is the equivalent circuit diagram of a capacitor. DETAILED DESCRIPTION

[0103] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0104] The terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0105] In this specification, for the sake of convenience, the words and phrases indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which the constituent elements are described. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately replaced according to the situation.

[0106] In this specification, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the meanings of the above terms in this disclosure can be understood according to the circumstances.

[0107] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. The term "coupled" indicates, for example, that two or more components are in direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0108] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within the acceptable deviation range, wherein the acceptable deviation range is determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, the difference between the two equalities is less than or equal to 10% of either one.

[0109] It will be understood that when a layer or an element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present between the layer or element and the other layer or substrate.

[0110] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of the layers and the area of ​​the regions are exaggerated for clarity. Therefore, variations in the shapes relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shapes of the regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0111] In this specification, circles, triangles, rectangles, trapezoids, pentagons or hexagons are not strictly defined, but may be approximate circles, triangles, rectangles, trapezoids, pentagons or hexagons, etc., and may have some small deformations caused by tolerances, and may have chamfers, arc edges and deformations. The transistors used in all embodiments of the present invention may be thin film transistors or field effect transistors or other devices with the same characteristics. In the embodiments of the present invention, in order to distinguish the two poles of the transistor except the gate, one of the poles is called the first pole and the other pole is called the second pole.

[0112] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

[0113] The display substrate of the embodiment of the present invention comprises a substrate and at least two conductive layers arranged on one side of the substrate, wherein the at least two conductive layers are arranged in a direction perpendicular to the one side of the substrate; the display substrate comprises a display area and a peripheral area surrounding the display area; the display substrate further comprises a driving circuit arranged on the substrate, wherein the driving circuit comprises a capacitor; and the capacitor is arranged in the peripheral area;

[0114] The capacitor comprises a first electrode plate and a second electrode plate; the orthographic projection of the first electrode plate on the substrate at least partially overlaps with the orthographic projection of the second electrode plate on the substrate;

[0115] At least one of the first electrode plate and the second electrode plate is in the same layer as the conductive layer; an insulating layer is provided between the first electrode plate and the second electrode plate, and the thickness of the insulating layer is less than a first thickness threshold;

[0116] The first thickness threshold is greater than or equal to 800 angstroms and less than or equal to 1200 angstroms.

[0117] In the related technology, as the current market demand for display panels PPI (Pixels Per Inch, pixel density) continues to increase and the borders continue to narrow, the area and size of the GOA (Gate On Array, gate drive circuit set on the array substrate) circuit are required to be further reduced. Among them, the number of TFTs (thin film transistors) and the size of the capacitor are the two main reasons that restrict the area occupied by the drive circuit. At present, there are many existing technologies for optimizing and reducing the number of TFTs, and capacitors are essential as necessary storage units of the drive circuit. In addition, at least one capacitor is required and the size must be at least a few picofarads to dozens of picofarads, that is, the area usually occupied is from 1000μm 2 To 1000000μm 2 In conventional LCD (liquid crystal display) products, the first electrode plate included in the capacitor is formed on the gate metal layer, and the second electrode plate included in the capacitor is formed on the light-shielding metal layer (the light-shielding metal layer may be formed with a light-shielding metal pattern and a data line), and two insulating layers are provided between the gate metal layer and the light-shielding metal layer: a gate insulating layer and a buffer layer; the sum of the thickness of the gate insulating layer and the thickness of the buffer layer is relatively large, and the capacitance value per unit area of ​​the capacitor is limited, and the area of ​​the electrode plate of the capacitor is required to be relatively large, so the space occupied by the capacitor is relatively large, which is not conducive to achieving a narrow frame.

[0118] Based on the above problems, in the display substrate described in the embodiment of the present invention, the capacitor includes a first electrode plate and a second electrode plate; the thickness of the insulating layer between the first electrode plate and the second electrode plate is less than a first thickness threshold, so that the capacitance value per unit area of ​​the capacitor is larger, reducing the area of ​​the electrode plate of the capacitor, which is conducive to achieving a narrow frame.

[0119] In at least one embodiment of the present invention, the first thickness threshold is greater than or equal to 800 angstroms and less than or equal to 1200 angstroms;

[0120] When the thickness of the insulating layer between the first electrode plate and the second electrode plate is too small, the insulating layer cannot play the role of a dielectric layer, and electrical connection is easily caused between the first electrode plate and the second electrode plate; when the thickness of the insulating layer between the first electrode plate and the second electrode plate is too large, the capacitance value per unit area of ​​the capacitor is small, and the electrode area of ​​the capacitor needs to be increased to achieve a larger capacitance value; therefore, the first thickness threshold needs to be set to be greater than or equal to 800 angstroms and less than or equal to 1200 angstroms. Within this thickness range, the dielectric constant of the insulating layer is relatively appropriate, which is conducive to forming a stable capacitor electric field.

[0121] In at least one embodiment of the present invention, the driving circuit further includes a transistor;

[0122] The first electrode plate and the second electrode plate are located at a side of the transistor away from the substrate.

[0123] In a specific implementation, the capacitor can be arranged on a side of the transistor included in the driving circuit away from the substrate, and the capacitor can be arranged above the transistor to realize a stacked design of the transistor and the capacitor, saving the design space of the driving circuit. The conductive layer where the capacitor's plate is located can also be used as a bridge trace between some transistors. At the same time, since there is a thicker organic layer between the capacitor and the transistor, the parasitic coupling added after the overlapping design is small and will not affect the performance of the driving circuit.

[0124] In at least one embodiment of the present invention, only one insulating layer is disposed between the first electrode plate and the second electrode plate.

[0125] In a specific implementation, only one insulating layer may be disposed between the first electrode plate and the second electrode plate to reduce the thickness of the insulating layer between the first electrode plate and the second electrode plate.

[0126] In at least one embodiment of the present invention, the first electrode plate may include at least one electrode plate portion, and the second electrode plate may include at least one electrode plate portion; the electrode plate portions included in the first electrode plate and the electrode plate portions included in the second electrode plate are alternately arranged, an insulating layer is arranged between two adjacent electrode plate portions, and the thickness of the insulating layer between two adjacent electrode plate portions is less than the first thickness threshold.

[0127] Optionally, the electrode portion of the capacitor which is farthest from the substrate may be formed in the transparent conductive layer.

[0128] For example, the transparent conductive layer may be an ITO (indium tin oxide) layer, but is not limited thereto.

[0129] In the related art, since the gate metal layer and the shading metal layer are both metal layers, in a display product with a narrow frame, due to the narrow frame, the frame sealant overlaps with the driving circuit area. Since the color film layer is blocked by BM (black matrix), UV (ultraviolet) irradiation is required on the TFT side to solidify the frame sealant. In order to ensure the light transmittance on the TFT side, the capacitor needs to be hollowed out. At this time, the area of ​​the capacitor plate becomes further larger, which is not conducive to the reduction in the size of the driving circuit. Based on this, at least one embodiment of the present invention sets the plate farthest from the substrate included in the capacitor to be formed on the transparent conductive layer to ensure the light transmittance on the TFT side, so that the capacitor plate does not need to be hollowed out, and the area of ​​the capacitor plate does not need to be increased, which is conducive to achieving a narrow frame.

[0130] Optionally, the first electrode plate includes at least two electrode plate portions, and the at least two electrode plate portions are electrically connected to each other; and / or,

[0131] The first electrode plate includes at least two electrode plate portions, and the at least two electrode plate portions are electrically connected to each other.

[0132] In at least one embodiment of the present invention, the capacitor may be arranged on a side of a transistor included in the driving circuit that is away from the substrate; the electrode of the transistor may include a gate, a first electrode, and a second electrode;

[0133] The orthographic projection of the first electrode plate on the substrate at least partially overlaps with the orthographic projection of the electrode included in the transistor on the substrate;

[0134] The orthographic projection of the first electrode plate on the substrate at least partially overlaps with the orthographic projection of the active pattern of the transistor on the substrate;

[0135] The orthographic projection of the second electrode plate on the substrate at least partially overlaps with the orthographic projection of the electrode included in the transistor on the substrate;

[0136] An orthographic projection of the second electrode plate on the substrate at least partially overlaps with an orthographic projection of the active pattern of the transistor on the substrate.

[0137] In a specific implementation, the capacitor can be arranged on a side of the transistor included in the driving circuit away from the substrate, and the capacitor can be arranged above the transistor to realize a stacked design of the transistor and the capacitor, saving the design space of the driving circuit. The conductive layer where the capacitor's plate is located can also be used as a bridge trace between some transistors. At the same time, since there is a thicker organic layer between the capacitor and the transistor, the parasitic coupling added after the overlapping design is small and will not affect the performance of the driving circuit.

[0138] In at least one embodiment of the present invention, the display substrate further includes a display area, and the display substrate further includes a sub-pixel and a first electrode disposed in the display area; the sub-pixel includes a second electrode;

[0139] The first electrode plate is disposed in the same layer as the first electrode, and the second electrode plate is disposed in the same layer as the second electrode.

[0140] Optionally, the first electrode may be a common electrode, and the second electrode may be a pixel electrode, but is not limited thereto.

[0141] In a specific implementation, the first electrode plate can be arranged in the same layer as the first electrode, and the second electrode plate can be arranged in the same layer as the second electrode. Further, the first electrode plate can be made of the same material as the first electrode, and the second electrode plate can be made of the same material as the second electrode, which can further optimize the preparation process, reduce costs and improve preparation stability.

[0142] Optionally, the display substrate includes a first insulating layer disposed between the capacitor and the transistor;

[0143] The thickness of the first insulating layer is greater than a second thickness threshold, and the second thickness threshold is greater than or equal to 0.8 μm and less than or equal to 1.2 μm.

[0144] Optionally, the first insulating layer may be an organic layer.

[0145] In a specific implementation, the thickness of the organic layer disposed between the capacitor and the transistor is set to be relatively large, so that the parasitic coupling increased by the overlapping design is relatively small and does not affect the performance of the driving circuit.

[0146] like Figure 1A As shown, numeral 10 is a substrate, numeral 11 is a shading metal layer, numeral 12 is a buffer layer, numeral 13 is a semiconductor layer, numeral 14 is a gate insulating layer, numeral 15 is a gate metal layer, numeral 16 is a first passivation layer, numeral 17 is an organic layer, numeral 18 is a first conductive layer, numeral 19 is a second passivation layer, and numeral 110 is a second conductive layer.

[0147] exist Figure 1A and Figure 1B In the figure, the area labeled A1 is the peripheral area, which includes the driving circuit, and the area labeled A2 is the display area;

[0148] In the display area A2, the first conductive layer 18 includes a common electrode CM, and the second conductive layer 110 includes a pixel electrode PX;

[0149] exist Figure 1A and Figure 1B middle,

[0150] The transistors labeled T0 are in the driving circuit, and the transistors labeled TD are in the display area A2;

[0151] The first plate of the capacitor is labeled J1, and the second plate of the capacitor is labeled J2; the first plate J1 is disposed on the same layer as the common electrode CM, and the second plate J2 is disposed on the same layer as the pixel electrode PX;

[0152] The gate electrode of the transistor T0 in the driving circuit is labeled G0, the first electrode of the transistor T0 in the driving circuit is labeled S0, and the second electrode of the transistor T0 in the driving circuit is labeled D0;

[0153] The active pattern labeled A0 is T0;

[0154] The orthographic projection of J1 on the base at least partially overlaps with the orthographic projection of G0 on the base;

[0155] The orthographic projection of J1 on the base at least partially overlaps with the orthographic projection of S0 on the base;

[0156] The orthographic projection of J1 on the base at least partially overlaps with the orthographic projection of D0 on the base;

[0157] The orthographic projection of J1 on the base at least partially overlaps with the orthographic projection of A0 on the base;

[0158] The orthographic projection of J2 on the base at least partially overlaps with the orthographic projection of G0 on the base;

[0159] The orthographic projection of J2 on the base at least partially overlaps with the orthographic projection of S0 on the base;

[0160] The orthographic projection of J2 on the base at least partially overlaps with the orthographic projection of D0 on the base;

[0161] The orthographic projection of J2 on the substrate at least partially overlaps with the orthographic projection of A0 on the substrate.

[0162] exist Figure 1A , Figure 1B In at least one embodiment shown, a second passivation layer 19 is disposed between J1 and J2, and the second passivation layer 19 is relatively thin, so that the capacitance per unit area of ​​the capacitor is relatively large, and the area of ​​the capacitor plate is reduced, which is conducive to achieving a narrow frame;

[0163] The orthographic projection of J1 on the base and the orthographic projection of J2 on the base at least partially overlap.

[0164] like Figure 1A and Figure 1B As shown, the second electrode plate J2 is electrically connected to the conductive pattern formed on the gate metal layer through a via hole penetrating the second passivation layer, the organic layer and the first passivation layer.

[0165] In at least one embodiment of the present invention, the first electrode J1 can be disposed in the same layer as the common electrode CM, and the second electrode J2 can be disposed in the same layer as the pixel electrode PX. Further, the first electrode J1 can be made of the same material as the common electrode CM, and the second electrode J2 can be made of the same material as the pixel electrode PX, which can further optimize the manufacturing process, reduce costs, and improve manufacturing stability.

[0166] In at least one embodiment of the present invention, at least one embodiment of the driving circuit may include an output circuit, an output reset circuit, a first node control circuit, a second node control circuit, a second node reset circuit, an enable circuit, a first energy storage circuit, and a second energy storage circuit;

[0167] The output circuit is electrically connected to the first node, the drive signal output terminal and the first clock signal line respectively, and is used to control the connection between the drive signal output terminal and the first clock signal line under the control of the potential of the first node;

[0168] The output reset circuit is electrically connected to the second node, the drive signal output terminal and the low voltage line respectively, and is used to control the connection between the drive signal output terminal and the low voltage line under the control of the potential of the second node;

[0169] The second node reset circuit is electrically connected to the second node, the drive signal output terminal and the low voltage line respectively, and is used to control the second node to be connected to the low voltage line under the control of the drive signal provided by the drive signal output terminal;

[0170] The first node control circuit is electrically connected to the first node, the input terminal, the reset terminal, the first scanning voltage line, the second scanning voltage line, the second node, the low voltage line and the reset signal line respectively, and is used to control the first node to be connected to the first scanning voltage line under the control of the input signal provided by the input terminal, control the first node to be connected to the second scanning voltage line under the control of the reset voltage signal provided by the reset terminal, control the first node to be connected to the low voltage line under the control of the potential of the second node, and control the first node to be connected to the low voltage line under the control of the reset voltage signal provided by the reset signal line;

[0171] The second node control circuit is electrically connected to the second clock signal line, the second node, the first node and the low voltage line respectively, and is used to control the potential of the second node under the control of the second clock signal provided by the second clock signal line, and control the connection between the second node and the low voltage line under the control of the potential of the first node;

[0172] The enable circuit is electrically connected to the enable line, the second node, the drive signal output terminal and the low voltage line respectively, and is used to control the drive signal provided by the drive signal output terminal under the control of the enable signal provided by the enable line, and control the connection between the second node and the low voltage line under the control of the enable signal.

[0173] Optionally, the first node control circuit includes a first transistor, a second transistor, a fifth transistor and an eleventh transistor; the output circuit may include a third transistor, and the output reset circuit may include a fourth transistor; the second node reset circuit may include an eighth transistor; the second node control circuit may include a sixth transistor and a seventh transistor; the enable circuit includes a ninth transistor and a tenth transistor; the first energy storage circuit includes a first capacitor, and the second energy storage circuit includes a second capacitor;

[0174] The gate of the first transistor is electrically connected to the input terminal, the first electrode of the first transistor is electrically connected to the first scanning voltage line, and the second electrode of the first transistor is electrically connected to the first node;

[0175] The gate of the second transistor is electrically connected to the reset terminal, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the second scanning voltage line;

[0176] The gate of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the first clock signal line, and the second electrode of the third transistor is electrically connected to the drive signal output terminal;

[0177] The gate of the fourth transistor is electrically connected to the second node, the first electrode of the fourth transistor is electrically connected to the drive signal output terminal, and the second electrode of the fourth transistor is electrically connected to the low voltage line;

[0178] The gate of the fifth transistor is electrically connected to the second node, the first electrode of the fifth transistor is electrically connected to the first node, and the second electrode of the fifth transistor is electrically connected to the low voltage line;

[0179] The gate of the sixth transistor is electrically connected to the first node, the first electrode of the sixth transistor is electrically connected to the second node, and the second electrode of the sixth transistor is electrically connected to the low voltage line;

[0180] The gate of the seventh transistor and the first electrode of the seventh transistor are both electrically connected to the second clock signal line, and the second electrode of the seventh transistor is electrically connected to the second node;

[0181] The gate of the eighth transistor is electrically connected to the driving signal output terminal, the first electrode of the eighth transistor is electrically connected to the second node, and the second electrode of the eighth transistor is electrically connected to the low voltage line;

[0182] The gate electrode of the ninth transistor and the second electrode of the ninth transistor are both electrically connected to the enable line, and the first electrode of the ninth transistor is electrically connected to the drive signal output terminal;

[0183] The gate of the tenth transistor is electrically connected to the enable line, the first electrode of the tenth transistor is electrically connected to the second node, and the second electrode of the tenth transistor is electrically connected to the low voltage line;

[0184] The gate of the eleventh transistor is electrically connected to the reset signal line, the first electrode of the eleventh transistor is electrically connected to the first node, and the second electrode of the eleventh transistor is electrically connected to the low voltage line;

[0185] The first plate of the first capacitor is electrically connected to the first node, and the second plate of the first capacitor is electrically connected to the drive signal output terminal;

[0186] The first plate of the second capacitor is electrically connected to the second node, and the second plate of the second capacitor is electrically connected to the low voltage line.

[0187] Figure 2 is a circuit diagram of at least one embodiment of a drive circuit. Figure 2 As shown, at least one embodiment of the driving circuit includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a first capacitor C1 and a second capacitor C2;

[0188] The gate of T1 is electrically connected to the input terminal I1, the source of T1 is electrically connected to the first scanning voltage line CN, and the drain of T1 is electrically connected to the source of T2;

[0189] The gate of T2 is electrically connected to the reset terminal R1, and the drain of T2 is electrically connected to the second scanning voltage line CNB;

[0190] The gate of T3 is electrically connected to the drain of T1, the source of T3 is electrically connected to the first clock signal line CLK, the drain of T3 is electrically connected to the drive signal output terminal OT; the gate of T3 is electrically connected to the first node PU;

[0191] The gate of T4 is electrically connected to the gate of T5, the source of T4 is electrically connected to the driving signal output terminal OT, the drain of T4 is electrically connected to the low voltage line VGL; the gate of T4 is electrically connected to the second node PD;

[0192] The first electrode plate of C2 is electrically connected to the gate of T4; the second electrode plate of C2 is electrically connected to the low voltage line VGL;

[0193] The gate of T5 is electrically connected to the drain of T7, the source of T5 is electrically connected to the gate of T3, and the drain of T5 is electrically connected to the low voltage line VGL;

[0194] The gate of T6 is electrically connected to the gate of T3, the source of T6 is electrically connected to the gate of T4, and the drain of T6 is electrically connected to the low voltage line VGL;

[0195] The gate of T7 and the source of T7 are electrically connected to the second clock signal line CLKB;

[0196] The gate of T8 is electrically connected to the driving signal output terminal OT, the source of T8 is electrically connected to the gate of T4, and the drain of T8 is electrically connected to the low voltage line VGL;

[0197] The gate of T9 and the drain of T9 are electrically connected to the enable line EN, and the source of T9 is electrically connected to the drive signal output terminal OT;

[0198] The gate of T10 is electrically connected to the enable line EN, the source of T10 is electrically connected to the gate of T4, and the drain of T10 is electrically connected to the low voltage line VGL;

[0199] The gate of T11 is electrically connected to the reset signal line RST, the source of T11 is electrically connected to the gate of T3, and the drain of T11 is electrically connected to the low voltage line VGL;

[0200] The first electrode plate of C1 is electrically connected to the gate of T3, and the second electrode plate of C1 is electrically connected to the driving signal output terminal OT.

[0201] exist Figure 2 In at least one embodiment shown, the capacitor in the driving circuit includes: a first capacitor C1 and a second capacitor C2.

[0202] Figure 3 yes Figure 2 A layout diagram of at least a portion of at least one embodiment of a driver circuit is shown.

[0203] exist Figure 3 In the figure, the line labeled CN is the first scanning voltage line; the line labeled CNB is the second scanning voltage line, the line labeled RST is the reset signal line, the line labeled VGL1 is the first low voltage line, the line labeled CLK is the first clock signal line, the line labeled CLKB is the second clock signal line, the line labeled VGL2 is the second low voltage line, and the line labeled EN is the enable line;

[0204] The capacitor labeled C1 is the first capacitor, and the capacitor labeled C2 is the second capacitor;

[0205] C1 is disposed on a side of T3 away from the substrate, and C2 is disposed on a side of T4 and T8 away from the substrate.

[0206] Figure 4 yes Figure 3 The layout of the semiconductor layers in Figure 5 yes Figure 3 The layout diagram of the gate metal layer in Figure 6 yes Figure 3 Layout diagram of source and drain metal layers in Figure 7 yes Figure 5 Layout diagram of the first conductive layer in Figure 8 yes Figure 5 Layout diagram of the second conductive layer in .

[0207] exist Figure 7 , the first electrode plate labeled C2a is C2, and the first electrode plate labeled C1a is C1;

[0208] exist Figure 8 In the figure, the plate labeled C2b is the second plate of C2, and the plate labeled C1b is the first plate of C1.

[0209] exist Figure 4 , the active pattern labeled A3 is T3, the active pattern labeled A4 is T4, and the active pattern labeled A8 is T8;

[0210] The orthographic projection of C1a on the base partially overlaps with the orthographic projection of A3 on the base, and the orthographic projection of C1b on the base partially overlaps with the orthographic projection of A3 on the base;

[0211] The orthographic projection of C2a on the base partially overlaps with the orthographic projection of A4 on the base, and the orthographic projection of C2b on the base partially overlaps with the orthographic projection of A4 on the base;

[0212] The orthographic projection of C2a on the substrate partially overlaps with the orthographic projection of A8 on the substrate, and the orthographic projection of C2b on the substrate partially overlaps with the orthographic projection of A8 on the substrate.

[0213] exist Figure 5 , the one labeled G3 is the gate of T3, the one labeled G4 is the gate of T4, and the one labeled G8 is the gate of T8.

[0214] exist Figure 6 , S3 is the first pole of T3, D3 is the second pole of T3, S4 is the first pole of T4, D4 is the second pole of T4, S8 is the first pole of T8, and D8 is the second pole of T8.

[0215] In a specific implementation, the first electrode may be a source electrode, and the second electrode may be a drain electrode, or the first electrode may be a drain electrode, and the second electrode may be a source electrode.

[0216] Fig.9A yes Figure 3 Layout diagram of the first capacitor C1 in FIG. Fig. 9B and Fig. 9C yes Fig.9A A-A' cross-section diagram.

[0217] like Fig. 9B As shown, numeral 10 is a substrate, numeral 13 is a semiconductor layer, numeral 14 is a gate insulating layer, numeral 15 is a gate metal layer, numeral 16 is a first passivation layer, numeral 17 is an organic layer, numeral 18 is a first conductive layer, numeral 19 is a second passivation layer, and numeral 110 is a second conductive layer.

[0218] exist Fig. 9CIn the figure, the first electrode plate of C1 is labeled C1a, the second electrode plate of C1 is labeled C1b, and the third transistor is labeled T3.

[0219] Fig.10 yes Fig.9A The layout of the semiconductor layers in Fig.11 yes Fig.9A The layout diagram of the gate metal layer in Fig.12 yes Fig.9A Layout diagram of source and drain metal layers in Fig.13 yes Fig.9A Layout diagram of the first conductive layer in Fig.14 yes Fig.9A Layout diagram of the second conductive layer in .

[0220] exist Fig.10 Among them, the one labeled A3 is the active pattern of T3.

[0221] exist Fig.11 In the figure, the one labeled G3 is the gate of T3.

[0222] exist Fig.12 In the figure, the first pole of T3 is labeled S3, and the second pole of T3 is labeled D3.

[0223] exist Fig.13 In the figure, the first plate of C1, labeled C1a, is Fig.14 Among them, the one labeled C1b is the second electrode plate of C1.

[0224] Fig.15 yes Figure 3 Layout diagram of the second capacitor C2 in FIG.

[0225] Fig.16 yes Fig.15 The layout of the semiconductor layers in Fig.17 yes Fig.15 The layout diagram of the gate metal layer in Fig.18 yes Fig.15 Layout diagram of source and drain metal layers in Fig.19 yes Fig.15 Layout diagram of the first conductive layer in Fig. 20 yes Fig.15 Layout diagram of the second conductive layer in .

[0226] exist Fig.16 Among them, the one labeled A4 is the active pattern of T4, and the one labeled A8 is the active pattern of T8.

[0227] exist Fig.17 , the gate labeled G4 is the gate of T4, and the gate labeled G8 is the gate of T8.

[0228] exist Fig.18Among them, the one labeled S4 is the first pole of T4, the one labeled D4 is the second pole of T4, the one labeled S8 is the first pole of T8, and the one labeled D8 is the second pole of T8.

[0229] exist Fig.19 In the embodiment, the first electrode plate of C2, labeled C2a, is Fig. 20 Among them, the one labeled C2b is the second electrode plate of C2.

[0230] In at least one embodiment of the present invention, the display substrate includes a first insulating layer and a second insulating layer disposed between the capacitor and the transistor; the second insulating layer is disposed between the transistor and the first insulating layer;

[0231] The first insulating layer has a groove, and the first electrode plate is directly in contact with the second insulating layer through the groove;

[0232] At least a portion of the first electrode plate and at least a portion of the second electrode plate are disposed in the groove.

[0233] Optionally, the first insulating layer may be an organic layer, and the second insulating layer may be a first passivation layer.

[0234] In a specific implementation, the organic layer may be provided with a groove, the first electrode plate directly contacts the second insulating layer through the groove, and at least a portion of the first electrode plate and at least a portion of the second electrode plate are provided in the groove.

[0235] In order to increase the capacitance value per unit area and further reduce the area occupied by the capacitor, the organic layer can be designed with grooves or holes. After adding the groove structure design, the overlapping area of ​​the first electrode plate and the second electrode plate in the same plane space can be further increased, thereby achieving the effect of occupying a small area and forming a large capacitance value of the capacitor.

[0236] like Fig.21A As shown, numeral 10 is a substrate, numeral 11 is a shading metal layer, numeral 12 is a buffer layer, numeral 13 is a semiconductor layer, numeral 14 is a gate insulating layer, numeral 15 is a gate metal layer, numeral 16 is a first passivation layer, numeral 17 is an organic layer, numeral 18 is a first conductive layer, numeral 19 is a second passivation layer, and numeral 110 is a second conductive layer.

[0237] exist Fig.21A and Fig.21B middle,

[0238] The area labeled A1 is the peripheral area, and the area labeled A2 is the display area;

[0239] In the display area A2, the first conductive layer 18 includes a common electrode CM, and the second conductive layer 110 includes a pixel electrode PX;

[0240] The transistors labeled T0 are in the driving circuit, and the transistors labeled TD are in the display area A2;

[0241] The first plate of the capacitor is labeled J1, and the second plate of the capacitor is labeled J2;

[0242] The gate electrode of the transistor in the driving circuit is labeled G0, the first electrode of the transistor in the driving circuit is labeled S0, and the second electrode of the transistor in the driving circuit is labeled D0;

[0243] The active pattern labeled A0 is T0;

[0244] The orthographic projection of J1 on the base at least partially overlaps with the orthographic projection of G0 on the base;

[0245] The orthographic projection of J1 on the base at least partially overlaps with the orthographic projection of S0 on the base;

[0246] The orthographic projection of J1 on the base at least partially overlaps with the orthographic projection of D0 on the base;

[0247] The orthographic projection of J1 on the base at least partially overlaps with the orthographic projection of A0 on the base;

[0248] The orthographic projection of J2 on the base at least partially overlaps with the orthographic projection of G0 on the base;

[0249] The orthographic projection of J2 on the base at least partially overlaps with the orthographic projection of S0 on the base;

[0250] The orthographic projection of J2 on the base at least partially overlaps with the orthographic projection of D0 on the base;

[0251] The orthographic projection of J2 on the substrate at least partially overlaps with the orthographic projection of A0 on the substrate.

[0252] exist Fig.21A , Fig.21B In at least one embodiment shown, a second passivation layer 19 is disposed between J1 and J2, and the second passivation layer 19 is relatively thin, so that the capacitance per unit area of ​​the capacitor is relatively large, and the area of ​​the capacitor plate is reduced, which is conducive to achieving a narrow frame;

[0253] The orthographic projection of J1 on the base and the orthographic projection of J2 on the base at least partially overlap.

[0254] exist Fig.21A , Fig.21BIn at least one embodiment shown, the organic layer 17 has two grooves, so that a portion of the first electrode plate and a portion of the second electrode plate are sunken, thereby increasing the overlapping space between the first electrode plate and the second electrode plate.

[0255] Fig. 22 It includes Fig.21A A cross-sectional view of a substrate 10, a light-shielding metal layer 11, a buffer layer 12, a semiconductor layer 13, a gate insulating layer 14, a gate metal layer 15, a first passivation layer 16 and an organic layer 17;

[0256] exist Fig. 22 In the figure, the groove labeled GC1 is the first groove, and the groove labeled GC2 is the second groove.

[0257] Optionally, the first electrode plate includes a first electrode plate portion and a second electrode plate portion electrically connected to each other;

[0258] The second electrode plate is disposed between the first electrode plate portion and the second electrode plate portion.

[0259] In at least one embodiment of the present invention, the at least two conductive layers include: a first metal layer (light-shielding wiring layer), a second metal layer (gate metal layer) and a first conductive layer (COM ITO layer); the first conductive layer is a transparent conductive layer; the first metal layer, the second metal layer and the first conductive layer are arranged in sequence along a direction away from the substrate;

[0260] A third insulating layer (buffer layer) is provided between the first electrode portion and the second electrode portion, and a fourth insulating layer (second passivation layer) is provided between the second electrode portion and the second electrode portion;

[0261] The first electrode portion is formed on the first metal layer, the second electrode is formed on the second metal layer, and the second electrode portion is formed on the first conductive layer.

[0262] Optionally, the first metal layer may be a light-shielding metal layer, the second metal layer may be a gate metal layer, the first conductive layer may be a common electrode layer, the third insulating layer may be a buffer layer, and the fourth insulating layer may be a second passivation layer.

[0263] Optionally, the display substrate further includes a display area, and the display substrate further includes a data line and a first electrode arranged in the display area;

[0264] The first plate portion is disposed in the same layer as the data line, the second plate portion is disposed in the same layer as the first electrode, and the second plate portion is disposed in the same layer as the gate of the transistor in the driving circuit.

[0265] In a specific implementation, the first electrode portion can be arranged in the same layer as the data line, the second electrode portion can be arranged in the same layer as the first electrode, and the second electrode can be arranged in the same layer as the gate of the transistor in the driving circuit. Further, the first electrode portion can be made of the same material as the data line, the second electrode portion can be made of the same material as the first electrode, and the second electrode can be made of the same material as the gate of the transistor, which can further optimize the manufacturing process, reduce costs and improve manufacturing stability.

[0266] like Fig.23A As shown, numeral 10 is a substrate, numeral 11 is a shading metal layer, numeral 12 is a buffer layer, numeral 13 is a semiconductor layer, numeral 14 is a gate insulating layer, numeral 15 is a gate metal layer, numeral 16 is a first passivation layer, numeral 17 is an organic layer, numeral 18 is a first conductive layer, numeral 19 is a second passivation layer, and numeral 110 is a second conductive layer.

[0267] exist Fig.23A , Fig. 23B middle,

[0268] The area labeled A1 is the peripheral area, and the area labeled A2 is the display area;

[0269] In the display area A2, the first conductive layer 18 includes a common electrode CM, and the second conductive layer 110 includes a pixel electrode PX;

[0270] The first electrode plate of the capacitor includes a first electrode plate portion J11 and a second electrode plate portion J12 electrically connected to each other, and the second electrode plate J2 of the capacitor is arranged between J11 and J12;

[0271] J11 is formed on the light shielding metal layer 11, J2 is formed on the gate metal layer 15, and J12 forms the first conductive layer 18;

[0272] J11 is electrically connected to J12 via a conductive pattern formed on the second conductive layer and a conductive pattern formed on the gate metal layer;

[0273] The orthographic projection of J11 on the base, the orthographic projection of J12 on the base and the orthographic projection of J2 on the base at least partially overlap;

[0274] After etching the gate insulating layer, only the buffer layer 12 exists between J2 and J11;

[0275] After the organic layer is removed between J2 and J12 , only the first passivation layer 16 exists.

[0276] In making Fig.23A , Fig. 23B In at least one embodiment of the display substrate shown in FIG. Fig.23C As shown, after a light-shielding metal layer 11, a buffer layer 12, a semiconductor layer 13 and a gate insulating layer 14 are sequentially manufactured on a substrate 10, a PR glue (photoresist) 230 is coated on a side of the gate insulating layer 14 away from the substrate 10, and exposure is performed through a mask MK, wherein the area labeled Q1 is a semi-transparent area of ​​MK, the area labeled Q2 is a fully transparent area of ​​MK, and the area of ​​MK other than Q1 and Q2 is an opaque area;

[0277] After exposure through the mask MK, the PR glue corresponding to the fully transparent area Q2 is exposed to light and the PR glue is completely removed. The PR glue corresponding to the semi-transparent area Q1 is exposed to light and a thinner PR glue is left after cleaning, such as Fig.24 As shown;

[0278] After etching, Fig.25 As shown, the fully transparent area will have a greater etching depth, etching to the light-shielding metal layer; the semi-transparent area has a smaller etching depth due to the thinner PR glue blocking, etching to the semiconductor layer and the buffer layer, thus forming different etching depths.

[0279] Continue to make subsequent film layers, and the final structure is as follows Fig. 23B shown.

[0280] like Fig. 23B As shown, in the peripheral area A1, the first electrode plate of the capacitor includes a first electrode plate portion J11 and a second electrode plate portion J12 electrically connected to each other, and the second electrode plate J2 of the capacitor is arranged between J11 and J12;

[0281] J11 is formed on the light-shielding metal layer 11, J2 is formed on the gate metal layer 15, and J12 forms the first conductive layer 18; wherein, J11 and J12 are connected through conductive pattern transfers and vias formed on the second conductive layer, and form a three-layer overlapping capacitor with J2, thereby realizing an increase in capacitance. In order to increase the capacitance value of the capacitor, in the area where the capacitor is set, the organic layer adopts a groove design to reduce the thickness of the insulating layer between J12 and J1. After the organic layer is removed, only the first passivation layer exists between the second electrode portion J12 and the second electrode plate J2, and the capacitance value per unit area is improved. After the second electrode plate J2 and the first electrode plate portion J11 are etched through the gate insulating layer, only a buffer layer exists between the second electrode plate J2 and the first electrode plate portion J11. Compared with conventional structures, at least one embodiment of the present invention can reduce the thickness of the insulating layer between adjacent electrode portions, and can form a larger capacitance value under a smaller area occupancy, realize the capacitance storage requirements in the drive circuit, and reduce the occupied space of the drive circuit.

[0282] like Fig. 23BAs shown, the overlapping electrode DJ will be exposed in the liquid crystal box. During the driving process, the electric field of the electrode will drive the liquid crystal to rotate. However, because the front BM will be designed to block the surrounding area A1, it will not cause adverse effects on the display.

[0283] Fig. 23B The equivalent circuit diagram of the capacitor structure is as follows Fig.26 As shown, the capacitor structure can be equivalent to two capacitors connected in parallel. Under the same overlapping area, the capacitance value of the capacitor can be doubled.

[0284] like Fig.26 As shown, the capacitor structure can be equivalent to two capacitors connected in parallel, wherein J2 and J11 form a capacitor, and J2 and J12 form a capacitor.

[0285] In at least one embodiment of the present invention, the first electrode plate includes a first electrode plate portion and a second electrode plate portion electrically connected to each other, and the second electrode plate includes a third electrode plate portion and a fourth electrode plate portion electrically connected to each other;

[0286] The first electrode portion, the third electrode portion, the second electrode portion, and the fourth electrode portion are sequentially arranged along a direction away from the substrate.

[0287] Optionally, the at least two conductive layers include: a first metal layer, a second metal layer, a first conductive layer, and a second conductive layer arranged in sequence in a direction away from the substrate; the first conductive layer and the second conductive layer are transparent conductive layers;

[0288] The first electrode portion is formed on the first metal layer, the second electrode portion is formed on the first conductive layer, the third electrode portion is formed on the second metal layer, and the fourth electrode portion is formed on the second conductive layer.

[0289] Optionally, the first metal layer may be a light-shielding metal layer, the second metal layer may be a gate metal layer, the first conductive layer may be a common electrode layer, and the second conductive layer may be a pixel electrode layer.

[0290] In at least one embodiment of the present invention, the display substrate further includes a display area, and the display substrate further includes a data line, a sub-pixel and a first electrode arranged in the display area; the sub-pixel includes a second electrode;

[0291] The first plate portion is disposed in the same layer as the data line, the second plate portion is disposed in the same layer as the first electrode, the third plate portion is disposed in the same layer as the gate of the transistor in the driving circuit, and the fourth plate portion is disposed in the same layer as the second electrode.

[0292] In a specific implementation, the first electrode portion can be arranged in the same layer as the data line, the second electrode portion can be arranged in the same layer as the first electrode, the third electrode portion can be arranged in the same layer as the gate electrode of the transistor in the driving circuit, and the fourth electrode portion can be arranged in the same layer as the second electrode. Furthermore, the first electrode portion can be made of the same material as the data line, the second electrode portion can be made of the same material as the first electrode, the third electrode portion can be made of the same material as the gate electrode of the transistor, and the fourth electrode portion can be made of the same material as the second electrode, which can further optimize the manufacturing process, reduce costs and improve manufacturing stability.

[0293] In a specific implementation, in order to further reduce the space occupied by the driving circuit, the light-shielding metal layer, the gate metal layer, the first conductive layer, and the second conductive layer can be used to form the plate portions of the capacitor respectively, forming a four-layer overlapping capacitor, thereby improving the capacitance value. Among them, the first plate portion is formed on the light-shielding metal layer, the second plate portion is formed on the first conductive layer, the third plate portion is formed on the gate metal layer, and the fourth plate portion is formed on the second conductive layer. The first plate portion and the second plate portion are electrically connected to each other, and the third plate portion and the fourth plate portion are electrically connected to each other.

[0294] like Fig.27A and Fig.27B As shown,

[0295] The area labeled A1 is the peripheral area, and the area labeled A2 is the display area;

[0296] The number 10 is a substrate, the number 11 is a shading metal layer, the number 12 is a buffer layer, the number 13 is a semiconductor layer, the number 14 is a gate insulating layer, the number 15 is a gate metal layer, the number 16 is a first passivation layer, the number 17 is an organic layer, the number 18 is a first conductive layer, the number 19 is a second passivation layer, and the number 110 is a second conductive layer.

[0297] In the display area A2, the first conductive layer 18 includes a common electrode CM, and the second conductive layer 110 includes a pixel electrode PX;

[0298] The first electrode plate of the capacitor includes a first electrode portion J11 and a second electrode portion J12 electrically connected to each other, and the second electrode plate J2 of the capacitor includes a third electrode portion J21 and a fourth electrode portion J22 electrically connected to each other;

[0299] J11 is formed on the light shielding metal layer 11, J12 is formed on the first conductive layer 18, J21 is formed on the gate metal layer 15, and J22 is formed on the second conductive layer 110;

[0300] J11 is electrically connected to J12, and J21 is electrically connected to J22; J22 and J21 are electrically connected via a via that penetrates the second passivation layer and the second passivation layer;

[0301] J12 is electrically connected to J11 through a conductive pattern formed in the second conductive layer and a via hole penetrating the second passivation layer, the first passivation layer, the gate insulating layer and the buffer layer;

[0302] In the area where the capacitor is set, the organic layer is excavated and the gate insulating layer is also removed by semi-transparent mask etching, so that only the first passivation layer exists between J12 and J21, and only the buffer layer exists between J21 and J11. This design structure can achieve a larger capacitance value with a smaller plate area.

[0303] Fig.27A , Fig.27B The equivalent circuit diagram of the capacitor structure is as follows Fig.28 As shown, the capacitor structure can be equivalent to three capacitors in parallel, wherein J22 and J12 form a capacitor, J12 and J21 form a capacitor, and J11 and J21 form a capacitor.

[0304] In at least one embodiment of the present invention, the capacitor may be a first capacitor included in the drive circuit; the drive circuit includes an output circuit, and the output circuit is used to control the connection between the drive signal output terminal and the first clock signal line under the control of the potential of the first node; the output circuit includes a third transistor; the gate of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the first clock signal line, and the second electrode of the third transistor is electrically connected to the drive signal output terminal;

[0305] The orthographic projection of the first electrode plate of the first capacitor on the substrate at least partially overlaps with the orthographic projection of the active pattern of the third transistor on the substrate;

[0306] An orthographic projection of the second plate of the first capacitor on the substrate at least partially overlaps with an orthographic projection of the active pattern of the third transistor on the substrate.

[0307] In a specific implementation, the capacitor can be the first capacitor in the driving circuit, and the orthographic projection of the electrode plate of the first capacitor on the substrate can at least partially overlap with the orthographic projection of the active pattern of the third transistor in the driving circuit on the substrate, so as to set the first capacitor above the third transistor, realize the stacking design of transistors and capacitors, save the design space of the driving circuit, and the conductive layer where the electrode plate of the first capacitor is located can also be used as a bridge trace between some transistors. At the same time, since there is a thicker organic layer between the first capacitor and the third transistor, the parasitic coupling increased after the overlapping design is small, and will not affect the performance of the driving circuit.

[0308] In at least one embodiment of the present invention, the capacitor may be a second capacitor included in the driving circuit; the driving circuit includes an output reset circuit and a second node reset circuit; the output reset circuit includes a third transistor; the second node reset circuit includes an eighth transistor;

[0309] The output reset circuit is electrically connected to the second node, the drive signal output terminal and the low voltage line respectively, and is used to control the connection between the drive signal output terminal and the low voltage line under the control of the potential of the second node;

[0310] The second node reset circuit is electrically connected to the second node, the drive signal output terminal and the low voltage line respectively, and is used to control the second node to be connected to the low voltage line under the control of the drive signal provided by the drive signal output terminal;

[0311] The gate of the fourth transistor is electrically connected to the second node, the first electrode of the fourth transistor is electrically connected to the drive signal output terminal, and the second electrode of the fourth transistor is electrically connected to the low voltage line;

[0312] The gate of the eighth transistor is electrically connected to the driving signal output terminal, the first electrode of the eighth transistor is electrically connected to the second node, and the second electrode of the eighth transistor is electrically connected to the low voltage line;

[0313] The orthographic projection of the first electrode plate of the second capacitor on the substrate at least partially overlaps with the orthographic projection of the active pattern of the fourth transistor on the substrate;

[0314] The orthographic projection of the second electrode plate of the second capacitor on the substrate at least partially overlaps with the orthographic projection of the active pattern of the fourth transistor on the substrate;

[0315] The orthographic projection of the first electrode plate of the second capacitor on the substrate at least partially overlaps with the orthographic projection of the active pattern of the eighth transistor on the substrate;

[0316] An orthographic projection of the second plate of the second capacitor on the substrate at least partially overlaps with an orthographic projection of the active pattern of the eighth transistor on the substrate.

[0317] In a specific implementation, the capacitor may be the second capacitor in the driving circuit, and the orthographic projection of the electrode plate of the second capacitor on the substrate may at least partially overlap with the orthographic projection of the active pattern of the fourth transistor in the driving circuit on the substrate, and the orthographic projection of the electrode plate of the second capacitor on the substrate may at least partially overlap with the orthographic projection of the active pattern of the eighth transistor in the driving circuit on the substrate, so that the first capacitor is arranged above the fourth transistor and the eighth transistor to realize a stacked design of transistors and capacitors, saving the design space of the driving circuit, and the conductive layer where the electrode plate of the second capacitor is located may also be used as a bridge trace between some transistors. At the same time, since there is a thicker organic layer between the second capacitor and the fourth transistor, and a thicker organic layer between the second capacitor and the eighth transistor, the parasitic coupling increased after the overlapping design is small, and will not affect the performance of the driving circuit.

[0318] The manufacturing method of the display substrate according to the embodiment of the present invention is applied to the above-mentioned display substrate, and the manufacturing method of the display substrate includes:

[0319] At least two conductive layers are formed on one side of the substrate; the at least two conductive layers are arranged along a direction perpendicular to the one side of the substrate;

[0320] Performing a patterning process on at least one of the at least two conductive layers to form at least one plate portion included in the first plate; performing a patterning process on at least one of the at least two conductive layers except the at least one conductive layer to form at least one plate portion included in the second plate; and controlling the plate portions included in the first plate and the plate portions included in the second plate to be alternately arranged;

[0321] An insulating layer is provided between two adjacent electrode plates, and a thickness of the insulating layer is set to be less than a first thickness threshold;

[0322] The first thickness threshold is greater than or equal to 800 angstroms and less than or equal to 1200 angstroms.

[0323] Optionally, the manufacturing method described in at least one embodiment of the present invention includes:

[0324] Manufacturing a light-shielding metal layer on the substrate, and patterning the light-shielding metal layer to form a first electrode portion included in the first electrode plate;

[0325] A buffer layer, a semiconductor layer and a gate insulating layer are sequentially formed on a side of the light-shielding metal layer away from the substrate;

[0326] Coating a photoresist on a side of the gate insulating layer away from the substrate, and exposing the display substrate coated with the photoresist using a mask, wherein the mask includes a semi-transparent area and an opaque area;

[0327] Etching the exposed display substrate to remove the residual photoresist, wherein the gate insulating layer is etched away in the semi-transparent area;

[0328] Making a first connecting via hole penetrating the gate insulating layer and the buffer layer;

[0329] A gate metal layer is formed on a side of the gate insulating layer away from the substrate, and a patterning process is performed on the gate metal layer to form a third electrode portion included in the second electrode plate;

[0330] Sequentially forming a second passivation layer and an organic layer on a side of the gate metal layer away from the substrate;

[0331] Performing a drilling operation on the organic layer to form a second connecting via hole penetrating the organic layer;

[0332] forming a first electrode layer on a side of the organic layer away from the substrate, performing a patterning process on the first electrode layer to form a second electrode portion included in the first electrode plate, and making the second electrode portion directly contact the second passivation layer through the second connecting via hole;

[0333] Forming a first passivation layer on a side of the first electrode layer away from the substrate, and forming a third connection via hole penetrating the first passivation layer and a fourth connection via hole penetrating the first passivation layer and the second passivation layer;

[0334] A second electrode layer is formed on a side of the first passivation layer away from the substrate, and a patterning process is performed on the second electrode layer to form a conductive connection portion, so that the conductive connection portion is electrically connected to the second electrode portion through the third connection via hole, and the conductive connection portion is electrically connected to the first electrode portion through the second connection via hole and the fourth connection via hole;

[0335] The first electrode layer and the second electrode layer are made of metal oxide.

[0336] The manufacturing method described in at least one embodiment of the present invention further includes:

[0337] While making a fourth connection via hole penetrating the first passivation layer and the second passivation layer, making a fifth connection via hole penetrating the first passivation layer and the second passivation layer;

[0338] While the second electrode layer is patterned to form the conductive connection portion, the fourth electrode portion included in the second electrode is formed, and the fourth electrode portion is electrically connected to the third electrode portion through the fifth connection via.

[0339] The display device described in at least one embodiment of the present invention includes the above-mentioned display substrate, and the display device can be any product or component with display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc. The display device can be applied to any one or more display devices in the display field, such as liquid crystal display (LCD), organic light emitting diode (OLED), micro display (MLED), quantum dot display (QLED / QD-OLED), etc.

[0340] The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A display substrate, characterized in that: The display substrate comprises a substrate and at least two conductive layers arranged on one side of the substrate, wherein the at least two conductive layers are arranged in a direction perpendicular to the one side of the substrate; the display substrate comprises a display area and a peripheral area surrounding the display area; the display substrate further comprises a driving circuit arranged on the substrate, wherein the driving circuit comprises a capacitor; the capacitor is arranged in the peripheral area; the capacitor comprises a first electrode plate and a second electrode plate; the orthographic projection of the first electrode plate on the substrate at least partially overlaps with the orthographic projection of the second electrode plate on the substrate; At least one of the first electrode plate and the second electrode plate is in the same layer as the conductive layer; An insulating layer is provided between the first electrode plate and the second electrode plate, and a thickness of the insulating layer is less than a first thickness threshold; The first thickness threshold is greater than or equal to 800 angstroms and less than or equal to 1200 angstroms.

2. The display substrate according to claim 1, wherein: The driving circuit further includes a transistor; The first electrode plate and the second electrode plate are located at a side of the transistor away from the substrate.

3. The display substrate according to claim 1 or 2, characterized in that: Only one insulating layer is disposed between the first electrode plate and the second electrode plate.

4. The display substrate according to claim 1 or 2, characterized in that: The first electrode plate includes at least one electrode plate portion, and the second electrode plate includes at least one electrode plate portion; the electrode plate portions included in the first electrode plate and the electrode plate portions included in the second electrode plate are arranged alternately, an insulating layer is arranged between two adjacent electrode plate portions, and the thickness of the insulating layer between two adjacent electrode plate portions is less than the first thickness threshold.

5. The display substrate according to claim 1 or 2, characterized in that: The first electrode plate includes at least two electrode plate portions, and the at least two electrode plate portions are electrically connected to each other; and / or, The first electrode plate includes at least two electrode plate portions, and the at least two electrode plate portions are electrically connected to each other.

6. The display substrate according to claim 2, wherein: The electrodes of the transistor include a gate, a first electrode and a second electrode; The orthographic projection of the first electrode plate on the substrate at least partially overlaps with the orthographic projection of the electrode included in the transistor on the substrate; The orthographic projection of the first electrode plate on the substrate at least partially overlaps with the orthographic projection of the active pattern of the transistor on the substrate; The orthographic projection of the second electrode plate on the substrate at least partially overlaps with the orthographic projection of the electrode included in the transistor on the substrate; An orthographic projection of the second electrode plate on the substrate at least partially overlaps with an orthographic projection of the active pattern of the transistor on the substrate.

7. The display substrate according to claim 6, wherein: The display substrate further includes a sub-pixel and a first electrode disposed in the display area; the sub-pixel includes a second electrode; The first electrode plate is disposed in the same layer as the first electrode, and the second electrode plate is disposed in the same layer as the second electrode.

8. The display substrate according to claim 6, wherein: The display substrate comprises a first insulating layer disposed between the capacitor and the transistor; The thickness of the first insulating layer is greater than a second thickness threshold, and the second thickness threshold is greater than or equal to 0.8 μm and less than or equal to 1.2 μm.

9. The display substrate according to claim 6, wherein: The display substrate comprises a first insulating layer and a second insulating layer arranged between the capacitor and the transistor; the second insulating layer is arranged between the transistor and the first insulating layer; The first insulating layer has a groove, and the first electrode plate is directly in contact with the second insulating layer through the groove; At least a portion of the first electrode plate and at least a portion of the second electrode plate are disposed in the groove.

10. The display substrate according to claim 1, wherein: The first electrode plate includes a first electrode plate portion and a second electrode plate portion electrically connected to each other; The second electrode plate is disposed between the first electrode plate portion and the second electrode plate portion.

11. The display substrate according to claim 10, wherein: The at least two conductive layers include: a first metal layer, a second metal layer and a first conductive layer; the first conductive layer is a transparent conductive layer; the first metal layer, the second metal layer and the first conductive layer are arranged in sequence along a direction away from the substrate; A third insulating layer is provided between the first electrode portion and the second electrode portion, and a fourth insulating layer is provided between the second electrode portion and the second electrode portion; The first electrode portion is formed on the first metal layer, the second electrode is formed on the second metal layer, and the second electrode portion is formed on the first conductive layer.

12. The display substrate according to claim 11, wherein: The display substrate further includes a data line and a first electrode arranged in the display area; The first plate portion is disposed in the same layer as the data line, the second plate portion is disposed in the same layer as the first electrode, and the second plate portion is disposed in the same layer as the gate of the transistor.

13. The display substrate according to claim 1, wherein: The first electrode plate includes a first electrode plate portion and a second electrode plate portion electrically connected to each other, and the second electrode plate includes a third electrode plate portion and a fourth electrode plate portion electrically connected to each other; The first electrode portion, the third electrode portion, the second electrode portion, and the fourth electrode portion are sequentially arranged along a direction away from the substrate.

14. The display substrate according to claim 13, wherein: The at least two conductive layers include: a first metal layer, a second metal layer, a first conductive layer, and a second conductive layer arranged in sequence in a direction away from the substrate; the first conductive layer and the second conductive layer are transparent conductive layers; The first electrode portion is formed on the first metal layer, the second electrode portion is formed on the first conductive layer, the third electrode portion is formed on the second metal layer, and the fourth electrode portion is formed on the second conductive layer.

15. The display substrate according to claim 14, wherein: The display substrate further comprises a data line, a sub-pixel and a first electrode arranged in the display area; the sub-pixel comprises a second electrode; The first plate portion is disposed in the same layer as the data line, the second plate portion is disposed in the same layer as the first electrode, the third plate portion is disposed in the same layer as the gate of the transistor, and the fourth plate portion is disposed in the same layer as the second electrode.

16. The display substrate according to claim 2, wherein: The capacitor is a first capacitor included in the driving circuit; the driving circuit includes an output circuit, and the output circuit is used to control the connection between the driving signal output terminal and the first clock signal line under the control of the potential of the first node; the output circuit includes a third transistor; the gate of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the first clock signal line, and the second electrode of the third transistor is electrically connected to the driving signal output terminal; The orthographic projection of the first electrode plate of the first capacitor on the substrate at least partially overlaps with the orthographic projection of the active pattern of the third transistor on the substrate; An orthographic projection of the second plate of the first capacitor on the substrate at least partially overlaps with an orthographic projection of the active pattern of the third transistor on the substrate.

17. The display substrate according to claim 2, wherein: The capacitor is a second capacitor included in the driving circuit; the driving circuit includes an output reset circuit and a second node reset circuit; the output reset circuit includes a fourth transistor; the second node reset circuit includes an eighth transistor; The output reset circuit is electrically connected to the second node, the drive signal output terminal and the low voltage line respectively, and is used to control the connection between the drive signal output terminal and the low voltage line under the control of the potential of the second node; The second node reset circuit is electrically connected to the second node, the drive signal output terminal and the low voltage line respectively, and is used to control the second node to be connected to the low voltage line under the control of the drive signal provided by the drive signal output terminal; The gate of the fourth transistor is electrically connected to the second node, the first electrode of the fourth transistor is electrically connected to the drive signal output terminal, and the second electrode of the fourth transistor is electrically connected to the low voltage line; The gate of the eighth transistor is electrically connected to the driving signal output terminal, the first electrode of the eighth transistor is electrically connected to the second node, and the second electrode of the eighth transistor is electrically connected to the low voltage line; The orthographic projection of the first electrode plate of the second capacitor on the substrate at least partially overlaps with the orthographic projection of the active pattern of the fourth transistor on the substrate; The orthographic projection of the second electrode plate of the second capacitor on the substrate at least partially overlaps with the orthographic projection of the active pattern of the fourth transistor on the substrate; The orthographic projection of the first electrode plate of the second capacitor on the substrate at least partially overlaps with the orthographic projection of the active pattern of the eighth transistor on the substrate; An orthographic projection of the second plate of the second capacitor on the substrate at least partially overlaps with an orthographic projection of the active pattern of the eighth transistor on the substrate.

18. A method for manufacturing a display substrate, applied to the display substrate according to any one of claims 1 to 17, characterized in that: The manufacturing method of the display substrate comprises: At least two conductive layers are formed on one side of the substrate; the at least two conductive layers are arranged along a direction perpendicular to the one side of the substrate; Performing a patterning process on at least one of the at least two conductive layers to form at least one plate portion included in the first plate; performing a patterning process on at least one of the at least two conductive layers except the at least one conductive layer to form at least one plate portion included in the second plate; and controlling the plate portions included in the first plate and the plate portions included in the second plate to be alternately arranged; An insulating layer is provided between two adjacent electrode plates, and a thickness of the insulating layer is set to be less than a first thickness threshold; The first thickness threshold is greater than or equal to 800 angstroms and less than or equal to 1200 angstroms.

19. The method for manufacturing a display substrate according to claim 18, wherein: The production method comprises: Manufacturing a light-shielding metal layer on the substrate, and patterning the light-shielding metal layer to form a first electrode portion included in the first electrode plate; A buffer layer, a semiconductor layer and a gate insulating layer are sequentially formed on a side of the light-shielding metal layer away from the substrate; Coating a photoresist on a side of the gate insulating layer away from the substrate, and exposing the display substrate coated with the photoresist using a mask, wherein the mask includes a semi-transparent area and an opaque area; Etching the exposed display substrate to remove the residual photoresist, wherein the gate insulating layer is etched away in the semi-transparent area; Making a first connecting via hole penetrating the gate insulating layer and the buffer layer; A gate metal layer is formed on a side of the gate insulating layer away from the substrate, and a patterning process is performed on the gate metal layer to form a third electrode portion included in the second electrode plate; Sequentially forming a second passivation layer and an organic layer on a side of the gate metal layer away from the substrate; Performing a drilling operation on the organic layer to form a second connecting via hole penetrating the organic layer; forming a first electrode layer on a side of the organic layer away from the substrate, performing a patterning process on the first electrode layer to form a second electrode portion included in the first electrode plate, and making the second electrode portion directly contact the second passivation layer through the second connecting via hole; Forming a first passivation layer on a side of the first electrode layer away from the substrate, and forming a third connection via hole penetrating the first passivation layer and a fourth connection via hole penetrating the first passivation layer and the second passivation layer; A second electrode layer is formed on a side of the first passivation layer away from the substrate, and a patterning process is performed on the second electrode layer to form a conductive connection portion, so that the conductive connection portion is electrically connected to the second electrode portion through the third connection via hole, and the conductive connection portion is electrically connected to the first electrode portion through the second connection via hole and the fourth connection via hole; The first electrode layer and the second electrode layer are made of metal oxide.

20. The method of claim 19, wherein: Also includes: While making a fourth connection via hole penetrating the first passivation layer and the second passivation layer, making a fifth connection via hole penetrating the first passivation layer and the second passivation layer; While the second electrode layer is patterned to form the conductive connection portion, the fourth electrode portion included in the second electrode is formed, and the fourth electrode portion is electrically connected to the third electrode portion through the fifth connection via.

21. A display device, characterized in that: The display substrate comprises a display substrate as claimed in any one of claims 1 to 17.

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