A storage-computation integrated unit and method for realizing multiplication function

Abstract

The present invention discloses a storage-computation integrated unit for realizing a multiplication function. The unit includes a collection transistor and a readout transistor formed on the same P-type silicon substrate; a voltage is input into the readout transistor through a control gate to control and modulate carriers as a first multiplier; a carrier collection region of the collection transistor collects carriers and stores the carriers in a charge coupling layer as a second multiplier; the charge coupling layer acts on the silicon substrate of the readout transistor to form a multiplication operation relationship; and a carrier readout region of the readout transistor outputs the carriers acted on by the first multiplier and the second multiplier in the form of current as an output result of the multiplication operation. The present invention separates the collection and operation functions of the storage-computation integrated device by region, effectively protects the readout function region when the device collects carriers, and can improve the life, durability and readout accuracy of the storage-computation integrated device.

Description

Technical Field

[0001] The present invention relates to a storage-calculation integrated unit and a method thereof for realizing a multiplication function, and more specifically, to a structure, a collection mechanism and a readout mechanism of a storage-calculation integrated unit based on a shared dielectric gate dual transistor. Background Art

[0002] In the traditional von Neumann computing architecture, the storage unit and the computing unit are separated, which results in repeated calls to the network weights when executing a class of algorithms represented by neural network algorithms, resulting in huge power consumption in data transmission.

[0003] In order to overcome this limitation, researchers have proposed a storage-computing integrated device. In the international patent PCT / CN2019 / 081342, an analog vector-matrix multiplication circuit is implemented based on a programmable memory (Flash) array. The proposed analog vector-matrix multiplication circuit includes a programmable semiconductor device array, a programming circuit, a controller, a conversion device, and a current detection output circuit. In the Chinese patent CN111208865B, a photoelectric storage-computing integrated device is proposed. The readout unit is characterized in that it can collect photocarriers at the optical input end and store them for a long time after the light is cut off, and can realize the multiplication operation of a single device, thereby realizing high-precision storage-computing integrated function, which is very suitable for accelerating a class of algorithms represented by neural network algorithms. However, the collection and readout functions of the storage-computing integrated device proposed in the above scheme are realized in the same area inside the device. During the collection process, high voltage is frequently applied to the device, which is bound to damage the internal structure of the device, resulting in a short device life, poor durability, and low readout accuracy. Summary of the invention

[0004] The object of the present invention is to provide a storage-computation integrated unit for realizing a multiplication function, so as to improve the life, durability and readout accuracy of the storage-computation integrated device.

[0005] The technical solution adopted by the method of the present invention is as follows:

[0006] A storage-computation integrated unit for realizing a multiplication function, the unit comprising a collection transistor and a readout transistor formed on the same P-type silicon substrate, respectively realizing a carrier collection function and a carrier readout function; the collection transistor and the readout transistor share a dielectric gate structure, the dielectric gate structure is located above the P-type silicon substrate, and comprises a bottom dielectric layer, a charge coupling layer, a top dielectric layer and a control gate from bottom to top; a carrier collection region, a collection tube source region and a collection tube drain region are provided in the silicon substrate of the collection transistor, and a carrier readout region, a readout tube source region and a readout tube drain region are provided in the silicon substrate of the readout transistor; the silicon substrate of the collection transistor is separated from the silicon substrate of the readout transistor by an isolation region;

[0007] A voltage is input into the readout transistor through the control gate to control and modulate the carriers as a first multiplier; the carrier collection region of the collection transistor collects the carriers and stores the carriers in the charge coupling layer as a second multiplier; the charge coupling layer acts on the silicon substrate of the readout transistor with the carriers to form a multiplication operation relationship; the carrier readout region of the readout transistor outputs the carriers after being acted upon by the first multiplier and the second multiplier in the form of current as an output result of the multiplication operation.

[0008] Furthermore, the carrier collection region of the collection transistor collects photogenerated carriers, and under illumination conditions, a photoelectric effect is generated in the carrier collection region of the collection transistor by controlling the voltage of the collection tube source region, the collection tube drain region, the control gate, and the P-type silicon substrate, thereby realizing electron collection.

[0009] Furthermore, the carrier collection region of the collection transistor collects electrically generated carriers, and by controlling the voltage of the collection tube source region, the collection tube drain region, the control gate, and the P-type silicon substrate, a strong lateral electric field is generated in the carrier collection region of the collection transistor to achieve channel hot electron collection.

[0010] Furthermore, the width-to-length ratio of the collection transistor is greater than the width-to-length ratio of the readout transistor.

[0011] Furthermore, the material of the bottom dielectric layer is silicon oxide or silicon oxynitride; the material of the charge coupling layer is polysilicon; the material of the top dielectric layer is silicon oxide-silicon nitride-silicon oxide, silicon oxide-aluminum oxide-silicon oxide, silicon oxide or aluminum oxide; the material of the control gate is polysilicon, metal or a transparent conductive electrode.

[0012] The working method of the storage-computation integrated unit for realizing the multiplication function of the present invention comprises the following steps:

[0013] (1) Generation and collection of carriers: divided into two cases: photogenerated carriers and electrically generated carriers:

[0014] For the generation and collection of photogenerated carriers, under external light conditions, a positive voltage is applied to the control gate, a negative voltage is applied to the P-type silicon substrate, and a 0V bias is applied to the source region and the drain region of the collection tube, so that the electrons in the P-type silicon substrate of the collection transistor are depleted under the action of a strong electric field in a vertical direction, and the energy of the photons incident on the depletion region is absorbed, and the valence band electrons of the silicon substrate are excited to the conduction band, generating photogenerated electron-hole pairs, and part of the electrons generated in the depletion region are accelerated under the action of the vertical electric field, and accelerate while moving toward the bottom dielectric layer to obtain a sufficiently high energy to cross the potential barrier of the silicon conduction band and the bottom dielectric layer and enter the bottom dielectric layer, and move at a very high speed toward the charge coupling layer under the action of the electric field in the bottom dielectric layer, enter the charge coupling layer and store therein, and complete the collection; and in the above process, the source region and the drain region of the readout transistor are applied with the same negative voltage bias as the P-type silicon substrate, so as to suppress the silicon substrate in the readout transistor from generating a strong electric field in a vertical direction, thereby suppressing the readout transistor from generating and collecting photogenerated carriers;

[0015] For the generation and collection of electrically generated carriers, under the condition of no light, a positive voltage is applied to the control gate, a 0V bias is applied to the P-type silicon substrate, a 0V bias is applied to the source region of the collection tube, and a positive voltage bias is applied to the drain region of the collection tube, so that an inversion occurs at the channel of the P-type silicon substrate between the source region of the collection tube and the drain region of the collection tube and a strong transverse electric field exists. The electrons in the source region of the collection tube are accelerated under the action of the transverse electric field, and accelerate to gain energy while moving toward the drain region of the collection tube. When they move to the bottom of the bottom dielectric layer, the energy is sufficient to cross the potential barrier of the silicon conduction band and the bottom dielectric layer and enter the bottom dielectric layer. Under the action of the electric field in the bottom dielectric layer, the electrons move toward the charge coupling layer at a very high speed, enter the charge coupling layer and store it there, and the collection is completed; and in the above process, the readout tube source region and the readout tube drain region are applied with a 0V bias, so as to suppress the silicon substrate in the readout transistor from generating a strong vertical electric field, thereby suppressing the readout transistor from generating and collecting electrically generated carriers;

[0016] (2) Reading out the multiplication result in current form: inputting voltage into the readout transistor through the control gate to control and modulate the carriers as the first multiplier; the carriers collected in the charge coupling layer change the potential of the charge coupling layer, which is equivalent to changing the threshold voltage of the readout transistor as the second multiplier; wherein the first multiplier V G represents the voltage of the common control gate, which is a binary value. When the control gate input binary data is 0, no matter how many carriers are collected in the charge coupling layer, that is, how much the second multiplier is equal to, it is enough to make the readout transistor in the cut-off region, and the output current I D=0, the output result is 0, which is consistent with the multiplication result of the first multiplier being 0 and the second multiplier of any size; when the control gate input binary data is 1, it is equal to the input constant control gate voltage, at this time the multiplier V G It is enough to make the silicon substrate in the readout transistor strongly inverted, the P-type silicon substrate is connected to 0V, the readout transistor source region is connected to 0V, and the readout transistor drain region is connected to 0.2V, so that the readout transistor works in the linear resistance region. Due to the potential V between the readout transistor source region and the readout transistor drain region DS It is also a constant value. The read current output result depends only on the threshold voltage of the read transistor after collecting carriers, that is, the second multiplier. Its output result still conforms to the multiplication result of the first multiplier with a constant value of 1 and the second multiplier of any size.

[0017] The storage-computing integrated unit designed by the present invention has the following specific characteristics and advantages:

[0018] (1) Improvement of lifespan, durability and readout accuracy: The two transistors realize the carrier collection function and the carrier readout function respectively, thereby separating the collection and calculation functions of the storage-computing integrated device by area. When the device collects carriers, the readout function area is effectively protected, which can improve the lifespan, durability and readout accuracy of the storage-computing integrated device.

[0019] (2) Improved collection efficiency: The width-to-length ratio of the collection transistor can be set larger than the width-to-length ratio of the readout transistor, thereby improving the carrier collection efficiency while maintaining the multiplication relationship unchanged;

[0020] (3) Full well improvement: The collection transistor can be set with a higher aspect ratio, which increases the gate oxide capacitor area, increases the capacitance, improves the charging capacity, and increases the number of full well carriers. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

[0022] Figure 1 It is a schematic diagram of the three-dimensional structure of the storage-computing integrated unit of the present invention;

[0023] Figure 2 yes Figure 1 The cross-section along the aa' direction;

[0024] Figure 3 yes Figure 1 The cross-section along the bb' direction;

[0025] Figure 4 yes Figure 1 Cross-sectional view along cc' direction;

[0026] Figure 5 It is a schematic diagram of the storage-computing integrated unit collecting photogenerated carriers;

[0027] Figure 6 It is a schematic diagram of the collection of electrically generated carriers by the storage-computing integrated unit;

[0028] Figure 7 It is the electrical model of the collector transistor;

[0029] Figure 8 It is a schematic diagram of the first type of multiplication operation of the storage-computation integrated unit;

[0030] Fig. 9 It is a schematic diagram of the second type of multiplication operation of the storage-computation unit. DETAILED DESCRIPTION

[0031] In order to make the purpose, technical solution and advantages of the embodiments of the present invention more obvious, the following will be described in detail with reference to the accompanying drawings. In this specification and the accompanying drawings, substantially the same steps and elements are represented by the same reference numerals, and repeated explanations of these steps and elements will be omitted.

[0032] It should be understood that the described embodiments are only some embodiments of the present invention, rather than all embodiments of the present invention. Based on the embodiments described in the present invention, all other embodiments obtained by those skilled in the art without creative work should fall within the protection scope of the present invention. Moreover, in order to make the description clearer and more concise, detailed descriptions of functions and structures well known in the art will be omitted.

[0033] Reference Figures 1 to 4 The storage-computation integrated unit for realizing the multiplication function of this embodiment is described. The unit structure includes two transistors, a collection transistor and a readout transistor, which share a dielectric gate structure formed on the same P-type silicon substrate. The two transistors realize the carrier collection function and the carrier readout function respectively. The width-to-length ratio of the collection transistor can be set to be greater than the width-to-length ratio of the readout transistor, so as to improve the carrier collection area and collection efficiency while maintaining the multiplication operation relationship unchanged.

[0034] like Figure 1 As shown, the shared dielectric gate structure of the two transistors includes, from bottom to top, a bottom dielectric layer, a charge coupling layer, a top dielectric layer, and a control gate. In this embodiment, the bottom dielectric layer is a silicon oxide material with a thickness of about ten nanometers, the charge coupling layer is a polysilicon floating gate with a thickness of about sixty nanometers, the top dielectric layer is a three-layer structure of silicon oxide-silicon nitride-silicon oxide, and the thickness of the three layers is about four nanometers. The control gate is a polysilicon material, and its length and width are both submicron to several microns.

[0035] like Figure 2As shown, the silicon substrate of the collection transistor is separated from the silicon substrate of the readout transistor by shallow trench isolation; for the shallow trench isolation process, high-density ion plasma bombardment sputtering is used to make the silicon dioxide material effectively fill the trapezoidal groove, and then the deposited silicon dioxide is flattened and set to be at the same height as the P-type substrate. The final silicon dioxide filling depth is about two hundred nanometers.

[0036] like Figure 3 As shown, the collection transistor has N-type source and drain regions, which are respectively formed at two ends of a substrate on one side of the collection transistor (ie, the carrier collection region) by N-type silicon ion implantation.

[0037] like Figure 4 As shown, the readout transistor has N-type source and drain regions, which are respectively formed at two ends of a substrate on one side of the readout transistor (ie, a carrier readout region) by N-type silicon ion implantation.

[0038] The following reference Figure 5 , Figure 6 Describe the two working modes of the storage-computing unit for generating and collecting carriers.

[0039] like Figure 5 As shown in the figure, the storage-computing integrated unit is in the working mode of generating and collecting photogenerated carriers. For the collection transistor, under external light conditions, +5V is added to the common control gate, -3V is added to the P-type substrate, and 0V is biased to the source and drain regions of the collection transistor, causing the electrons in part of the P-type substrate on one side of the collection transistor to be depleted under the action of a strong electric field in the vertical direction (the arrow represents the direction of movement of the electrons under the action of the electric field). The energy of the photons incident on the depletion region is absorbed, and the absorbed energy excites the valence band electrons of the silicon substrate to the conduction band, generating photogenerated electron-hole pairs, and generating part of the depletion region. The electrons (only this part of the electrons is drawn in the figure) are accelerated under the action of the vertical electric field, and accelerate while moving toward the underlying dielectric layer to obtain sufficiently high energy to cross the potential barrier between the silicon conduction band and the underlying dielectric layer and enter the underlying dielectric layer, and move toward the charge coupling layer at a very high speed under the action of the electric field in the underlying dielectric layer, enter the charge coupling layer and be stored there, completing the collection; and in the above process, the source and drain regions of the readout transistor are applied with the same -3V as the P-type substrate, suppressing the generation of a strong vertical electric field on this side of the substrate, thereby suppressing the generation and collection of photogenerated carriers in this area.

[0040] like Figure 6As shown, the storage-computing integrated unit is in a working mode of generating and collecting electrically generated carriers. For the collecting transistor, under no light conditions, +5V is added to the common control gate, 0V bias is added to the P-type substrate, 0V bias is added to the source region of the collecting transistor, and 4V is added to the drain region of the collecting transistor, causing inversion at the P-type substrate channel between the source and drain regions of the collecting transistor and the existence of a strong transverse electric field (the arrow represents the movement direction of the electron under the action of the electric field). The electrons in the source region are accelerated under the action of the transverse electric field, and accelerate to gain energy while moving toward the drain region. When moving to the bottom of the common underlying matrix layer, the energy is sufficient to cross the potential barriers of the silicon conduction band and the underlying dielectric layer and enter the underlying dielectric layer, and under the action of the electric field in the underlying dielectric layer, move toward the charge coupling layer at a very high speed, enter the charge coupling layer and store it there, completing the collection; and in the above process, a 0V bias is applied to the source and drain region of the readout transistor to suppress the generation of a strong electric field in the vertical direction of the substrate on this side, thereby suppressing the generation and collection of electrically generated carriers in this area.

[0041] Reference Figure 7 , Figure 8 , Fig. 9 Describe the multiplication function implemented by the storage-arithmetic unit in the form of readout current.

[0042] like Figure 7 As shown, the effect of the charge collected by the collection transistor on the readout tube current is quantitatively analyzed.

[0043] Among them, C FC , C S , C B , C D They are the capacitances between the floating gate and the control gate, the source terminal, the substrate, and the drain terminal.

[0044] When there is no charge in the floating gate, available:

[0045]

[0046] Among them, V FG is the potential on the floating gate, V CG is the potential on the control gate, V S 、V D 、V B are the potentials of the source, drain and substrate respectively.

[0047] If we define the total capacitance of the floating gate, C T C T =C FC +C S +C D +C B , and define the coupling coefficient of electrode J for The electrode J can be any one of the control gate G, the drain terminal D, the source terminal S, and the substrate B, and then the floating gate potential V FG The coupling coefficient can be expressed as:

[0048] V FG =α G V GS +α D V DS +α S V S +α B V B (1-2)

[0049] Among them, V GS 、V DS are the gate-source voltage and source-drain voltage respectively, α G , α S , α D , α B They are the coupling coefficients of the gate, source, drain and substrate respectively. It can be seen that the potential of the floating gate is not only related to the control gate, but also to the potential of the source, drain and substrate. If the source and substrate are both grounded, then:

[0050]

[0051] in,

[0052] For floating gate devices, the threshold voltage V T The conduction coefficient β can be derived from the formula of ordinary MOS devices:

[0053]

[0054]

[0055] in, The floating gate potential when the device reaches threshold is, is the control gate potential when the device reaches the threshold, β CG is the bulk conduction coefficient for the control gate, β FG is the bulk conductivity coefficient for the floating gate.

[0056] Therefore, for the linear region For the drain current I DS for:

[0057]

[0058] When there is charge stored in the floating gate, Formulas (1-3), (1-5), and (1-7) are:

[0059]

[0060]

[0061]

[0062] From formula (1-9), we can see that V T is with is directly related to V. T Change of ΔV T It can be expressed as:

[0063]

[0064] Among them, V T0 It is the threshold value when there is no charge in the floating gate. After the charge coupling layer stores electrons, the drain current and threshold voltage of the floating gate MOSFET will change when reading.

[0065] From formula (1-11), we can know that the change of device threshold voltage caused by electrons entering the charge coupling layer can be expressed as:

[0066]

[0067] Where △V T is the change in threshold voltage, Q e is the charge of a single electron, C CG is the capacitance from control gate to floating gate, N elec is the number of photoelectrons in the storage layer. This formula shows that the change in threshold voltage is linearly related to the amount of charge. Thus, the shared charge coupling layer allows the collected and stored carriers to act on the silicon substrate on one side of the readout transistor, acting as the second multiplier on the readout current of the readout transistor.

[0068] like Figure 8 , Fig. 9 As shown, the multiplication result is read out in the form of the channel current of the readout transistor, and the common control gate is input into the readout transistor in the form of voltage to control and modulate the carriers as the first multiplier; the carriers collected in the common charge coupling layer change the potential of the common charge coupling layer, which is equivalent to changing the threshold voltage of the readout transistor as the second multiplier; where the first multiplier V G Represents the voltage of the common control gate, which is a binary value. Figure 8 As shown, when the control gate input binary data is 0, for example, VG is 0V, the P-type substrate is connected to 0V, the source region of the readout transistor is connected to 0V, and the drain region is connected to 0.2V. Regardless of the carriers collected in the common charge coupling layer, that is, the second multiplier is equal to, the readout transistor is in the cut-off region, and the output current I Dis equal to 0, the output result is 0, which is consistent with the multiplication result of the first multiplier being 0 and the second multiplier of any size. Fig. 9 As shown, when the control gate input binary data is 1, it is equal to the input of a constant control gate voltage, for example, VG is 5V, at this time V G It is enough to make the substrate on one side of the readout transistor strongly inverted, the P-type substrate is connected to 0V, the source region of the readout transistor is connected to 0V, and the drain region is connected to 0.2V, so that the readout transistor works in the linear resistance region. DS It is also a constant value. The readout current output result depends only on the threshold voltage of the readout transistor after collecting carriers (the arrow represents the direction of electron movement under the action of the electric field), that is, the second multiplier. Its output result still conforms to the multiplication result of the first multiplier with a constant value of 1 and the second multiplier of any size. Therefore, the channel current of the readout transistor completes the multiplication function of the storage-computation integrated device.

Claims

1. A storage-computation integrated unit for realizing a multiplication function, characterized in that: The unit comprises a collection transistor and a readout transistor formed on the same P-type silicon substrate, which respectively realize the carrier collection function and the carrier readout function; the collection transistor and the readout transistor share a dielectric gate structure, the dielectric gate structure is located above the P-type silicon substrate, and comprises a bottom dielectric layer, a charge coupling layer, a top dielectric layer and a control gate from bottom to top; the silicon substrate of the collection transistor is provided with a carrier collection region, a collection tube source region and a collection tube drain region, and the silicon substrate of the readout transistor is provided with a carrier readout region, a readout tube source region and a readout tube drain region; The silicon substrate of the collection transistor is separated from the silicon substrate of the readout transistor by an isolation region; A voltage is input into the readout transistor through the control gate to control and modulate the carriers as a first multiplier; the carrier collection region of the collection transistor collects the carriers and stores the carriers in the charge coupling layer as a second multiplier; the charge coupling layer acts on the silicon substrate of the readout transistor with the carriers to form a multiplication operation relationship; the carrier readout region of the readout transistor outputs the carriers after being acted upon by the first multiplier and the second multiplier in the form of current as an output result of the multiplication operation.

2. A storage-computation integrated unit for realizing a multiplication function according to claim 1, characterized in that: The carrier collection region of the collection transistor collects photogenerated carriers, and under illumination conditions, a photoelectric effect is generated in the carrier collection region of the collection transistor by controlling the voltage of the collection tube source region, the collection tube drain region, the control gate, and the P-type silicon substrate, thereby realizing electron collection.

3. The storage-computation integrated unit for realizing a multiplication function according to claim 1, characterized in that: The carrier collection region of the collection transistor collects electrically generated carriers, and by controlling the voltage of the collection tube source region, the collection tube drain region, the control gate, and the P-type silicon substrate, a strong lateral electric field is generated in the carrier collection region of the collection transistor to achieve channel hot electron collection.

4. A storage-computation integrated unit for realizing a multiplication function according to claim 1, characterized in that: The collection transistor has a width-to-length ratio greater than a width-to-length ratio of the readout transistor.

5. A storage-computation integrated unit for realizing a multiplication function according to claim 1, characterized in that: The material of the bottom dielectric layer is silicon oxide or silicon oxynitride; the material of the charge coupling layer is polysilicon; the material of the top dielectric layer is silicon oxide-silicon nitride-silicon oxide, silicon oxide-aluminum oxide-silicon oxide, silicon oxide or aluminum oxide; the material of the control gate is polysilicon, metal or a transparent conductive electrode.

6. A method for implementing a storage-calculation unit for multiplication as claimed in claim 1, characterized in that: The steps include: (1) Generation and collection of carriers: divided into two cases: photogenerated carriers and electrically generated carriers: For the generation and collection of photogenerated carriers, under external light conditions, a positive voltage is applied to the control gate, a negative voltage is applied to the P-type silicon substrate, and a 0V bias is applied to the source region and the drain region of the collection tube, so that the electrons in the P-type silicon substrate of the collection transistor are depleted under the action of a strong electric field in a vertical direction, and the energy of the photons incident on the depletion region is absorbed, and the valence band electrons of the silicon substrate are excited to the conduction band, generating photogenerated electron-hole pairs, and part of the electrons generated in the depletion region are accelerated under the action of the vertical electric field, and accelerate while moving toward the bottom dielectric layer to obtain a sufficiently high energy to cross the potential barrier of the silicon conduction band and the bottom dielectric layer and enter the bottom dielectric layer, and move at a very high speed toward the charge coupling layer under the action of the electric field in the bottom dielectric layer, enter the charge coupling layer and store therein, and complete the collection; and in the above process, the source region and the drain region of the readout transistor are applied with the same negative voltage bias as the P-type silicon substrate, so as to suppress the silicon substrate in the readout transistor from generating a strong electric field in a vertical direction, thereby suppressing the readout transistor from generating and collecting photogenerated carriers; For the generation and collection of electrically generated carriers, under the condition of no light, a positive voltage is applied to the control gate, a 0V bias is applied to the P-type silicon substrate, a 0V bias is applied to the source region of the collection tube, and a positive voltage bias is applied to the drain region of the collection tube, so that an inversion occurs at the channel of the P-type silicon substrate between the source region of the collection tube and the drain region of the collection tube and a strong transverse electric field exists. The electrons in the source region of the collection tube are accelerated under the action of the transverse electric field, and accelerate to gain energy while moving toward the drain region of the collection tube. When they move to the bottom of the bottom dielectric layer, the energy is sufficient to cross the potential barrier of the silicon conduction band and the bottom dielectric layer and enter the bottom dielectric layer. Under the action of the electric field in the bottom dielectric layer, the electrons move toward the charge coupling layer at a very high speed, enter the charge coupling layer and store it there, and the collection is completed; and in the above process, the readout tube source region and the readout tube drain region are applied with a 0V bias, so as to suppress the silicon substrate in the readout transistor from generating a strong vertical electric field, thereby suppressing the readout transistor from generating and collecting electrically generated carriers; (2) Reading out the multiplication result in current form: inputting voltage into the readout transistor through the control gate to control and modulate the carriers as the first multiplier; the carriers collected in the charge coupling layer change the potential of the charge coupling layer, which is equivalent to changing the threshold voltage of the readout transistor as the second multiplier; wherein the first multiplier V G represents the voltage of the common control gate, which is a binary value. When the control gate input binary data is 0, no matter how many carriers are collected in the charge coupling layer, that is, how much the second multiplier is equal to, it is enough to make the readout transistor in the cut-off region, and the output current I D =0, the output result is 0, which is consistent with the multiplication result of the first multiplier being 0 and the second multiplier of any size; when the control gate input binary data is 1, it is equal to the input constant control gate voltage, at this time the multiplier V G It is enough to make the silicon substrate in the readout transistor strongly inverted, the P-type silicon substrate is connected to 0V, the readout transistor source region is connected to 0V, and the readout transistor drain region is connected to 0.2V, so that the readout transistor works in the linear resistance region. Due to the potential V between the readout transistor source region and the readout transistor drain region DS It is also a constant value. The read current output result depends only on the threshold voltage of the read transistor after collecting carriers, that is, the second multiplier. Its output result still conforms to the multiplication result of the first multiplier with a constant value of 1 and the second multiplier of any size.

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