Package Structure of Semiconductor Device

Abstract

The present disclosure provides a packaging structure of a semiconductor device. The packaging structure includes: a substrate having a soldering area on its upper surface; a first semiconductor device including a first die and a first cover plate bonded to the first die on the upper surface; a first conductive bump disposed on a pad on the lower surface of the first cover plate; a second semiconductor device disposed above the first semiconductor device, including a second die and a second cover plate bonded to the second die on the upper surface, a first area on the lower surface of the second cover plate having a groove for accommodating the first semiconductor device; a second conductive bump disposed on a pad in a second area on the lower surface of the second cover plate, the length of the second conductive bump being greater than the length of the first conductive bump; and a packaging colloid covering the first and second semiconductor devices and the first and second conductive bumps. According to the packaging structure of the semiconductor device of the present disclosure, it is possible to reduce the size of the packaging structure of the semiconductor device and lower its cost.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technologies, and in particular, to a packaging structure of a semiconductor device. Background Art

[0002] With the development of wireless communication applications, the data transmission rate is getting higher and higher, resulting in an increasing demand for the utilization rate of spectrum resources and an increasingly complex spectrum, thus posing strict requirements on the performance of radio frequency systems. Due to the advantages such as low insertion loss, steep transition characteristics, high selectivity, high power capacity, and strong electrostatic discharge (ESD) resistance of filters and duplexers based on thin film bulk acoustic resonators (FBARs), they are increasingly widely used.

[0003] In the prior art, a duplexer is generally manufactured by packaging a filter for the transmit end (Tx) and a filter for the receive end (Rx) on a single packaging substrate, so that both the Tx filter and the Rx filter are formed on the same packaging substrate.

[0004] Figure 1 A cross-sectional view of a packaging structure of a duplexer according to the prior art is shown. As Figure 1 described, the Tx filter and the Rx filter of the duplexer generally both adopt wafer-level packaging. That is to say, for each of the Tx filter and the Rx filter, a filter die composed of, for example, FBAR acoustic resonators having a sandwich structure is fabricated on a wafer, and then a capping (CAP) structure, such as a capping plate, is used to cover the device wafer on which the filter die is fabricated and bond thereto to form the wafer-level packaging of the filter. Then, the Tx filter and the Rx filter having wafer-level packaging are flip-chip mounted side by side on a substrate, and usually the spacing between the Tx filter and the Rx filter is not less than 100 μm. Subsequently, the Tx filter and the Rx filter are sealed on the substrate using a packaging colloid.

[0005] However, Figure 1 the packaging structure of the duplexer according to the prior art shown at least has the following defects. The wafer-level packaging of the filter involves many process steps such as lithography, sputtering, etching, bonding, cleaning, and grinding, making the packaging process extremely complex and having strict requirements on the accuracy of packaging equipment, resulting in an increase in the overall product cost. In addition, since the Tx filter and the Rx filter of the duplexer are flip-chip mounted side by side on the substrate, the overall product size is increased. Summary of the Invention

[0006] A brief summary of the present disclosure is given below to provide a basic understanding of certain aspects of the present disclosure. However, it should be understood that this summary is not an exhaustive summary of the present disclosure, nor is it intended to identify the key or important parts of the present disclosure, nor is it intended to limit the scope of the present disclosure. The purpose of this summary is only to present certain concepts of the present disclosure in a simplified form as a prelude to the more detailed description given later.

[0007] The object of the present disclosure is to provide a packaging structure for an improved semiconductor device, which can eliminate the above-mentioned defects existing in the prior art.

[0008] According to one aspect of the present disclosure, there is provided a packaging structure for a semiconductor device, including: a substrate having a soldering area on its upper surface; a first semiconductor device including a first die and a first cover plate, the first die being bonded to the upper surface of the first cover plate; a first conductive bump disposed on a pad on the lower surface of the first cover plate of the first semiconductor device for electrically connecting to a pad in the soldering area; a second semiconductor device disposed above the first semiconductor device, including a second die and a second cover plate, the second die being bonded to the upper surface of the second cover plate, a first area on the lower surface of the second cover plate having a groove for accommodating the first semiconductor device; a second conductive bump disposed on a pad in a second area on the lower surface of the second cover plate of the second semiconductor device for electrically connecting to a pad in the soldering area, the length of the second conductive bump being greater than the length of the first conductive bump; and a packaging colloid covering the first semiconductor device, the first conductive bump, the second semiconductor device, and the second conductive bump.

[0009] According to an embodiment of the present disclosure, the substrate is a packaging substrate or a lead frame made of at least one material selected from resin, ceramic, and metal.

[0010] According to an embodiment of the present disclosure, the first die is one of a transmit filter and a receive filter in a duplexer, and the second die is the other of the transmit filter and the receive filter in the duplexer.

[0011] According to an embodiment of the present disclosure, the first cover plate has through-silicon vias and a redistribution layer for providing electrical connection between the first die and the first conductive bump, and the second cover plate has through-silicon vias and a redistribution layer for providing electrical connection between the second die and the second conductive bump.

[0012] According to an embodiment of the present disclosure, the first area is located at the center of the lower surface of the second cover plate, and the second area is located at the outer periphery of the lower surface of the second cover plate.

[0013] According to an embodiment of the present disclosure, each of the first conductive bump and the second conductive bump is made of copper, aluminum, or an alloy thereof.

[0014] According to an embodiment of the present disclosure, each of the first conductive bump and the second conductive bump is electrically connected to a pad in a solder joint area on the upper surface of the substrate by using a solder ball through at least one of a soldering process, a thermocompression bonding process, a thermosonic bonding process, and an adhesive bonding process.

[0015] According to an embodiment of the present disclosure, the solder ball is a leaded solder ball or a lead-free solder ball.

[0016] According to an embodiment of the present disclosure, the solder ball is made of copper, nickel, tin, silver, or an alloy thereof.

[0017] According to an embodiment of the present disclosure, the solder ball is disposed on the top surface of the first conductive bump and the second conductive bump.

[0018] According to an embodiment of the present disclosure, the solder ball is disposed on a pad in a solder joint area on the upper surface of the substrate.

[0019] According to an embodiment of the present disclosure, each of the first cover plate and the second cover plate is made of a silicon material or a resin material.

[0020] According to an embodiment of the present disclosure, a groove in a first area of the lower surface of the second cover plate is formed by an etching process.

[0021] According to an embodiment of the present disclosure, the encapsulation colloid is a curable resin material.

[0022] According to another aspect of the present disclosure, there is provided a method for encapsulating an electronic component, including: preparing a substrate having a solder joint area on an upper surface thereof; flip-chip bonding a first semiconductor device in the solder joint area through a first conductive bump, wherein the first semiconductor device includes a first die and a first cover plate, the first die is bonded to an upper surface of the first cover plate, and wherein the first conductive bump is disposed on a pad on a lower surface of the first cover plate of the first semiconductor device for electrically connecting to a pad in the solder joint area; flip-chip bonding a second semiconductor device in the solder joint area above the first semiconductor device through a second conductive bump, wherein the second semiconductor device includes a second die and a second cover plate, the second die is bonded to an upper surface of the second cover plate, a first area of a lower surface of the second cover plate has a groove for accommodating the first semiconductor device, and wherein the second conductive bump is disposed on a pad in a second area on a lower surface of the second cover plate of the second semiconductor device for electrically connecting to a pad in the solder joint area, and a length of the second conductive bump is greater than a length of the first conductive bump; and forming an encapsulation colloid covering the first semiconductor device, the first conductive bump, the second semiconductor device, and the second conductive bump.

[0023] According to the packaging structure of the semiconductor device of the present disclosure, by providing a groove in the cover plate of the semiconductor device located above for accommodating the semiconductor device located below, two semiconductor devices can be stacked and packaged on the substrate with a reduced height and area. Therefore, the size of the packaging structure of the semiconductor device can be reduced and the cost of the packaging structure of the semiconductor device can be lowered. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The accompanying drawings included are used to provide a further understanding of the present disclosure and are incorporated into this specification to form a part of this specification. The drawings illustrate embodiments of the present disclosure and are used to explain the principles of the present disclosure together with the following description.

[0025] Figure 1 A cross-sectional view showing the packaging structure of a duplexer according to the prior art is shown.

[0026] Figure 2 A cross-sectional view showing the packaging structure of a duplexer according to an embodiment of the present disclosure is shown.

[0027] Figure 3 A flowchart showing the packaging method of a duplexer according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0028] In this specification, it will also be understood that when a component is referred to as being relative to other components, such as "on", "connected to", or "coupled to" other components, the one component may be directly disposed on the one component, directly connected to, or directly coupled to the one component, or there may also be an intervening third component. In contrast, when a component is referred to as being relative to other components in this specification, such as "directly" "on", "directly connected to", or "directly coupled to" other components, there is no intervening component between them.

[0029] The present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which various embodiments are shown. However, the present disclosure may be implemented in many different ways and should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art. The same reference numerals throughout the drawings denote the same components. Furthermore, in the drawings, the thickness, ratio, and dimensions of the components are enlarged for clarity of illustration.

[0030] The terms used herein are for the purpose of describing particular embodiments only and are not intended to be limiting. Unless the context clearly dictates otherwise, as used herein, "a", "an", "the", and "at least one" are not intended to limit the quantity but are intended to include both the singular and the plural. For example, unless the context clearly dictates otherwise, the meaning of "a component" is the same as that of "at least one component". "At least one" should not be construed as being limited to the quantity "one". "Or" means "and / or". The term "and / or" includes any and all combinations of one or more of the associated listed items.

[0031] Furthermore, terms such as "below", "beneath", "above", "on" are used to describe the positional relationship of components shown in the figures. These terms can be relative concepts and are described based on the directions presented in the figures.

[0032] Unless otherwise defined, all terms used herein, including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms defined in commonly used dictionaries should be construed as having the same meaning as in the relevant technical context, and these terms are not to be construed in an idealized or overly formal sense as having a formal meaning unless explicitly defined in the specification.

[0033] "Comprising" or "including" means specifying the nature, quantity, steps, operations, components, parts, or combinations thereof, but does not exclude other natures, quantities, steps, operations, components, parts, or combinations thereof.

[0034] Embodiments are described herein with reference to cross-sectional views of idealized embodiments. Thus, shape variations are anticipated as a result of, for example, manufacturing techniques and / or tolerances. Accordingly, the embodiments described herein should not be construed as being limited to the specific shapes of the regions shown herein, but should include shape deviations resulting from, for example, manufacturing. For example, regions shown or described as flat may typically have rough and / or non-linear features. Also, the sharp angles shown may be rounded. Thus, the regions shown in the figures are schematic in nature, and their shapes are not intended to show the exact shape of the regions and are not intended to limit the scope of the claims.

[0035] Hereinafter, exemplary embodiments according to the present disclosure will be described with reference to the accompanying drawings.

[0036] Figure 2 A cross-sectional view of a package structure 200 of a semiconductor device according to an embodiment of the present disclosure is shown.

[0037] As Figure 2As shown, according to an embodiment of the present disclosure, the packaging structure 200 includes a substrate 201, a first semiconductor device 202, a first conductive bump 203, a second semiconductor device 204, a second conductive bump 205, and a packaging colloid 206.

[0038] According to an embodiment of the present disclosure, the substrate 201 may be a packaging substrate or a lead frame made of at least one material selected from resin, ceramic, and metal.

[0039] In addition, as Figure 2 shown, according to an embodiment of the present disclosure, a redistribution layer (RDL) and a through-silicon via (TSV) may be provided in the substrate 201 to achieve electrical extension in the horizontal direction parallel to the surface of the substrate 201 and in the vertical direction perpendicular to the surface of the substrate 201, respectively.

[0040] According to an embodiment of the present disclosure, a soldering area is provided on the upper surface of the substrate 201, and pads for connecting to the first conductive bump 203 and the second conductive bump 205 are provided therein. In addition, according to an embodiment of the present disclosure, pads for external connection may also be provided on the lower surface of the substrate 201 opposite to the upper surface. According to an embodiment of the present disclosure, the pads may be formed of at least one material selected from silver, copper, nickel, palladium, and gold.

[0041] As Figure 2 shown, according to an embodiment of the present disclosure, the first semiconductor device 202 is disposed on the upper surface of the substrate 201. According to an embodiment of the present disclosure, the first semiconductor device 202 includes a first die 2021 and a first cover plate 2022, and the first die 2021 is bonded to the upper surface of the first cover plate 2022. According to an embodiment of the present disclosure, the first die 2021 may be a die manufactured on a wafer. For example, according to an embodiment of the present disclosure, the first die 2021 may be a transmit filter included in a duplexer. Correspondingly, as will be described below, the second die 2041 included in the second semiconductor device 204 may be a receive filter included in a duplexer. However, the present disclosure is not limited thereto, and the first die 2021 may also be a receive filter included in a duplexer, and correspondingly, the second die 2041 may be a transmit filter included in a duplexer.

[0042] According to an embodiment of the present disclosure, the wafer for fabricating the first die 2021 may be made of at least one material selected from the following: silicon, gallium arsenide, gallium nitride, and lithium tantalate. According to an embodiment of the present disclosure, the first cover plate 2022 is used to support and protect the first die 2021, and provides an electrical connection between the first die 2021 and an external component such as the first conductive bump 203 described below. According to an embodiment of the present disclosure, the first cover plate 2022 may have through-silicon vias and a redistribution layer for providing an electrical connection between the first die 2021 and the first conductive bump 203.

[0043] According to an embodiment of the present disclosure, the first cover plate 2022 may be made of a silicon material or a resin material.

[0044] As Figure 2 shown, according to an embodiment of the present disclosure, the first conductive bump 203 may be disposed on a pad on the lower surface of the first cover plate 2022 of the first semiconductor device 202, for electrically connecting the first die 2021 to a pad in the solder region of the substrate 201 via the first cover plate 2022. According to an embodiment of the present disclosure, the first conductive bump 203 may be made of copper (Cu), aluminum (Al), or an alloy thereof. Additionally, according to an embodiment of the present disclosure, the first conductive bump 203 may be formed in a cylindrical shape, but the present disclosure is not limited thereto.

[0045] According to an embodiment of the present disclosure, the electrical connection between the first conductive bump 203 and the pad in the solder region of the substrate 201 may be achieved by using a flip-chip bonding process with solder balls 207. According to an embodiment of the present disclosure, the solder balls 207 may be pre-formed on the top surface of the first conductive bump 203. According to an embodiment of the present disclosure, the solder balls 207 may be leaded solder balls or lead-free solder balls. According to an embodiment of the present disclosure, the solder balls 207 may be made of copper (Cu), nickel (Ni), tin (Sn), silver (Ag), or an alloy thereof. According to an embodiment of the present disclosure, the solder balls 207 may be, for example, solder balls, solder paste, or a solder layer, but the present disclosure is not limited thereto. Alternatively, the solder balls 207 may also be pre-formed on the pads in the solder region of the substrate 201 by a ball placement process.

[0046] According to an embodiment of the present disclosure, the first semiconductor device 202 provided with the first conductive bump 203 may be flip-chip bonded to the solder region of the substrate 201, for example, by a flip-chip bonding process. According to an embodiment of the present disclosure, the flip-chip bonding process may be at least one of a solder bonding process, a thermocompression bonding process, a thermosonic bonding process, and an adhesive bonding process.

[0047] Those skilled in the art should recognize that the first conductive bump 203 is not necessary, and the first semiconductor device 202 can be flip-chip bonded directly to the bonding area on the upper surface of the substrate 201 through solder balls 207, omitting the first conductive bump 203.

[0048] As Figure 2 shown, according to an embodiment of the present disclosure, the second semiconductor device 204 is disposed above the first semiconductor device 202. According to an embodiment of the present disclosure, the second semiconductor device 204 includes a second die 2041 and a first cover plate 2042, and the second die 2041 is bonded to the upper surface of the second cover plate 2042. According to an embodiment of the present disclosure, the second die 2041 can be a die fabricated on a wafer. For example, according to an embodiment of the present disclosure, the second die 2041 can be a receive filter included in a duplexer. However, the present disclosure is not limited thereto. As described above, the second die 2021 can also be a transmit filter included in a duplexer, and correspondingly, the first die 2021 can be a receive filter included in a duplexer.

[0049] According to an embodiment of the present disclosure, the wafer for fabricating the second die 2041 can be made of a material selected from at least one of the following: silicon, gallium arsenide, gallium nitride, and lithium tantalate. According to an embodiment of the present disclosure, the second cover plate 2042 is used to support and protect the second die 2041 and provide an electrical connection between the second die 2041 and an external component, such as the second conductive bump 205 described below. According to an embodiment of the present disclosure, the second cover plate 2042 can have through-silicon vias and a redistribution layer for providing an electrical connection between the second die 2041 and the second conductive bump 205.

[0050] According to an embodiment of the present disclosure, the second cover plate 2042 can be made of a silicon material or a resin material.

[0051] As Figure 2As shown, according to an embodiment of the present disclosure, a first region on the lower surface of the second encapsulation cover plate 2042 has a groove 2043 for accommodating the first semiconductor device 202. According to an embodiment of the present disclosure, at least a portion of the first semiconductor device 202 is accommodated in the groove 2043 in the first region on the lower surface of the second encapsulation cover plate 2042 of the second semiconductor device 204, thereby reducing the height and area of the overall package structure 200. According to an embodiment of the present disclosure, the size of the first semiconductor device 202 is smaller than the size of the groove 2043. According to an embodiment of the present disclosure, the shape of the groove 2043 may correspond to the shape of the first semiconductor device 202. According to an embodiment of the present disclosure, the groove 2043 in the first region on the lower surface of the second encapsulation cover plate 2042 may be formed by an etching process. In addition, since it is necessary to form the groove 2043 in the second encapsulation cover plate 2042, there is no need to perform a thinning process on the second encapsulation cover plate 2042, thus simplifying the packaging process steps.

[0052] As Figure 2 shown, according to an embodiment of the present disclosure, the second conductive bumps 205 may be disposed on pads in a second region on the lower surface of the second encapsulation cover plate 2042 of the second semiconductor device 204 for electrically connecting the second die 2041 to pads in the solder region of the substrate 201 via the second encapsulation cover plate 2042. According to an embodiment of the present disclosure, the second conductive bumps 205 may be made of copper (Cu), aluminum (Al), or an alloy thereof. In addition, according to an embodiment of the present disclosure, the second conductive bumps 205 may be formed in a cylindrical shape, but the present disclosure is not limited thereto.

[0053] In addition, as Figure 2 shown, according to an embodiment of the present disclosure, the first region on the lower surface of the second encapsulation cover plate 2042 having the groove 2043 for accommodating the first semiconductor device 202 may be located at the center of the lower surface of the second encapsulation cover plate 2043, and the second region on the lower surface of the second encapsulation cover plate 2042 where the second conductive bumps 205 are disposed may be located at the outer periphery of the lower surface of the second encapsulation cover plate 2043, but the present disclosure is not limited thereto.

[0054] In addition, although Figure 2The lower surface of the second cover plate 2042 is shown to have only one groove 2043 for accommodating one first semiconductor device 202, but the present disclosure is not limited thereto. According to other embodiments of the present disclosure, the lower surface of the second cover plate 2042 may have two or more grooves 2043 for two or more first semiconductor devices 202 respectively. According to other embodiments of the present disclosure, the lower surface of the second cover plate 2042 may have one groove 2043 for accommodating two or more first semiconductor devices 202. The above embodiments can be combined arbitrarily without departing from the spirit and scope of the present disclosure.

[0055] In addition, although embodiments of the present disclosure are described herein in connection with a duplexer including a transmit filter and a receive filter, the present disclosure is not limited thereto. The first semiconductor device 202 and the second semiconductor device 204 can be any semiconductor devices known in the art and are encapsulated in a package substrate by the stacking manner described above in connection with the embodiments of the present disclosure.

[0056] In addition, although embodiments of the present disclosure are described herein in connection with two layers of semiconductor devices stacked on each other, namely the first semiconductor device 202 and the second semiconductor device 204, the present disclosure is not limited thereto. Three or more layers of semiconductor devices can be provided and encapsulated in a package substrate by the stacking manner described above in connection with the embodiments of the present disclosure.

[0057] According to an embodiment of the present disclosure, similar to the first conductive bump 203, the electrical connection between the second conductive bump 205 and the pad in the welding area of the substrate 201 can be achieved by solder balls 207 using a flip-chip bonding process. According to an embodiment of the present disclosure, the solder balls 207 can be pre-formed on the top surface of the second conductive bump 205.

[0058] According to an embodiment of the present disclosure, the second semiconductor device 204 provided with the second conductive bump 203 can be flip-chip bonded to the welding area of the substrate 201, for example, by a flip-chip bonding process. According to an embodiment of the present disclosure, the flip-chip bonding process can be at least one of a solder bonding process, a thermocompression bonding process, a thermosonic bonding process, and an adhesive bonding process.

[0059] As Figure 2 shown, according to an embodiment of the present disclosure, in the vertical direction, the length of the second conductive bump 205 is greater than the length of the first conductive bump 203 to ensure that the first semiconductor device 202 and the second semiconductor device 204 can be encapsulated on the substrate 201 in a stacked manner.

[0060] As Figure 2As shown, according to an embodiment of the present disclosure, the encapsulating colloid 206 is arranged to cover the first semiconductor device 202, the first conductive bump 203, the second semiconductor device 204, and the second conductive bump 205. According to an embodiment of the present disclosure, the encapsulating colloid 206 may be formed of a curable resin material, but the present disclosure is not limited thereto. For example, the encapsulating colloid 206 may be a thermosetting resin such as phenolic resin, melamine formaldehyde resin, and epoxy resin, which has great fluidity before reaching the curing temperature and has a fast curing rate after reaching the curing temperature. According to an embodiment of the present disclosure, the encapsulating colloid 206 may be formed by a transfer molding process or a compression molding process.

[0061] Figure 3 The flowchart of a manufacturing method 300 of a filter according to an embodiment of the present disclosure is shown.

[0062] As Figure 3 shown by the solid-line box in, the manufacturing method 300 of an acoustic resonator according to an embodiment of the present disclosure includes the following steps:

[0063] S310: Prepare a substrate having a welding area on its upper surface;

[0064] S320: Flip-chip the first semiconductor device into the welding area through the first conductive bump. The first semiconductor device includes a first die and a first cover plate. The first die is bonded to the upper surface of the first cover plate. The first conductive bump is disposed on the pad on the lower surface of the first cover plate of the first semiconductor device for electrically connecting to the pad in the welding area;

[0065] S330: Flip-chip the second semiconductor device into the welding area above the first semiconductor device through the second conductive bump. The second semiconductor device includes a second die and a second cover plate. The second die is bonded to the upper surface of the second cover plate. The first area on the lower surface of the second cover plate has a groove for accommodating the first semiconductor device. The second conductive bump is disposed on the pad in the second area on the lower surface of the second cover plate of the second semiconductor device for electrically connecting to the pad in the welding area. The length of the second conductive bump is greater than the length of the first conductive bump; and

[0066] S340: Form an encapsulating colloid covering the first semiconductor device, the first conductive bump, the second semiconductor device, and the second conductive bump.

[0067] Each of the above steps of the manufacturing method of the filter according to the embodiment of the present disclosure can be respectively implemented by semiconductor processes known to those skilled in the art, such as deposition, etching, sputtering, electroplating, etc. Therefore, the specific process details are not described in more detail here.

[0068] According to the embodiment described above, by providing a groove in the cover plate of the semiconductor device located above for accommodating the semiconductor device located below, two semiconductor devices can be stacked and packaged on a substrate with a reduced height and area. Therefore, the size of the packaging structure of the semiconductor device can be reduced and the cost of the packaging structure of the semiconductor device can be lowered.

[0069] Although the present disclosure has been described with reference to exemplary embodiments of the present disclosure, those skilled in the art will understand that various modifications and variations can be made without departing from the spirit and scope of the present disclosure set forth in the claims.

Claims

1. A packaging structure of a semiconductor device, comprising: A substrate having a soldering area on an upper surface thereof; A first semiconductor device including a first die and a first cover plate, wherein the first die is bonded to an upper surface of the first cover plate; A first conductive bump disposed on a pad on a lower surface of the first cover plate of the first semiconductor device for electrically connecting to a pad in the soldering area; A second semiconductor device disposed above the first semiconductor device, including a second die and a second cover plate, wherein the second die is bonded to an upper surface of the second cover plate, and a first area on a lower surface of the second cover plate has a groove for accommodating the first semiconductor device; A second conductive bump disposed on a pad in a second area on a lower surface of the second cover plate of the second semiconductor device for electrically connecting to a pad in the soldering area, and the length of the second conductive bump is greater than the length of the first conductive bump; And A packaging colloid covering the first semiconductor device, the first conductive bump, the second semiconductor device, and the second conductive bump.

2. The encapsulation structure according to claim 1, wherein The substrate is a packaging substrate or a lead frame made of at least one material selected from resin, ceramic, and metal.

3. The encapsulation structure according to claim 1, wherein, The first die is one of a transmit filter and a receive filter in a duplexer, and the second die is the other of the transmit filter and the receive filter in the duplexer.

4. The encapsulation structure according to claim 1, wherein, The first cover plate has through-silicon vias and a redistribution layer for providing electrical connection between the first die and the first conductive bump, and Wherein, the second cover plate has through-silicon vias and a redistribution layer for providing electrical connection between the second die and the second conductive bump.

5. The encapsulation structure according to claim 1, wherein, The first area is located at the center of the lower surface of the second cover plate, and the second area is located at the outer periphery of the lower surface of the second cover plate.

6. The encapsulation structure according to claim 1, wherein, Each of the first conductive bump and the second conductive bump is made of copper, aluminum, or an alloy thereof.

7. The encapsulation structure according to claim 1, wherein, Each of the first conductive bump and the second conductive bump is electrically connected to a pad in the soldering area on the upper surface of the substrate by using a solder ball through at least one of a solder soldering process, a thermocompression bonding process, a thermosonic bonding process, and an adhesive bonding process.

8. The encapsulation structure according to claim 7, wherein, The solder ball is a leaded solder ball or a lead-free solder ball.

9. The encapsulation structure according to claim 7, wherein, The solder ball is made of copper, nickel, tin, silver, or an alloy thereof.

10. The encapsulation structure according to claim 7, wherein, The solder ball is disposed on a top surface of the first conductive bump and the second conductive bump.

11. The encapsulation structure according to claim 7, wherein, The solder ball is disposed on a pad in the soldering area on the upper surface of the substrate.

12. The encapsulation structure according to claim 1, wherein, Each of the first cover plate and the second cover plate is made of a silicon material or a resin material.

13. The encapsulation structure according to claim 1, wherein, The groove in the first area on the lower surface of the second cover plate is formed by an etching process.

14. The encapsulation structure according to claim 1, wherein, The packaging colloid is a curable resin material.

15. A packaging method for an electronic component, comprising: Preparing a substrate having a soldering area on an upper surface thereof; Flip the first semiconductor device in the solder region through the first conductive bumps, wherein the first semiconductor device includes a first die and a first cover plate, the first die is bonded to the upper surface of the first cover plate, and wherein the first conductive bumps are disposed on the pads on the lower surface of the first cover plate of the first semiconductor device for electrical connection to the pads in the solder region; Flip the second semiconductor device in the solder region above the first semiconductor device through the second conductive bumps, wherein the second semiconductor device includes a second die and a second cover plate, the second die is bonded to the upper surface of the second cover plate, a first region on the lower surface of the second cover plate has a groove for accommodating the first semiconductor device, and wherein the second conductive bumps are disposed on the pads in a second region on the lower surface of the second cover plate of the second semiconductor device for electrical connection to the pads in the solder region, and the length of the second conductive bumps is greater than the length of the first conductive bumps; and Form a molding compound covering the first semiconductor device, the first conductive bumps, the second semiconductor device, and the second conductive bumps.

Images