Electronic package and its carrier substrate

Abstract

An electronic package and its carrier substrate include a first signal layer and a second signal layer arranged in a circuit board body and stacked with each other so that the lengths and shapes of the first and second signal layers are consistent. Therefore, the wiring paths of the first and second signal layers can meet the requirements and the degree of noise cancellation between the signals of the two layers can meet the requirements.

Description

Technical Field

[0001] The present invention relates to a semiconductor packaging structure, and in particular to an electronic packaging component and a carrier substrate thereof. Background Art

[0002] Conventional semiconductor package substrates have multiple circuits configured inside according to functional requirements, such as circuits with signal transmission, grounding, and power functions.

[0003] Figure 1A FIG. 1 is a cross-sectional view of an existing packaging substrate 1. Figure 1A As shown, the package substrate 1 includes: a core layer 10, at least one conductive via 100 penetrating the core layer 10, and a build-up structure 11 formed on the core layer 10 and electrically connected to the conductive via 100. The build-up structure 11 has a plurality of dielectric layers 110, a plurality of circuit layers 111 disposed on the dielectric layers 110, and a plurality of conductive blind vias 112 disposed in the dielectric layers 110 and electrically connected to the circuit layers 111.

[0004] The build-up structure 11 is provided with a differential signal portion 12 on the circuit layer 111 contacting the core layer 10, which includes a first signal line 13a for inputting signals, a second signal line 13b for outputting signals, a first ground line 14a, and a second ground line 14b. The first signal line 13a and the second signal line 13b are used as a signal group, and the signal transmission directions through the first signal line 13a and the second signal line 13b are respectively in opposite directions of one input and one output, and the wiring paths of the first signal line 13a and the second signal line 13b are designed to be substantially similar and of equal length (e.g., Figure 1B As shown), the noise between the two signals is canceled out as much as possible, and a first grounding line 14a and a second grounding line 14b are respectively configured outside the first signal line 13a and the second signal line 13b (as shown). Figure 1C As shown), a ground layer 120 is respectively configured on the upper and lower sides of the differential signal portion 12 to shield the signals of the first signal line 13a and the second signal line 13b, so that the signals of the first signal line 13a and the second signal line 13b are not interfered with by external signals or noise.

[0005] However, in the conventional differential signal section 12, the wiring paths of the first signal line 13a and the second signal line 13b often cannot meet the actual design requirements. For example, in order to match the configuration of other lines, the first signal line 13a and the second signal line 13b need to be bent (such as Figure 1BIf the two need to be arranged symmetrically or in parallel, they cannot be of equal length. If they are to be arranged in equal length, not only is it time-consuming to design their respective routing paths (which also requires consideration of the routing of other functional circuits), but symmetrical or parallel routing is also difficult. Therefore, conventional differential signaling sections 12 often fail to meet the design requirements of identical routing paths and equal lengths for the first signal line 13a and the second signal line 13b, resulting in a degree of noise cancellation between the two signals that fails to meet practical requirements.

[0006] In addition, the signal group of the differential signal unit 12 is configured on the same circuit layer 111, so that the layout area of ​​the core layer 10 needs to take into account the layout paths of the first signal line 13a, the second signal line 13b, the first ground line 14a and the second ground line 14b. Therefore, it is difficult to reduce the layout area of ​​the core layer 10, resulting in the packaging substrate 1 being difficult to meet the requirements of miniaturization.

[0007] Therefore, how to overcome the various problems of the above-mentioned prior art has become a topic that needs to be solved urgently. Summary of the Invention

[0008] In view of the above-mentioned various defects of the prior art, the present invention provides an electronic package and a carrier substrate thereof, so that the degree of noise cancellation between the signals of the two can meet the requirements.

[0009] The carrier substrate of the present invention includes: a circuit board body; a first signal layer, which is arranged in the circuit board body and is used to transmit differential signals; and a second signal layer, which is arranged in the circuit board body and stacked at intervals on one side of the first signal layer and is used to transmit differential signals.

[0010] In the aforementioned carrier substrate, the circuit board body includes an insulating portion and a circuit portion combined with the insulating portion, so that the circuit portion is electrically connected to the first signal layer and the second signal layer.

[0011] In the aforementioned carrier substrate, the circuit board body includes a core layer having opposing first and second surfaces and at least one conductive via connecting the first and second surfaces. A build-up structure is formed on the first and second surfaces, with the first and second signal layers disposed within the build-up structure. For example, the first signal layer is located on the first surface of the core layer, and the second signal layer is located on the second surface of the core layer. Furthermore, ground circuits may be provided on both sides of the first and second signal layers.

[0012] The aforementioned carrier substrate further includes a first ground layer disposed in the circuit board body and stacked at intervals on the other side of the first signal layer.

[0013] The aforementioned carrier substrate further includes a second ground layer disposed in the circuit board body, which is stacked with the second signal layer in an interval.

[0014] The present invention further provides an electronic package, comprising: the aforementioned carrier substrate; and an electronic component, which is combined with the carrier substrate and electrically connected to the carrier substrate.

[0015] In the aforementioned electronic package, the electronic component is electrically connected to the first signal layer and the second signal layer.

[0016] The aforementioned electronic package further includes a plurality of conductive elements combined with the carrier substrate.

[0017] As can be seen from the above, in the electronic package and its carrier substrate of the present invention, the second signal layer is mainly stacked on one side of the first signal layer to make the length and shape of the two consistent. Therefore, compared with the prior art, the wiring paths of the first signal layer and the second signal layer of the present invention can meet the requirements, so that the degree of noise cancellation between the signals of the two meets the requirements.

[0018] In addition, by stacking the first signal layer and the second signal layer, the single-layer circuit layout area of ​​the carrier substrate only needs to consider the layout path of the first or second signal layer. Therefore, compared with the existing technology, the carrier substrate can effectively reduce its layout area, which is conducive to the miniaturization of the carrier substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1A It is a cross-sectional schematic diagram of an existing packaging substrate.

[0020] Figure 1B for Figure 1A A partial top view schematic diagram of .

[0021] Figure 1C for Figure 1A A partial three-dimensional schematic diagram of .

[0022] Figure 2A It is a cross-sectional schematic diagram of the carrier substrate of the present invention.

[0023] Figure 2B for Figure 2A A partial three-dimensional schematic diagram of .

[0024] Figure 3 FIG. 4 is a comparison curve diagram of the insertion loss of the carrier substrate of the present invention and the conventional packaging substrate.

[0025] Figure 4 It is a schematic cross-sectional view of the electronic package of the present invention.

[0026] Description of Reference Numerals

[0027] 1: Package substrate

[0028] 10: Core layer

[0029] 100: conductive through hole

[0030] 11: Layered structure

[0031] 110: dielectric layer

[0032] 111: Circuit layer

[0033] 112: Conductive blind hole

[0034] 12: Differential signal department

[0035] 120: Ground layer

[0036] 13a: First signal line

[0037] 13b: Second signal line

[0038] 14a: First grounding line

[0039] 14b: Second ground line

[0040] 2: Carrier substrate

[0041] 2a: Circuit board body

[0042] 2b: Insulation

[0043] 2c: Line Department

[0044] 20: Core layer

[0045] 20a: first surface

[0046] 20b: Second surface

[0047] 200: conductive through hole

[0048] 200': Pad

[0049] 21: First layer structure

[0050] 210: first dielectric layer

[0051] 211: First circuit layer

[0052] 211',221': Grounding line

[0053] 212: First conductive blind hole

[0054] 213: first insulating protective layer

[0055] 214: Electrical contact pad

[0056] 22: Second layer structure

[0057] 220: second dielectric layer

[0058] 221: Second circuit layer

[0059] 222: Second conductive blind hole

[0060] 223: Second insulating protective layer

[0061] 224:Ball pad

[0062] 31: First signal layer

[0063] 32: Second signal layer

[0064] 41: First ground layer

[0065] 42: Second ground layer

[0066] 5: Electronic packaging

[0067] 50: Electronic components

[0068] 500: conductive bump

[0069] 51: Conductive element

[0070] 52: Encapsulation layer

[0071] P1, P2: decibel ratio

[0072] Y: Arrow direction. DETAILED DESCRIPTION

[0073] The following describes the embodiments of the present invention through specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.

[0074] It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings attached to this specification are only used to match the contents disclosed in the specification for the understanding and reading of those skilled in the art, and are not used to limit the conditions under which the present invention can be implemented. Therefore, they have no substantial technical significance. Any modification of the structure, change in the proportional relationship, or adjustment of the size should still fall within the scope of the technical content disclosed by the present invention without affecting the efficacy and purpose that can be achieved by the present invention. At the same time, the terms such as "on", "first", "second" and "one" quoted in this specification are only for the convenience of description and are not used to limit the scope of the implementation of the present invention. Changes or adjustments in their relative relationships should also be regarded as the scope of the implementation of the present invention without substantially changing the technical content.

[0075] Figures 2A to 2B Schematic diagram of the carrier substrate 2 of the present invention. Figure 2AAs shown, the carrier substrate 2 includes: a circuit board body 2 a , a first signal layer 31 , a second signal layer 32 , a first ground layer 41 and a second ground layer 42 disposed in the circuit board body 2 a .

[0076] In this embodiment, the circuit board body 2a includes an insulating portion 2b and a circuit portion 2c connected to the insulating portion 2b, and the circuit portion 2c is electrically connected to the second ground layer 42, the second signal layer 32, the first signal layer 31 and the first ground layer 41.

[0077] For example, the circuit board body 2a includes a core layer 20 having a first surface 20a and a second surface 20b relative to each other and at least one conductive through-hole 200 connecting the first surface 20a and the second surface 20b, and a first build-up layer structure 21 and a second build-up layer structure 22 are formed on the first surface 20a and the second surface 20b, respectively, so that the second ground layer 42, the second signal layer 32, the first signal layer 31 and the first ground layer 41 are arranged in the first build-up layer structure 21 and the second build-up layer structure 22.

[0078] Furthermore, the first build-up structure 21 includes a plurality of first dielectric layers 210, a plurality of first circuit layers 211 disposed on the first dielectric layers 210, and a plurality of first conductive blind vias 212 disposed in the first dielectric layers 210 and electrically connecting the first circuit layers 211. A first insulating protective layer 213, such as a solder mask, may be formed on the outermost side of the first build-up structure 21, such that a portion of the first circuit layers 211 is exposed from the first insulating protective layer 213, thereby providing electrical contact pads 214. For example, the first circuit layer 211 may be a fan-out redistribution layer (RDL), and the dielectric material of the first dielectric layer 210 may be polybenzoxazole (PBO), polyimide (PI), or prepreg (PP).

[0079] Similarly, the second build-up structure 22 includes a plurality of second dielectric layers 220, a plurality of second circuit layers 221 disposed on the second dielectric layers 220, and a plurality of second conductive blind vias 222 disposed in the second dielectric layers 220 and electrically connecting the second circuit layers 221. A second insulating protective layer 223, such as a solder mask, may be formed on the outermost side of the second build-up structure 22, such that a portion of the second circuit layers 221 is exposed from the second insulating protective layer 223, thereby serving as ball implant pads 224. For example, the second circuit layer 221 may be a fan-out redistribution layer (RDL), and the dielectric material of the second dielectric layer 220 may be polybenzoxazole (PBO), polyimide (PI), or prepreg (PP).

[0080] Therefore, in this embodiment, the insulating portion 2b includes the core layer 20, the first dielectric layer 210, the first insulating protective layer 213, the second dielectric layer 220, and the second insulating protective layer 223, and the circuit portion 2c includes the conductive via 200, the first circuit layer 211, the first conductive blind via 212, the second circuit layer 221, and the second conductive blind via 222. It should be understood that the circuit board body 2a can be constructed in a variety of forms, such as a coreless form, and therefore its structure is not limited to the above.

[0081] The first signal layer 31 is disposed on the first surface 20 a of the core layer 20 and is electrically connected to the first circuit layer 211 .

[0082] In this embodiment, the first signal layer 31 includes at least one wire (such as Figure 2B For example, when the first build-up structure 21 is fabricated with the innermost first circuit layer 211, the first signal layer 31 can also be fabricated.

[0083] The second signal layer 32 is disposed on the second surface 20 b of the core layer 20 and is electrically connected to the second circuit layer 221 .

[0084] In this embodiment, the second signal layer 32 includes at least one wire (such as Figure 2B ), which is used to transmit differential signals, and the second signal layer 32 is stacked on one side of the first signal layer 31. For example, when the second build-up structure 22 is formed when the innermost second circuit layer 221 is formed, the second signal layer 32 can be formed at the same time, so that the second signal layer 32 and the first signal layer 31 are stacked on each other with the core layer 20 interposed therebetween.

[0085] The first ground layer 41 is disposed on the first dielectric layer 210 and electrically connects the first circuit layer 211 and the first conductive blind via 212 .

[0086] In this embodiment, the first ground layer 41 includes a piece of Figure 2B ), which is stacked on the other side of the first signal layer 31. For example, when the first build-up structure 21 is fabricated with the outer first circuit layer 211, the first ground layer 41 can be fabricated simultaneously, so that the first ground layer 41 and the first signal layer 31 are stacked with each other through the first dielectric layer 210.

[0087] The second ground layer 42 is disposed on the second dielectric layer 220 and electrically connects the second circuit layer 221 and the second conductive blind via 222 .

[0088] In this embodiment, the second ground layer 42 includes a piece of Figure 2B As shown), it is stacked with the second signal layer 32 to be spaced apart from each other so as to be spaced apart from each other along a direction (as shown Figure 2A The second ground layer 42, the second signal layer 32, the first signal layer 31, and the first ground layer 41 are stacked in sequence (as shown in the arrow direction Y from bottom to top). For example, when the second build-up structure 22 is fabricated with the outer second circuit layer 221, the second ground layer 42 can be fabricated simultaneously, so that the second ground layer 42 and the second signal layer 32 are stacked with each other separated by the second dielectric layer 220.

[0089] In addition, the conductive via 200 is electrically connected to the first conductive blind via 212 and the second conductive blind via 222 through the pad portion 200 ′, so that the conductive via 200 is electrically connected to the first ground layer 41 and the second ground layer 42 .

[0090] Therefore, the carrier substrate 2 of the present invention is configured by stacking the first signal layer 31 and the second signal layer 32, that is, the differential signal line adopts a vertical layout, so that the length and shape of the upper line (such as the first signal layer 31) and the lower line (such as the second signal layer 32) of the differential signal group are consistent (such as Figure 2B As shown in FIG, the two are arranged in a mutually perpendicular projection manner. Therefore, compared with the prior art, the wiring paths of the first signal layer 31 and the second signal layer 32 of the present invention can meet the requirements, so that the degree of noise cancellation between the two signals meets the requirements, such as the noise of the differential signal can be completely eliminated. Specifically, with a design of a line width of 13 microns (um) and an impedance of 90 ohms, the insertion loss of the present invention is almost the same (0.6% @ 30GHz), and, as shown in FIG. Figure 3As shown, the decibel (dB) ratio P1 of the return loss of the present invention is much smaller than the decibel ratio P2 of the conventional return loss. For example, the return loss of the present invention is below -25dB, which is a good performance.

[0091] In addition, the carrier substrate 2 of the present invention stacks the first signal layer 31 and the second signal layer 32 on each other in upper and lower layers (such as the first surface 20a and the second surface 20b of the core layer 20), so that the layout area of ​​the first surface 20a of the core layer 20 only needs to consider the layout path of the first signal layer 31, and the layout area of ​​the second surface 20b only needs to consider the layout path of the second signal layer 32. Therefore, compared with the prior art, the layout area of ​​the core layer 20 can be reduced by 21%, thereby effectively reducing the layout area of ​​the core layer 20, which is conducive to the miniaturization of the carrier substrate 2.

[0092] In addition, if the layout area of ​​the core layer 20 is the same as that of the existing packaging substrate, the extra layout area of ​​the core layer 20 can be used to layout other functional circuits as needed to improve the area utilization of the carrier substrate 2 .

[0093] In addition, the first signal layer 31 and the second signal layer 32 are provided with a first ground layer 41 and a second ground layer 42 such as a ground plane on the upper and lower sides, and the first signal layer 31 and the second signal layer 32 can be provided with ground lines 211 ', 221 ' (such as Figure 2B As shown), the signals of the first signal layer 31 and the second signal layer 32 are shielded so that the signals of the first signal layer 31 and the second signal layer 32 are not interfered with by external signals or noises.

[0094] The present invention further provides an electronic package 5 , comprising a carrier substrate 2 and at least one electronic component 50 combined with the carrier substrate 2 .

[0095] The electronic component 50 is electrically connected to the carrier substrate 2 , such as electrically connected to the first signal layer 31 and the second signal layer 32 .

[0096] In this embodiment, the electronic component 50 is an active component, a passive component, or a combination thereof, and the active component is, for example, a semiconductor chip, while the passive component is, for example, a resistor, a capacitor, and an inductor. For example, the semiconductor chip is flip-chip mounted on the electrical contact pads 214 of the carrier substrate 2 via a plurality of conductive bumps 500, such as solder material, metal pillars, or other materials, to electrically connect the first circuit layer 211 and the first signal layer 31. The conductive bumps 500 can be coated with a primer (not shown) as needed. Alternatively, the electronic component 50 can be electrically connected to the electrical contact pads 214 via a plurality of bonding wires (not shown). Alternatively, the electronic component 50 can directly contact the electrical contact pads 214. It should be understood that there are many ways for the electronic component 50 to be electrically connected to the carrier substrate 2, and they are not limited to the above.

[0097] Furthermore, an encapsulation layer 52 can be formed on the carrier substrate 2 to encapsulate the electronic component 50. The encapsulation layer 52 can be made of an insulating material such as polyimide (PI), dry film, epoxy, or a molding compound. For example, the encapsulation layer 52 can be formed on the carrier substrate 2 using a liquid compound, injection, lamination, or compression molding.

[0098] It should be understood that the electronic component 50 can also be embedded in the carrier substrate 2 to omit the production of the packaging layer 52. Therefore, there are many ways to package the electronic component 50, and there is no particular limitation.

[0099] In one embodiment, the electronic package 5 further includes a plurality of conductive elements 51 coupled to the carrier substrate 2. For example, the conductive elements 51 contact and couple with the ball-planting pads 224 to electrically connect the second circuit layer 221.

[0100] In summary, the electronic package and its carrier substrate of the present invention are configured by stacking the first signal layer and the second signal layer so that the lengths and shapes of the two are consistent. Therefore, the wiring paths of the first signal layer and the second signal layer of the present invention can meet the requirements, so that the degree of noise cancellation between the signals of the two meets the requirements.

[0101] In addition, the carrier substrate of the present invention stacks the first signal layer and the second signal layer on upper and lower layers, so as to reduce the layout area of ​​the carrier substrate, thereby effectively miniaturizing the carrier substrate.

[0102] The above embodiments are intended only to illustrate the principles and effects of the present invention and are not intended to limit the present invention. Any person skilled in the art may modify the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be as set forth in the claims.

Claims

1. A carrier substrate, characterized in that: include: A circuit board body comprising an insulating core layer having a first surface and a second surface opposite to each other; A first signal layer is provided in the circuit board body and located on the first surface of the core layer for transmitting differential signals; as well as A second signal layer is provided in the circuit board body and is located on the second surface of the core layer. It is stacked on one side of the first signal layer and is used to transmit differential signals. The first signal layer and the second signal layer are arranged in a perpendicular projection manner to each other, and the length and shape of the first signal layer and the second signal layer are consistent.

2. The carrier substrate according to claim 1, wherein The circuit board body includes an insulating portion and a circuit portion combined with the insulating portion, so that the circuit portion is electrically connected to the first signal layer and the second signal layer.

3. The carrier substrate according to claim 1, wherein: The core layer also has at least one conductive through hole communicating with the first surface and the second surface, and a build-up layer structure is formed on the first surface and the second surface so that the first signal layer and the second signal layer are configured in the build-up layer structure.

4. The carrier substrate according to claim 1, wherein: The carrier substrate further includes grounding circuits disposed on both sides of the first signal layer and the second signal layer.

5. The carrier substrate according to claim 1, wherein The carrier substrate further includes a first ground layer disposed in the circuit board body and stacked at intervals on the other side of the first signal layer.

6. The carrier substrate according to claim 1, wherein: The carrier substrate further includes a second ground layer disposed in the circuit board body and stacked with the second signal layer.

7. An electronic package, characterized in that: include: The carrier substrate according to any one of claims 1 to 6; as well as The electronic component is combined with the carrier substrate and electrically connected to the carrier substrate.

8. The electronic package according to claim 7, wherein: The electronic component is electrically connected to the first signal layer and the second signal layer.

9. The electronic package according to claim 7, wherein: The electronic package further includes a plurality of conductive elements combined with the carrier substrate.

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