A semiconductor device, a manufacturing method thereof, a chip, and an electronic device

Abstract

The present disclosure provides a semiconductor device and a manufacturing method thereof, a chip, and an electronic device. The device includes a semiconductor substrate, a stacked metal layer, and an air gap, etc. The stacked metal layer is disposed above the semiconductor substrate, and a recess is disposed in the stacked metal layer. A first spacer is disposed in the recess and along the side of the stacked metal layer, and an air gap is disposed in the recess. The chip includes the device of any embodiment of the present disclosure. The electronic device includes the chip of any embodiment of the present disclosure. The manufacturing method includes forming a stacked metal layer above a semiconductor substrate, forming a recess in the stacked metal layer, forming a first spacer and a second spacer on the sidewall of the recess, forming a sacrificial layer between adjacent second spacers, and sequentially removing the second spacer and the sacrificial layer to form an air gap in the recess. The present disclosure can manufacture a large-size air gap on the stacked metal layer, thereby greatly improving the problem of chip performance deterioration caused by parasitic resistance and parasitic capacitance.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor devices, and more particularly, to a semiconductor device and a manufacturing method thereof, a chip, and an electronic device. BACKGROUND

[0002] At present, in order to improve the characteristics of the chip, it is often necessary to reduce the parasitic resistance and parasitic capacitance. Common technical means for reducing the parasitic resistance and parasitic capacitance include: using copper instead of aluminum as a component material of a conductive line to reduce the delay through copper interconnection, or using an oxide of low-k material as an insulating material. However, these means still limit the reduction of parasitic resistance and parasitic capacitance, and it is difficult to meet the actual application requirements. Therefore, some people have proposed a scheme of using an air gap as an insulating film. However, due to the limitations of conventional technology, it is very difficult to make an air gap and a semiconductor device structure that meet the design requirements. For example, the sizes of different metal layers are often different, and the distances between the metal layers are generally different. Conventional technology is difficult to make air gaps with the same shape in different areas, and the size of the air gap made is often small, which limits the insulation performance. SUMMARY

[0003] To solve the problems of conventional technology, such as small size of the air gap and difficulty in making air gaps with the same shape in different areas, the present disclosure innovatively provides a semiconductor device and a manufacturing method thereof, a chip, and an electronic device to achieve the purpose of making an air gap that meets the requirements.

[0004] To achieve the above technical purpose, the present disclosure provides a semiconductor device. The semiconductor device can include, but is not limited to, a semiconductor substrate, a stacked metal layer, an air gap, a first spacer, and an upper stop layer. At least one stacked metal layer is arranged above the semiconductor substrate, and a recess is arranged in the stacked metal layer. The first spacer is arranged in the recess and along the side surface of the stacked metal layer. The upper stop layer is deposited on the stacked metal layer, and the first spacer, the stacked metal layer, and the upper stop layer collectively enclose the air gap.

[0005] To achieve the above technical purpose, the present disclosure also provides a chip including the semiconductor device of any one of the embodiments of the present disclosure.

[0006] To achieve the above technical purpose, the present disclosure provides an electronic device including the chip of any one of the embodiments of the present disclosure. The electronic device includes, but is not limited to, a smart phone, a computer, a tablet computer, a wearable smart device, an artificial intelligence device, a mobile power supply, and the like.

[0007] To achieve the above technical purposes, the present disclosure provides a manufacturing method of a semiconductor device, which can include but is not limited to the following steps. At least one stacked metal layer is formed above a semiconductor substrate, a groove is formed in the stacked metal layer by etching, a first spacer and a second spacer are sequentially formed on the sidewall of the groove, a sacrificial layer is formed between adjacent second spacers, the second spacer and the sacrificial layer are sequentially removed, and a top stop layer is deposited on the stacked metal layer, so that the first spacer, the stacked metal layer and the top stop layer together enclose an air gap.

[0008] The present disclosure has the following advantages. Compared with the prior art, the present disclosure can manufacture a large-size air gap on the stacked metal layer as an insulating film with good insulation, thereby greatly improving the problem of poor performance of chips such as dynamic random access memory caused by parasitic resistance and parasitic capacitance.

[0009] The present disclosure can also provide an air gap with a certain shape and size for a semiconductor device, that is, an air gap with the same shape and size can be made in different regions of the stacked metal layer in the same layer or different layers to meet the actual design requirements of the semiconductor device.

[0010] The present disclosure can manufacture the required air gap structure without the need for complex processes, can meet the actual application requirements in various scenarios, and has the outstanding advantages of low processing cost, short process cycle, and suitability for large-area promotion and application of semiconductor devices. BRIEF DESCRIPTION OF DRAWINGS

[0011] Figure 1 A longitudinal cross-sectional structure schematic diagram of a semiconductor device after a groove is formed in the stacked metal layer is shown.

[0012] Figure 2 A longitudinal cross-sectional structure schematic diagram of a semiconductor device after a first spacer is formed on the inner sidewall of the groove is shown.

[0013] Figure 3 A longitudinal cross-sectional structure schematic diagram of a semiconductor device after a second spacer is formed on the outer sidewall of the first spacer and part of the inner sidewall of the groove is shown.

[0014] Figure 4 A longitudinal cross-sectional structure schematic diagram of a semiconductor device after a sacrificial layer is formed between adjacent second spacers and is etched back is shown.

[0015] Figure 5 A longitudinal cross-sectional structure schematic diagram of a semiconductor device after a protective layer is deposited and chemical mechanical planarization is performed is shown.

[0016] Figure 6 A longitudinal cross-sectional structure schematic diagram of a semiconductor device after the second spacer is removed is shown.

[0017] Figure 7 A longitudinal cross-sectional structure of a semiconductor device after removing the sacrificial layer is shown.

[0018] Figure 8 A longitudinal cross-sectional structure of a semiconductor device after depositing the upper stop layer is shown.

[0019] In the drawings,

[0020] 100, semiconductor substrate.

[0021] 200, lower stop layer.

[0022] 300, stacked metal layer; 301, recess.

[0023] 400, first spacer.

[0024] 500, second spacer.

[0025] 600, sacrificial layer.

[0026] 700, protective layer.

[0027] 800, air gap.

[0028] 900, upper stop layer. DETAILED DESCRIPTION

[0029] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it is to be understood that these descriptions are only exemplary and are not intended to limit the scope of the present disclosure. Also, in the following description, the description of well-known structures and techniques is omitted to avoid unnecessarily obscuring the concept of the present disclosure.

[0030] In the drawings, various structure diagrams according to embodiments of the present disclosure are shown. These diagrams are not drawn to scale, in which certain details are exaggerated for the purpose of clarity and precision, and certain details can be omitted. The shapes of various regions, layers, and their relative sizes and positional relationships shown in the drawings are only exemplary, and in actuality, they can be deviated due to manufacturing tolerances or technical limitations, and regions / layers having different shapes, sizes, and relative positions can be additionally designed by those skilled in the art according to actual needs.

[0031] In the context of the present disclosure, when a layer / element is referred to as being located "on" another layer / element, the layer / element can be directly located on the other layer / element, or an intervening layer / element can be present therebetween. In addition, if a layer / element is located "on" another layer / element in one orientation, it can be located "under" the other layer / element when the orientation is reversed.

[0032] In order to be able to manufacture air gaps that meet the product design requirements, the present disclosure provides a semiconductor device manufacturing method to provide air gaps with large sizes and meet the requirement of having the same shape air gaps in different areas, and further utilize the air gaps as an insulating film with better performance and improve the chip performance.

[0033] Specifically, to solve at least one problem existing in the prior art, the semiconductor device manufacturing method provided by the present disclosure can include but is not limited to the following steps.

[0034] As shown in Figure 1 A semiconductor substrate 100 is provided. A lower stop layer 200 and a stack metal layer 300 can be sequentially formed above the semiconductor substrate 100. In some embodiments of the present disclosure, the lower stop layer 200 is disposed on the semiconductor substrate 100, and the stack metal layer 300 can be disposed on the lower stop layer 200. More specifically, at least one stack metal layer 300 is formed above the semiconductor substrate 100, and a groove 301 is formed on the stack metal layer 300 by etching. The stack metal layer 300 includes each stack metal, and can have a metal interlayer dielectric (IMD) or other dielectric between adjacent stack metals. In a specific implementation of the present disclosure, each groove 301 can be formed by etching the metal interlayer dielectric between the stack metals. The process of forming the groove on the stack metal layer 300 by etching the metal interlayer dielectric is a mature process, and will not be described in detail in the present embodiment. As shown in Figure 1 The bottom wall of the groove 301 is the upper surface of the lower stop layer 200, and the side wall of the groove 301 is the side surface of the stack metal. In addition, the lower stop layer 200 is used to prevent metal ions in the stack metal layer 300 from diffusing into other layers, thereby improving the reliability of the semiconductor device. The material of the lower stop layer 200 in the present embodiment can be silicon nitride. It should be understood that although the stack metal layer 300 is shown as one layer in each figure, the technical solution provided by the present disclosure can obviously be used on a two-layer or more multi-layer stack metal layer structure.

[0035] As shown in Figure 2As shown, a first spacer 400 is formed on the sidewall of the groove 301. In this embodiment, the first spacer 400 is formed beside the stacked metal layer 300, and the height of the first spacer 400 is less than the height of the stacked metal layer 300. In this embodiment, the first spacer 400 with a certain thickness and shape is formed along the sidewall of the stacked metal layer 300 through a sidewall process. The specific shape and thickness of the first spacer 400 can be determined according to the shape and thickness of the air gaps 800 to be formed. It can be seen that when the shape and size of the groove 301 are determined, the specific shape and thickness of the first spacer 400 plays a very crucial role in determining the shape and size of the air gaps. In this embodiment, the size and shape of each air gap 800 can be adjusted by adjusting the size and shape of the first spacer 400. The sidewall process is a mature process and will not be described in detail in this embodiment. The material of the first spacer 400 in this embodiment can be, for example, silicon nitride.

[0036] like Figure 3 As shown, a second spacer 500 with a certain thickness and shape is formed on the outer wall of the first spacer 400 and the side wall of the groove 301. In this embodiment, the second spacer 500 is formed through a sidewall process. The second spacer 500 occupies part of the space that needs to be filled in the air gap, and the second spacer 500 needs to be removed in subsequent processes. In this embodiment, the material of the second spacer 500 can be an oxide, such as silicon oxide. The specific process of the sidewall process is a mature technology and will not be described in detail in this embodiment. In this embodiment, the first spacer 400 and the second spacer 500 are sequentially formed on the sidewall of the stacked metal layer 300 through a sidewall process. Figure 3 As shown, in some embodiments of this disclosure, the height of the second spacer 500 needs to be greater than the height of the first spacer 400.

[0037] like Figure 4 As shown, a sacrificial layer 600 is formed between adjacent second spacers 500. The sacrificial layer 600 also occupies part of the space that needs to be filled in the air gap, and is used to be removed in subsequent processes. In this embodiment, the sacrificial layer can be, for example, a spin-on hard mask (SOH). More specifically, the process of forming the sacrificial layer 600 between adjacent second spacers 500 includes: coating the sacrificial layer 600, and then etching back the sacrificial layer 600 so that the height of the sacrificial layer 600 is less than the height of the second spacer 500 and greater than or equal to the height of the first spacer 400.

[0038] like Figure 5As shown, in this embodiment, a protective layer 700 can be deposited. Since the height of the sacrificial layer 600 is less than the height of the second spacer 500, the second spacer 500 can be exposed after the protective layer 700 is subjected to chemical-mechanical planarization (CMP) treatment, so that the second spacer 500 can be removed in the next step. The material of the protective layer 700 in this embodiment can be, for example, silicon nitride.

[0039] like Figure 6 As shown, the second spacer 500 is removed to form a partial air gap. In this embodiment, the second spacer 500 is removed by etching, for example, by wet etching or dry etching to remove the second spacer 500 between the first spacer 400 and the sacrificial layer 600.

[0040] like Figure 7 As shown, the sacrificial layer 600 is removed to form an air gap 800 within the groove 301. Specifically, the sacrificial layer 600 can be removed by an ashing process. Etching gas can enter along the space formed after the removal of the second spacer 500. After the ashing process, an air gap 800 is formed between adjacent stacked metals. The air gap 800 consists of the space originally occupied by the second spacer 500 and the space originally occupied by the sacrificial layer 600. Obviously, the air gap 800 provided in this embodiment is very large, almost filling the entire groove 301 except for the space occupied by the first spacer 400. It can be seen that this embodiment can form a large-sized air gap 800 with a set shape and thickness, thereby forming a semiconductor device structure with a large air gap as shown in some embodiments of this disclosure, meeting the semiconductor device design requirements in different application scenarios.

[0041] like Figure 8 As shown, an upper stop layer 900 is deposited. This disclosure utilizes a first spacer 400, a stacked metal layer 300, and an upper stop layer 900 to collectively form an air gap 800. The shape of the air gap 800 can vary according to the shape of the first spacer 400. It is evident that this disclosure can utilize the fabricated air gap 800 as an insulating film with superior insulation properties, thereby effectively improving problems such as performance degradation in chips like dynamic random access memory caused by parasitic capacitance and resistance. This effectively solves the problems of conventionally fabricated air gaps often having small sizes and the difficulty in fabricating air gaps with the same shape in different areas. Furthermore, the upper stop layer 900 can be used to provide etching stop positions for other device layers above it. The material of the upper stop layer 900 can be, for example, silicon nitride.

[0042] like Figure 7 and Figure 8As shown, based on the same inventive concept as the method for manufacturing semiconductor devices, one or more embodiments of the present disclosure can also provide a semiconductor device. The corresponding semiconductor device can be processed by one or more embodiments of the method for manufacturing semiconductor devices, and the semiconductor device can include, but is not limited to, a semiconductor substrate 100, a lower stop layer 200, a stacked metal layer 300, a first spacer 400, a protective layer 700, an air gap 800, and an upper stop layer 900, and the like.

[0043] The semiconductor substrate 100 can be, for example, a silicon substrate, a germanium substrate, or a silicon-germanium substrate, so that a plurality of memory cells can be formed on the semiconductor substrate 100. The lower stop layer 200, the stacked metal layer 300, the first spacer 400, the protective layer 700, the air gap 800, and the like are disposed on the semiconductor substrate 100.

[0044] The lower stop layer 200 is disposed on the upper surface of the semiconductor substrate 100, and the material of the lower stop layer 200 can include, but is not limited to, silicon nitride, silicon oxynitride, and / or silicon carbon nitride (SiCN), and the like. The lower stop layer 200 can be, for example, silicon nitride.

[0045] The stacked metal layer 300 is at least one layer and is disposed above the semiconductor substrate 100. The stacked metal layer 300 can be used to form part of a conductive line of a semiconductor device such as a dynamic random access memory, and the material thereof can be copper and / or aluminum, and the like. As shown, Figure 1 As shown, the recess 301 is disposed on the stacked metal layer 300.

[0046] The first spacer 400 is disposed in the recess 301 and also along the side surface of the stacked metal layer 300. In the case where the size of the recess 301 is determined, the larger the size of the first spacer 400 is, the smaller the size of the air gap 800 is, and the smaller the size of the first spacer 400 is, the larger the size of the air gap 800 is. Therefore, the first spacer 400 directly affects the thickness and size of the air gap 800 in the present embodiment, which also indicates that the size and shape of the air gap 800 can be adjusted as needed, and a large-size air gap 800 can be provided. In the case where the spacing between the stacked metals at different positions (which can be understood as the width of the recess 301) is different, one or more embodiments of the present disclosure can still make the air gaps at different positions have almost the same size and shape by adjusting the size of the first spacer 400; for example, the first spacer 400 is made larger when the width of the recess 301 is larger, and the first spacer 400 is made smaller when the width of the recess 301 is smaller, so that all the air gaps have a consistent shape and size. In addition, the material of the first spacer 400 in the present embodiment can be, for example, silicon nitride.

[0047] The protective layer 700 is disposed on the air gap 800, formed by deposition on the stacked metal layer 300, the second spacer 500 and the sacrificial layer 600 in the process of forming the air gap 800, and retained on the sacrificial layer 600 by etching back. The material of the protective layer 700 can be silicon nitride.

[0048] The air gap 800 is disposed in the recess, and more specifically, the air gap 800 in the embodiment fills the recess 301. As shown, the air gap 800 can surround the outside of the first spacer 400 and the side of the stacked metal layer 300 exposed in the recess 301 in the circumferential direction. Figure 8

[0049] The air gap 800 in the embodiment can be disposed between adjacent first spacers 400 and between adjacent upper stacked metals, so that the air gap 800 fills all the remaining space in the recess 301. The air gap 800 in the embodiment can be filled with a gaseous medium, and the dielectric constant of the gaseous medium is lower than that of silicon oxide. The dielectric constant of the gaseous medium in some embodiments of the disclosure can be less than 2.8, for example, the dielectric constant of the gaseous medium can be close to 1. The gaseous medium can be air with better insulation effect, of course, the air gap 800 in one or more embodiments of the disclosure can also contain two or more other media. It can be seen that the disclosure can set a large-size and shape-selectable air gap 800 as an insulating film beside the stacked metal layer 300, to significantly improve the performance of the semiconductor device, and effectively reduce the problem of parasitic capacitance and parasitic resistance in chips such as dynamic random access memory.

[0050] As shown, the upper stop layer 900 is disposed on the stacked metal layer 300. The upper stop layer 900 in the embodiment is deposited on the stacked metal layer 300. The first spacer 400, the stacked metal layer 300 and the upper stop layer 900 together enclose the air gap 800. The material of the upper stop layer 900 can include but is not limited to silicon nitride, silicon oxynitride and / or silicon carbon nitride (SiCN), and the material of the upper stop layer 900 can be the same as that of the protective layer 700, such as silicon nitride. Figure 8 One or more embodiments of the disclosure can provide a chip with a large-size air gap, which can include a semiconductor device in any embodiment of the disclosure.

[0051] The disclosure can also provide an electronic device including a chip in any embodiment of the disclosure. The electronic device can include but is not limited to a smart phone, a computer, a tablet computer, a wearable smart device, an artificial intelligence device, and a mobile power supply.

[0052]

[0053] ​​In the above description, the technical details of the patterning, etching, etc. of each layer are not described in detail. However, it should be understood by those skilled in the art that the layers, regions, etc. of the desired shape can be formed by various technical means. In addition, those skilled in the art can also design methods that are not exactly the same as the methods described above in order to form the same structure. In addition, although each embodiment is described separately above, this does not mean that the measures in each embodiment cannot be used advantageously in combination.

[0054] The embodiments of the present disclosure are described above. However, these embodiments are only for illustrative purposes, and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art can make various substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A method of manufacturing a semiconductor device, characterized by, include: At least one stacked metal layer is formed on top of the semiconductor substrate; A groove is formed within the stacked metal layers; A first spacer and a second spacer are formed sequentially on the sidewall of the groove; A sacrificial layer is formed between adjacent second spacers; Remove the second spacer and the sacrificial layer in sequence; A stop layer is deposited on the stacked metal layer so that the first spacer, the stacked metal layer, and the stop layer together form an air gap; The process of sequentially removing the second spacer and the sacrificial layer includes: Deposition protective layer; The protective layer is subjected to chemical mechanical planarization to expose the second spacer; The second spacer is etched and removed by dry etching or wet etching. The sacrificial layer is removed by ashing to create an air gap between adjacent stacked metals.

2. The method of manufacturing a semiconductor device according to claim 1, wherein The height of the second spacer is greater than the height of the first spacer; The process of forming a sacrificial layer between adjacent second spacers includes: Apply a sacrificial layer; The sacrificial layer is etched back so that the height of the sacrificial layer is less than the height of the second spacer and greater than or equal to the height of the first spacer.

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