Integrated Ultra-High Voltage Isolation Capacitor and Its Control Circuit

Abstract

An embodiment of the present invention provides an integrated ultra-high voltage isolation capacitor and its control circuit. The ultra-high voltage isolation capacitor is located on the surface of the silicon substrate and includes a first electrode plate, a second electrode plate, a first dielectric, and a second dielectric. The first dielectric is located between the first silicon substrate and the first electrode plate, and the second dielectric is located between the first electrode plate and the second electrode plate. The first dielectric is composed of one or more layers of a first group of insulating dielectric layers stacked, and the second dielectric is composed of one or more layers of a second group of insulating dielectric layers stacked. The ratio of the total thickness of the second group of insulating dielectric layers to the sum of the ratio of the thickness of the second group of insulating dielectric layers to the dielectric constant of the corresponding dielectric layer is greater than the ratio of the total thickness of the first group of insulating dielectric layers to the sum of the ratio of the thickness of the first group of insulating dielectric layers to the dielectric constant of the corresponding dielectric layer. The first electrode plate is connected to the control circuit located on the silicon substrate, and the second electrode plate is coupled to the second silicon substrate through a bonding wire.

Description

Technical Field

[0001] The present invention relates to the field of electricity, and more particularly, to an integrated ultra-high voltage isolation capacitor and its control circuit. Background Art

[0002] Digital isolators are increasingly used in isolated signal transmission due to their high data rate, low transmission delay, low power consumption and other characteristics. The higher the isolation breakdown voltage of a digital isolator, the longer its service life and the higher its reliability under the operating voltage.

[0003] In the existing integrated isolation capacitor and circuit design, the inter-metal dielectric layer in the back-end process of the integrated circuit is usually used as the breakdown voltage dielectric (IMD). As the dielectric layer thickens, while the isolation breakdown voltage increases, the strength of the analog signal in the signal link also attenuates. Although the attenuation of the signal strength can be compensated by increasing the amplification factor of the receiving circuit amplifier, etc., since the interference signal is also amplified, this method will reduce the signal-to-noise ratio of the signal link, making the circuit more vulnerable to external electromagnetic signals, and instead reducing the reliability of the signal link, which goes against the original intention of increasing the breakdown voltage ability. Therefore, how to improve the breakdown voltage ability and the reliability of the signal link simultaneously is an urgent problem to be solved in this field. Summary of the Invention

[0004] In view of this, the present invention provides an integrated ultra-high voltage isolation capacitor and its control circuit to improve the problem that the breakdown voltage ability and the reliability of the signal link cannot be improved simultaneously in the existing integrated capacitor technology.

[0005] To achieve the above object, the present invention provides the following technical solutions:

[0006] An integrated ultra-high voltage isolation capacitor and its control circuit, wherein the ultra-high voltage isolation capacitor is located on the surface of a silicon substrate and includes a first electrode plate, a second electrode plate, a first dielectric, and a second dielectric. The first dielectric is located between the silicon substrate and the first electrode plate, and the second dielectric is located between the first electrode plate and the second electrode plate. The first dielectric is composed of one or more layers of a first group of insulating dielectric layers stacked, and the second dielectric is composed of one or more layers of a second group of insulating dielectric layers stacked. Moreover, the ratio of the total thickness of the second group of insulating dielectric layers to the sum of the thickness of the second group of insulating dielectric layers and the ratio of the corresponding dielectric layer permittivity is greater than the ratio of the total thickness of the first group of insulating dielectric layers to the sum of the thickness of the first group of insulating dielectric layers and the ratio of the corresponding dielectric layer permittivity.

[0007] A control circuit includes a first silicon substrate and a second silicon substrate. A first integrated ultra-high voltage isolation capacitor is disposed on the surface of the first silicon substrate. The first electrode plate of the first integrated ultra-high voltage isolation capacitor is connected to the control circuit located on the first silicon substrate, and the second electrode plate is coupled to the circuit of the second silicon substrate through a bonding wire. Optionally, a second integrated ultra-high voltage isolation capacitor is disposed on the surface of the second silicon substrate. The first electrode plate of the second integrated ultra-high voltage isolation capacitor is connected to the control circuit located on the second silicon substrate, and the second electrode plate is coupled to the circuit of the first silicon substrate through a bonding wire; preferably, it is connected to the second electrode plate of the first integrated ultra-high voltage capacitor disposed on the surface of the first silicon substrate.

[0008] The beneficial effects of the integrated ultra-high voltage isolation capacitor and its control circuit provided by the embodiments of the present invention are as follows:

[0009] The signal of the controller is transmitted from the first silicon substrate to the second silicon substrate through the integrated ultra-high voltage isolation capacitor. During the signal transmission process, the isolation capacitor formed by the first electrode plate, the second electrode plate, and the second dielectric is the signal transmission path; the parasitic capacitor formed by the first electrode plate, the silicon substrate, and the first dielectric is the main signal interference path. Since the ratio of the total thickness of the second group of insulating dielectric layers to the sum of the thickness of the second group of insulating dielectric layers and the ratio of the corresponding dielectric layer dielectric constant is greater than the ratio of the total thickness of the first group of insulating dielectric layers to the sum of the thickness of the first group of insulating dielectric layers and the ratio of the corresponding dielectric layer dielectric constant; therefore, compared with the prior art, even if the total thickness of the second group of insulating dielectric layers is increased, the capacitance ratio of the isolation capacitor to the parasitic capacitor can still be increased, and the signal gain is correspondingly improved. Therefore, through the embodiments of the present invention, the breakdown voltage capability corresponding to the total thickness of the dielectric layer and the reliability of the signal link corresponding to the signal gain can be improved simultaneously. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0011] Figure 1 is a cross-sectional view of the integrated ultra-high voltage isolation capacitor and its control circuit provided by the first embodiment of the present invention

[0012] Figure 2 is a specific cross-sectional view of the first dielectric and the second dielectric of the integrated ultra-high voltage isolation capacitor provided by the first embodiment of the present invention;

[0013] Figure 3It is a cross-sectional view of an integrated ultra-high voltage isolation capacitor and its control circuit provided by the second embodiment of the present invention;

[0014] Figure 4 It is a simplified schematic diagram of the signal link principle of the second embodiment of the present invention;

[0015] Icons: 100 - silicon substrate; 101 - first electrode plate; 102 - second electrode plate; 101a - surface of the first electrode plate corresponding to the second electrode plate; 102a - surface of the second electrode plate corresponding to the first electrode plate; 111 - first dielectric; 112 - second dielectric; 1111, 1112 - first group of insulating dielectric layers; 1121, 1122, 1123, 1124 - second group of insulating dielectric layers; 170 - heavily doped region; 180 - control circuit (transmitter); 190 - bonding wire; 200 - second silicon substrate; 201 - first electrode plate of the second ultra-high voltage isolation capacitor; 202 - second electrode plate of the second ultra-high voltage isolation capacitor; 280 - control circuit (receiver). Specific embodiments

[0016] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. The following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the present invention to be protected, but only represents the selected embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts belong to the scope of protection of the present invention.

[0017] For details, see Figure 1 , Figure 1 shows a cross-sectional view of an integrated ultra-high voltage isolation capacitor and its control circuit provided by the first embodiment of the present invention. The ultra-high voltage capacitor is located on the surface of the silicon substrate 100 and has a first electrode plate 101 and a second electrode plate 102; a first dielectric 111 is located between the first electrode plate 101 and the silicon substrate 100, and a second dielectric 112 is located between the first electrode plate and the second electrode plate. The first electrode plate 101 is connected to the control circuit 180, and the control circuit can be a transmitter or a receiver. As an example, Figure 1 in the control circuit 180 is a transmitter circuit. The second electrode plate 102 is connected to the bonding wire 190, and the bonding wire 190 is coupled to the circuit of the second silicon substrate (not shown). The first electrode plate 101 is a conductor, the second electrode plate 102 is a conductor, the surface of the first electrode plate corresponding to the second electrode plate is 101a, the surface of the second electrode plate corresponding to the first electrode plate is 102a, and the surface 101a is parallel to the surface 102a, so as to achieve the purpose of maximizing the isolation withstand voltage.

[0018] Optionally, a heavily doped region 170 is provided in the region of the surface of the silicon substrate 100 corresponding to the first electrode plate 101. The doping type of the heavily doped region is optionally N-type heavy doping or P-type heavy doping. If it is an N-type heavy doping region, the heavily doped region 170 is preferably connected to the power supply voltage of the circuit on the surface of the silicon substrate 100; if it is a P-type heavy doping region, the heavily doped region 170 is preferably connected to the ground voltage of the circuit on the surface of the silicon substrate 100.

[0019] For the specific structural cross-sectional view of the first dielectric 111 and the second dielectric 112 of the integrated ultra-high voltage isolation capacitor, see Figure 2 . The first dielectric 111 is composed of one or more layers of the first group of insulating dielectric layers stacked. For the convenience of display, Figure 2 in the figure, taking 2 layers as an example, they are 1111 and 1112 respectively. Their thicknesses are d 11 、d 12 , and their dielectric constants are ℰ 11 、ℰ 12 respectively. The second dielectric 112 is composed of one or more layers of the second group of insulating dielectric layers stacked. For the convenience of display, Figure 2 in the figure, taking 4 layers as an example, they are 1121, 1122, 1123, and 1124 respectively. Their thicknesses are d 21 、d 22 、d 23 、d 24 , and their dielectric constants are ℰ 21 、ℰ 22 、ℰ 23 、ℰ 24 respectively.

[0020] And the first group of insulating dielectric layers and the second group of insulating dielectric layers satisfy the following conditions. The ratio of the total thickness of the second group of insulating dielectric layers to the sum of the ratios of the thickness of each layer of the second group of insulating dielectric layers to the corresponding layer dielectric constant is greater than the ratio of the total thickness of the first group of insulating dielectric layers to the sum of the ratios of the thickness of each layer of the first group of insulating dielectric layers to the corresponding layer dielectric constant. Taking the structure in Figure 2 as an example, that is:

[0021]

[0022] More generally, if the second group of insulating dielectric layers contains m layers of dielectrics and the first group of insulating dielectric layers contains n layers of dielectrics, it can be described as:

[0023]

[0024] For details, see Figure 3 , Figure 3Shows a cross-sectional view of the integrated ultra-high voltage isolation capacitor and its control circuit provided by the second embodiment of the present invention. The first silicon substrate 100 includes a first integrated ultra-high voltage capacitor, whose lower electrode plate 101 is connected to a control circuit ( Figure 3 taking the emitter 180 as an example in the figure), and the upper electrode plate 102 of the first integrated ultra-high voltage capacitor is coupled to the second silicon substrate 200 through a bonding wire 190. A second integrated ultra-high voltage capacitor is provided on the second silicon substrate 200, whose lower electrode plate 201 is connected to a control circuit ( Figure 3 taking the receiver 280 as an example in the figure), and its upper electrode plate 202 is coupled to the circuit of the first substrate through a bonding wire 190; preferably, it is connected to the second electrode plate of the first integrated ultra-high voltage capacitor provided on the surface of the first silicon substrate. Thus, it can be seen that two ultra-high voltage capacitors are connected in series between the first silicon substrate and the second silicon substrate, thereby further improving the voltage withstand capacity of the isolator.

[0025] Figure 4 Is a simplified schematic diagram of the signal link principle of the second embodiment. The voltage output by the emitter 180 on the first substrate is V1, and the voltage received by the receiver on the second substrate is V2. Refer to Figure 3 , the capacitance between the lower electrode plate 101 and the upper electrode plate 102 of the first high-voltage isolation capacitor is isolation capacitor 1, and its capacitance value is C m , the capacitance between the lower electrode plate 101 of the first high-voltage isolation capacitor and the first silicon substrate is parasitic capacitor 1, and its capacitance value is C p . Similarly, the capacitance between the lower electrode plate 201 and the upper electrode plate 202 of the second high-voltage isolation capacitor is isolation capacitor 2, and its capacitance value is C m , the capacitance between the lower electrode plate 201 of the second high-voltage isolation capacitor and the second silicon substrate is parasitic capacitor 2, and its capacitance value is C p . For the sake of simplifying the analysis, Figure 4 other parasitic parameters are not shown in the figure, but it does not affect the explanation of the working principle of the present invention.

[0026] From the first-order approximate calculation of time-domain analysis, the gain of the signal from V1 to V2 can be obtained as:

[0027]

[0028] In order to increase the isolation ability, usually the thickness of the second dielectric is increased as much as possible, resulting in a very small thickness of the first dielectric. Therefore, C p is generally much larger than C m , so the signal gain G is much less than 1. The higher the isolation voltage, the smaller C m , the smaller the received signal V2, and the lower the reliability of signal transmission.

[0029] The prior art uses the integrated circuit back-end metal interconnect layer (IMD) process to fabricate the dielectric layer. Generally, both the first dielectric and the second dielectric are silicon dioxide (dielectric constant 3.9). In some copper interconnect processes, some low dielectric constant dielectrics are also used as the dielectrics between metal layers, such as porous silicon dioxide or silicon dioxide doped with carbon elements, reducing the dielectric constant to about 3, resulting in C m being further reduced.

[0030] For example, if the distance from the lower plate of the capacitor to the substrate is 1 um and the dielectric is silicon dioxide; the distance from the upper plate to the lower substrate of the capacitor is 10 um and the dielectric is also silicon dioxide; then the breakdown voltage can be estimated to be 4 kV and the signal link gain is -26.4 dB.

[0031] If the capacitor structure proposed by the present invention is used, referring to Figure 2 the dielectric layer stack structure, using 4 layers of silicon dioxide containing nitrogen elements (dielectric constant between 4 - 7), it can be estimated that when the distance between the upper and lower substrates of the capacitor increases to 12 um, the isolation breakdown voltage increases from 4 kV to 4.8 kV, an increase of 20%; and the signal link gain increases from -26.4 dB to -23.8 dB, an increase of 2.6 dB. The thickness and dielectric constant of each dielectric layer are shown in the following table. It should be noted that the parameters in the following table are only examples used to illustrate the working principle and are not specific limitations on the content of the present invention.

[0032]

[0033] It can also be seen from the above table that the ratio of the total thickness of the second group of insulating dielectric layers to the sum of the ratios of the thickness of each layer of the second group of insulating dielectric layers to the corresponding layer dielectric constant (6.1 in this example) is greater than the ratio of the total thickness of the first group of insulating dielectric layers to the sum of the ratios of the thickness of each layer of the first group of insulating dielectric layers to the corresponding layer dielectric constant (3.7 in this example).

[0034] The above number of layers and the dielectric constant corresponding to each layer are all illustrative examples. Those skilled in the art can adjust the number of dielectric layers and the dielectric constant according to needs. For example, the total stress balance can be achieved by alternately stacking multiple dielectric layers with tensile stress and compressive stress. Since doping nitrogen elements into silicon dioxide can increase its dielectric constant and doping carbon elements into silicon dioxide can reduce its dielectric constant, therefore, preferably, the nitrogen element content in at least one layer of the second group of insulating dielectric layers is higher than that in one or more layers of the first group of insulating dielectric layers. Or, the carbon element content in at least one layer of the first group of insulating dielectric layers is higher than that in one or more layers of the second group of insulating dielectric layers.

[0035] Through the embodiments of the present invention, the breakdown voltage capability corresponding to the total thickness of the dielectric layer and the reliability of the signal link corresponding to the signal gain can be improved simultaneously, thus solving the problems existing in the prior art.

[0036] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention have been clearly and completely described above with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. Components of the embodiments of the present invention generally described and illustrated in the figures herein can be arranged and designed in a variety of different configurations.

[0037] Therefore, the detailed description of the embodiments of the present invention provided in the figures above is not intended to limit the scope of the claimed present invention, but merely represents selected embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts fall within the scope of protection of the present invention.

[0038] It should be noted that like reference numerals and letters denote like items in the following figures. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0039] In the description of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings or the orientation or positional relationship in which the inventive product is usually placed during use. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation of the present invention. In addition, the terms "first", "second", "third", etc. are only used for descriptive distinction and should not be construed as indicating or implying relative importance.

[0040] In the description of the present invention, it should also be noted that unless otherwise clearly specified and defined, the terms "set", "installed", "connected", and "coupled" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the internal communication of two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

Claims

1. An integrated ultra-high voltage isolation capacitor, characterized in that, The isolation capacitor is located on the surface of the silicon substrate and includes: a first electrode plate, a second electrode plate, a first dielectric, and a second dielectric; the first dielectric is located between the silicon substrate and the first electrode plate and is composed of one or more stacked first group of insulating dielectric layers, the second dielectric is located between the second electrode plate and the first electrode plate and is composed of one or more stacked second group of insulating dielectric layers, and the ratio of the total thickness of the second group of insulating dielectric layers to the sum of the ratios of the thickness of each layer of the second group of insulating dielectric layers to the corresponding layer dielectric constant is greater than the ratio of the total thickness of the first group of insulating dielectric layers to the sum of the ratios of the thickness of each layer of the first group of insulating dielectric layers to the corresponding layer dielectric constant; The content of nitrogen in at least one layer of the second group of insulating dielectric layers is higher than the content of nitrogen in one or more insulating dielectric layers of the first group of insulating dielectric layers; The content of carbon in at least one layer of the first group of insulating dielectric layers is higher than the content of carbon in one or more insulating dielectric layers of the second group of insulating dielectric layers.

2. The integrated ultra-high voltage isolation capacitor according to claim 1, wherein: The first electrode plate and the second electrode plate are conductors; and the surface of the first electrode plate corresponding to the second electrode plate is parallel to the surface of the second electrode plate corresponding to the first electrode plate.

3. The integrated ultra-high voltage isolation capacitor according to claim 1, characterized in that: A heavily doped region is provided in the region of the silicon substrate surface corresponding to the first electrode plate, and the doping type is N-type; and this heavily doped region is connected to the power supply voltage of the circuit on the silicon substrate surface.

4. The integrated ultra-high voltage isolation capacitor according to claim 1, characterized in that: A heavily doped region is provided in the region of the silicon substrate surface corresponding to the first electrode plate, and the doping type is P-type; and this heavily doped region is connected to the ground voltage of the circuit on the silicon substrate surface.

5. A control circuit, characterized in that: It includes a first silicon substrate and a second silicon substrate, wherein a first integrated ultra-high voltage isolation capacitor as described in claim 1 is provided on the surface of the first silicon substrate, the first electrode plate of the first integrated ultra-high voltage isolation capacitor is connected to the control circuit located on the first silicon substrate, and the second electrode plate is coupled to the circuit of the second silicon substrate through a bonding wire.

6. The control circuit according to claim 5, wherein: A second integrated ultra-high voltage isolation capacitor as described in claim 1 is provided on the surface of the second silicon substrate, the first electrode plate of the second integrated ultra-high voltage isolation capacitor is connected to the control circuit located on the second silicon substrate, the second electrode plate is coupled to the circuit of the first silicon substrate through a bonding wire and is connected to the second electrode plate of the first integrated ultra-high voltage capacitor provided on the surface of the first silicon substrate.

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