Nord flash memory device manufacturing process
In the Nord flash memory device manufacturing process, by first etching the polysilicon control gate layer to form a window, then depositing and etching the floating gate silicon nitride layer and oxide layer, and removing unnecessary dielectric layers, the problem of insufficient data current window caused by uneven etching stop surface is solved, and the read and write reliability of the device is improved.
Patent Information
- Application Number
- CN202210104685.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-01-28
- Publication Date
- 2025-10-03
- Estimated Expiration
- 2042-01-28
AI Technical Summary
During the etching process of existing Nord flash memory devices, the etch stop surface between the floating gate and the control gate is uneven, resulting in inconsistent control gate layer thickness, affecting the data 0 and data 1 current windows and reducing the device's read and write data reliability.
The first window is formed by etching the polysilicon control gate layer, and then the floating gate silicon nitride layer is deposited and etched to form the second window. After that, the oxide layer is deposited and the polysilicon inter-dielectric layer and oxide are removed with an acid wash solution to ensure the uniformity of the polysilicon control gate layer thickness.
The uniformity of the thickness of the polysilicon control gate layer is achieved, which avoids the unevenness problem caused by over-etching and improves the read and write data reliability of Nord flash memory devices.
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Figure CN114334989B_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor integrated circuit manufacturing technology, and in particular to a manufacturing process for a Nord flash memory device. Background Art
[0002] Nord Flash memory devices, with their low cost, low power consumption, and fast access speeds, have become increasingly important in the non-volatile memory market. With technological advancements, data storage media applications are shifting from traditional non-volatile memory to flash-based storage. Large-capacity solid-state storage devices using flash as the primary storage medium have become one of the mainstream data storage solutions today.
[0003] Typically, a Nord flash memory device consists of a stacked floating gate and control gate, with a composite dielectric layer formed between them. Read, write, and erase operations are controlled by applying different operating voltages to the control gate. The storage content of a Nord flash memory device depends on the state of the electrons stored on the floating gate in its storage structure. If the floating gate is empty, the data in the Nord flash memory device is 1; if the floating gate is empty, the data in the Nord flash memory device is 0.
[0004] When etching the floating gate silicon nitride layer located on the control gate layer, the Nord flash memory device manufacturing process of the related technology usually over-etches, so that the etch stop surface is located in the control gate layer. However, this over-etching easily makes the etch stop surface morphology uneven, resulting in inconsistent thickness of the remaining control gate layer, affecting the storage of electrons in the floating gate, and resulting in insufficient current windows for data 0 and data 1, which has an adverse impact on the reliability of reading and writing data in the Nord flash memory device. Summary of the Invention
[0005] The present application provides a manufacturing process for a Nord flash memory device, which can solve the problem in the related art that the current window for data 0 and the current window for data 1 are insufficient, which adversely affects the reliability of reading and writing data in the Nord flash memory device.
[0006] In order to solve the technical problems described in the background technology, the present application provides a process for manufacturing a Nord flash memory device, which comprises the following steps:
[0007] Step 1: Forming a polysilicon floating gate layer, a polysilicon inter-layer dielectric layer, and a polysilicon control gate layer stacked sequentially from bottom to top on the substrate;
[0008] Step 2: etching the polysilicon control gate layer to form a first window in the polysilicon control gate layer;
[0009] Step 3: depositing a floating gate silicon nitride layer according to the surface morphology of the polysilicon control gate layer with the first window;
[0010] Step 4: etching the floating gate silicon nitride layer to form a second window in the floating gate silicon nitride layer;
[0011] Step 5: depositing an oxide layer according to the surface morphology of the floating gate silicon nitride layer with the second window;
[0012] Step 6: etching the oxide layer;
[0013] Step 7: removing the inter-polysilicon dielectric layer at the first window position, and the oxide and silicon nitride at the sidewall position of the first window by an acid wash solution, so that the side surface of the polysilicon control gate layer and the upper surface of the polysilicon floating gate layer at the first window position are exposed;
[0014] Step 8: Fabricate the word line structure of the Nord flash memory device.
[0015] Optionally, in the second step of etching the polysilicon control gate layer to form a first window in the polysilicon control gate layer,
[0016] The upper surface of the inter-polysilicon dielectric layer located at the position of the first window is exposed.
[0017] Optionally, in the third step of depositing a floating gate silicon nitride layer according to the surface morphology of the polysilicon control gate layer with the first window,
[0018] The floating gate silicon nitride layer covers the surface of the remaining polysilicon control gate layer and the upper surface of the inter-polysilicon dielectric layer exposed from the position of the first window.
[0019] Optionally, in the fourth step of etching the floating gate silicon nitride layer to open a second window in the floating gate silicon nitride layer,
[0020] The first window and the polysilicon control gate layer on both sides of the first window are located in the second window, and the polysilicon control gate layer on both sides of the first window and the upper surface of the polysilicon inter-dielectric layer located in the first window are exposed from the second window.
[0021] Optionally, in the fifth step: in accordance with the surface morphology of the floating gate silicon nitride layer with the second window, in the step of depositing the oxide layer, the oxide layer covers the surface of the remaining floating gate silicon nitride layer and the surface of the polysilicon control gate layer exposed from the second window position, as well as the upper surface of the polysilicon inter-dielectric layer.
[0022] Optionally, in the sixth step of etching the oxide layer, the oxide layer on the side wall of the second window is retained.
[0023] Optionally, the seventh step of removing the inter-polysilicon dielectric layer at the first window position and the oxide and silicon nitride at the sidewall position of the first window by an acid wash solution to expose the side surface of the polysilicon control gate layer and the upper surface of the polysilicon floating gate layer at the first window position includes:
[0024] The inter-polysilicon dielectric layer at the first window position and the oxide and silicon nitride at the side wall position of the first window are removed by hydrofluoric acid and phosphoric acid, so that the side surface of the polysilicon control gate layer and the upper surface of the polysilicon floating gate layer at the first window position are exposed.
[0025] Optionally, after the seventh step of removing the inter-polysilicon dielectric layer at the first window position and the oxide and silicon nitride at the sidewall position of the first window by an acid wash solution, so that the side surface of the polysilicon control gate layer and the upper surface of the polysilicon floating gate layer at the first window position are exposed,
[0026] The second window with the first spacer structure formed on its sidewall and the first window with the inter-crystalline silicon dielectric layer removed together form a third window.
[0027] Optionally, the eighth step of manufacturing a word line structure of the Nord flash memory device includes the following steps:
[0028] forming a second sidewall structure on the sidewall of the third window;
[0029] Etching and removing the polysilicon floating gate layer located at the position of the third window and not covered by the second sidewall structure, so that the third window extends downward to form a fourth window;
[0030] so that a third sidewall structure is formed on the side surface of the polysilicon floating gate layer exposed from the fourth window;
[0031] Etching and removing the gate oxide layer located at the position of the fourth window and not covered by the third spacer structure, so that the etch stop layer is located in the gate oxide layer, and the fourth window extends downward to form a word line filling window;
[0032] The word line filling window is filled with word line polysilicon.
[0033] The technical solution of the present application has at least the following advantages: a polysilicon control gate layer is first etched to form a first window in the polysilicon control gate layer; a floating gate silicon nitride layer is then deposited according to the surface morphology of the polysilicon control gate layer with the first window; the floating gate silicon nitride layer is then etched to form a second window in the floating gate silicon nitride layer; an oxide layer is then deposited according to the surface morphology of the floating gate silicon nitride layer with the second window; after etching the oxide layer, the inter-polysilicon dielectric layer at the location of the first window and the oxide and silicon nitride at the sidewalls of the first window are removed by an acid wash solution, so that the side surfaces of the polysilicon control gate layer and the upper surface of the polysilicon floating gate layer at the location of the first window are exposed, thereby making the thickness of the polysilicon control gate layer uniform and avoiding related problems caused by unevenness of the polysilicon control gate layer due to over-etching. BRIEF DESCRIPTION OF THE DRAWINGS
[0034] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the specific implementation methods or the description of the prior art. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.
[0035] Figure 1 A flowchart of a manufacturing process of a Nord flash memory device provided by an embodiment of the present application is shown;
[0036] Figure 2 FIG. 4 shows a schematic cross-sectional structure diagram of the device after step S2 is completed;
[0037] Figure 3 FIG4 shows a schematic diagram of a cross-sectional structure of the device after step S4 is completed;
[0038] Figure 4 FIG. 4 shows a schematic cross-sectional structure diagram of the device after step S7 is completed;
[0039] Figure 5 FIG. 4 shows a schematic cross-sectional structure diagram of the device after step S81 is completed;
[0040] Figure 6 FIG. 4 shows a schematic cross-sectional structure diagram of the device after step S82 is completed;
[0041] Figure 7 FIG. 4 shows a schematic cross-sectional structure diagram of the device after step S85 is completed. DETAILED DESCRIPTION
[0042] The following is a clear and complete description of the technical solutions in this application in conjunction with the accompanying drawings. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of this application.
[0043] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate the description of this application and simplify the description. They do not indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0044] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to internal connections between two components; they can refer to wireless connections or wired connections. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.
[0045] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.
[0046] Figure 1 The process flow chart of the Nord flash memory device manufacturing process provided by an embodiment of the present application is shown. Figure 1 As can be seen from the figure, the manufacturing process of the Nord flash memory device includes the following steps:
[0047] Step S1: forming a polysilicon floating gate layer, a polysilicon inter-dielectric layer and a polysilicon control gate layer stacked in sequence from bottom to top on a substrate.
[0048] For example, the substrate may be a silicon substrate, wherein the inter-polysilicon dielectric layer may be a multi-layer structure, and when the inter-polysilicon dielectric layer is multi-layer, it includes a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer stacked sequentially from bottom to top.
[0049] A gate oxide layer may also be formed between the substrate and the polysilicon floating gate layer.
[0050] Step S2: etching the polysilicon control gate layer to form a first window in the polysilicon control gate layer.
[0051] Reference Figure 2 , which shows a schematic diagram of the cross-sectional structure of the device after step S2 is completed, Figure 2 As can be seen in the figure, the substrate 110 includes a gate oxide layer 101, a polysilicon floating gate layer 120, an inter-polysilicon dielectric layer 130, and a polysilicon control gate layer 140, which are stacked in sequence. A first window 150 is formed in the polysilicon control gate layer 140, and the upper surface of the inter-polysilicon dielectric layer 130 at the location of the first window 150 is exposed.
[0052] Step S3: depositing a floating gate silicon nitride layer according to the surface morphology of the polysilicon control gate layer with the first window.
[0053] The deposited floating gate silicon nitride layer covers the Figure 2 The surface of the remaining polysilicon control gate layer 140 shown in FIG. 1 and the upper surface of the polysilicon inter-layer dielectric 130 exposed at the position of the first window 150. The surface of the remaining polysilicon control gate layer 140 covered by the floating gate silicon nitride layer includes Figure 2 The upper surface of the remaining polysilicon control gate layer 140 and the side surface of the remaining polysilicon control gate layer 140 located at the position of the first window 150 are shown.
[0054] Step S4: etching the floating gate silicon nitride layer to form a second window in the floating gate silicon nitride layer.
[0055] Reference Figure 3 , which shows a schematic diagram of the cross-sectional structure of the device after step S4 is completed, Figure 3 As can be seen in the figure, a second window 170 is formed in the floating gate silicon nitride layer 160 , and the formed second window 170 is connected to the first window 150 .
[0056] The first window 150 and the polysilicon control gate layer 140 on both sides of the first window 150 are located in the second window 170. The polysilicon control gate layer 140 on both sides of the first window 150 and the upper surface of the polysilicon inter-dielectric layer 130 located in the first window 150 are exposed from the second window 170.
[0057] Due to the directionality of etching, after step S4 is completed, there will still be nitride residues such as the floating gate silicon nitride layer on the side surface of the remaining polysilicon control gate layer 140 at the position of the first window 150 ( Figure 3 not shown).
[0058] Step S5: depositing an oxide layer according to the surface morphology of the floating gate silicon nitride layer with the second window.
[0059] The oxide layer deposited by step S5 covers the upper surface of the remaining floating gate silicon nitride layer 160 and the surface of the second window 170, wherein the surface of the second window 170 includes the side surface of the floating gate silicon nitride layer 160 exposed from the second window 170, the side surface of the polysilicon control gate layer 140 exposed from the first window 150, and the upper surface of the polysilicon inter-dielectric layer 130 exposed from the first window 150.
[0060] Step S6: etching the oxide layer.
[0061] Due to the directionality of the etching, during step S6, the etching rate of the oxide layer covering the upper surface is greater than the etching rate of the oxide layer covering the side surfaces. Therefore, after step S6 is completed, the oxide layer covering the upper surface of the remaining floating gate silicon nitride layer 160 and the oxide layer covering the upper surface of the inter-polysilicon dielectric layer 130 exposed through the first window 150 are completely etched away, while the oxide layer covering the side surfaces of the floating gate silicon nitride layer 160 and the oxide layer covering the side surfaces of the polysilicon control gate layer 140 are retained.
[0062] Step S7: removing the inter-polysilicon dielectric layer at the first window position, and the oxide and silicon nitride at the sidewall position of the first window by an acid wash solution, so that the side surface of the polysilicon control gate layer and the upper surface of the polysilicon floating gate layer at the first window position are exposed.
[0063] After steps S4 and S6 are completed, nitride and oxide layers will remain on the side surfaces of the polysilicon control gate layer 140 (i.e., at the sidewalls of the first window), respectively. The oxide and silicon nitride on the sidewalls of the polysilicon control gate layer can be removed by an acid wash solution, exposing the side surfaces of the polysilicon control gate layer.
[0064] Optionally, the polysilicon inter-layer dielectric layer at the first window position and the oxide and silicon nitride at the first window sidewall position can be removed by using hydrofluoric acid and phosphoric acid removal pickling solution, so that the side surface of the polysilicon control gate layer and the upper surface of the polysilicon floating gate layer at the first window position are exposed.
[0065] Reference Figure 4 , which shows a schematic diagram of the cross-sectional structure of the device after step S7 is completed, Figure 4 As can be seen in FIG, after step S7 is completed, only the oxide layer covering the side surface of the floating gate silicon nitride layer 160 remains to form the first spacer structure 180. The first spacer structure 180 also covers the polysilicon control gate layer 140 on both sides of the first window 150.
[0066] Continue to refer to Figure 4 After step S7 is completed, the second window 170 with the first spacer structure 180 formed on the sidewall and the first window 150 with the intercrystalline silicon dielectric layer 130 removed together form a third window 190.
[0067] Step S8: manufacturing the word line structure of the Nord flash memory device.
[0068] Step S8 may be implemented by the following embodiment, including:
[0069] Step S81: forming a second sidewall structure on the sidewall of the third window formed after step S7.
[0070] Reference Figure 5 , which shows a schematic diagram of the cross-sectional structure of the device after step S81 is completed, Figure 5 As can be seen in FIG, after step S81 is completed, the sidewall of the third window 190 is covered with a second sidewall structure 200.
[0071] Step S82: etching and removing the polysilicon floating gate layer located at the position of the third window and not covered by the second sidewall structure, so that the third window extends downward to form a fourth window.
[0072] Reference Figure 6 , which shows a schematic cross-sectional structure diagram of the device after step S82 is completed, from Figure 6 It can be seen that in Figure 4 At the position of the third window 190, the polysilicon floating gate layer 120 not covered by the second sidewall structure 200 is etched away, thereby Figure 4 The third window 190 shown extends downward to form Figure 5 As shown in the fourth window 210 , the gate oxide layer 101 located at the position of the fourth window 210 is exposed.
[0073] In step S83 , a third spacer structure is formed on the side surface of the polysilicon floating gate layer exposed from the fourth window.
[0074] from Figure 6 It can be seen that after step S83 is completed, the side surface of the polysilicon floating gate layer 120 is exposed in the fourth window 210, and the third sidewall structure covers the side surface of the polysilicon floating gate layer exposed from the fourth window, and covers the upper surfaces of both ends of the gate oxide layer 101 exposed from the fourth window 210.
[0075] Step S84: etching and removing the gate oxide layer located at the fourth window position and not covered by the third spacer structure, so that the etch stop layer is located in the gate oxide layer, and the fourth window extends downward to form a word line filling window.
[0076] Step S85: Filling the word line filling window with word line polysilicon.
[0077] Reference Figure 7 , which shows a schematic diagram of the cross-sectional structure of the device after step S85 is completed, Figure 7 It can be seen from FIG. 1 that after step S84 , the etch stop layer 220 is located in the gate oxide layer 101 , and the word line filling window is fully filled with word line polysilicon 230 .
[0078] In this embodiment, a polysilicon control gate layer is first etched to form a first window in the polysilicon control gate layer. A floating gate silicon nitride layer is then deposited according to the surface morphology of the polysilicon control gate layer with the first window. The floating gate silicon nitride layer is then etched to form a second window in the floating gate silicon nitride layer. An oxide layer is then deposited according to the surface morphology of the floating gate silicon nitride layer with the second window. After etching the oxide layer, an inter-polysilicon dielectric layer at the location of the first window and oxide and silicon nitride at the sidewalls of the first window are removed using an acid wash solution, so that the side surfaces of the polysilicon control gate layer and the upper surface of the polysilicon floating gate layer at the location of the first window are exposed. This allows the thickness of the polysilicon control gate layer to be uniform, thereby avoiding related problems caused by unevenness of the polysilicon control gate layer due to over-etching.
[0079] Obviously, the above embodiments are merely examples for clarity of explanation and are not intended to limit the implementation methods. Those skilled in the art will appreciate that other variations or modifications can be made based on the above description. It is not necessary and impossible to enumerate all implementation methods here. Obvious variations or modifications arising therefrom remain within the scope of protection of this application.
Claims
1. A process for manufacturing a Nord flash memory device, characterized in that: Manufacturing process of the Nord flash memory device The following steps are involved: Step 1: Forming a polysilicon floating gate layer, a polysilicon inter-layer dielectric layer, and a polysilicon control gate layer stacked sequentially from bottom to top on the substrate; Step 2: etching the polysilicon control gate layer to form a first window in the polysilicon control gate layer; Step 3: depositing a floating gate silicon nitride layer according to the surface morphology of the polysilicon control gate layer with the first window; Step 4: etching the floating gate silicon nitride layer to form a second window in the floating gate silicon nitride layer; Step 5: depositing an oxide layer according to the surface morphology of the floating gate silicon nitride layer with the second window; Step 6: etching the oxide layer; Step 7: removing the inter-polysilicon dielectric layer at the first window position, and the oxide and silicon nitride at the sidewall position of the first window by an acid wash solution, so that the side surface of the polysilicon control gate layer and the upper surface of the polysilicon floating gate layer at the first window position are exposed; Step 8: Fabricate the word line structure of the Nord flash memory device.
2. The process for manufacturing a Nord flash memory device according to claim 1, wherein: The second step: etching the polysilicon control gate layer to form a first window in the polysilicon control gate layer, The upper surface of the inter-polysilicon dielectric layer located at the position of the first window is exposed.
3. The process for manufacturing a Nord flash memory device according to claim 1, wherein: The third step: depositing a floating gate silicon nitride layer according to the surface morphology of the polysilicon control gate layer with the first window, The floating gate silicon nitride layer covers the surface of the remaining polysilicon control gate layer and the upper surface of the inter-polysilicon dielectric layer exposed from the position of the first window.
4. The process for manufacturing a Nord flash memory device according to claim 1, wherein: In the fourth step of etching the floating gate silicon nitride layer to open a second window in the floating gate silicon nitride layer, The first window and the polysilicon control gate layer on both sides of the first window are located in the second window, and the polysilicon control gate layer on both sides of the first window and the upper surface of the polysilicon inter-dielectric layer located in the first window are exposed from the second window.
5. The process for manufacturing a Nord flash memory device according to claim 1, wherein: The fifth step: in the step of depositing an oxide layer according to the surface morphology of the floating gate silicon nitride layer with the second window, the oxide layer covers the surface of the remaining floating gate silicon nitride layer and the surface of the polysilicon control gate layer exposed from the position of the second window, as well as the upper surface of the polysilicon inter-dielectric layer.
6. The process for manufacturing a Nord flash memory device according to claim 1, wherein: The sixth step: in the step of etching the oxide layer, the oxide layer on the side wall of the second window is retained.
7. The process for manufacturing a Nord flash memory device according to claim 1, wherein: The seventh step of removing the inter-polysilicon dielectric layer at the first window position and the oxide and silicon nitride at the sidewall position of the first window by an acid wash solution, so that the side surface of the polysilicon control gate layer and the upper surface of the polysilicon floating gate layer at the first window position are exposed, includes: The inter-polysilicon dielectric layer at the first window position and the oxide and silicon nitride at the side wall position of the first window are removed by hydrofluoric acid and phosphoric acid, so that the side surface of the polysilicon control gate layer and the upper surface of the polysilicon floating gate layer at the first window position are exposed.
8. The process for manufacturing a Nord flash memory device according to claim 1, wherein: After the seventh step of removing the inter-polysilicon dielectric layer at the first window position and the oxide and silicon nitride at the sidewall position of the first window by an acid wash solution, so that the side surface of the polysilicon control gate layer and the upper surface of the polysilicon floating gate layer at the first window position are exposed, The second window with the first spacer structure formed on its sidewall and the first window with the intercrystalline silicon dielectric layer removed together form a third window.
9. The process for manufacturing a Nord flash memory device according to claim 8, wherein: The eighth step: manufacturing the word line structure of the Nord flash memory device, including the following steps: forming a second sidewall structure on the sidewall of the third window; Etching and removing the polysilicon floating gate layer located at the position of the third window and not covered by the second sidewall structure, so that the third window extends downward to form a fourth window; so that a third sidewall structure is formed on the side surface of the polysilicon floating gate layer exposed from the fourth window; Etching and removing the gate oxide layer located at the position of the fourth window and not covered by the third spacer structure, so that the etch stop layer is located in the gate oxide layer, and the fourth window extends downward to form a word line filling window; The word line filling window is filled with word line polysilicon.
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