Semiconductor device

Abstract

A semiconductor device that reduces the recovery loss of the diode region of an RC-IGBT. The semiconductor device according to the present invention is an RC-IGBT in which an IGBT region (10) and a diode region (20) are disposed adjacent to each other. In the diode region (20), a p-type anode layer (25) is provided, which is disposed on the first main surface side compared with the n- type drift layer (1); a p-type contact layer (24) is provided on the main surface side of the p-type anode layer (25) and on the surface layer on the first main surface side of the semiconductor substrate, and the p-type contact layer (24) is connected to the emitter electrode (6); and an n+ type cathode layer (26) is provided on the surface layer on the second main surface side of the semiconductor substrate. The p-type contact layer (24) contains aluminum as a p-type impurity, and the thickness of the p-type contact layer (24) is smaller than the thickness of the n+ type source layer (13) provided in the IGBT region (10).

Description

Technical Field

[0001] The present invention relates to a semiconductor device. Background Art

[0002] Conventionally, a semiconductor device called RC-IGBT (Reverse Conducting IGBT) in which an insulated gate bipolar transistor (IGBT: Insulated Gate Bipolar Transistor) and a freewheeling diode are formed on a single semiconductor substrate has been proposed. In such a semiconductor device, in order to reduce the contact resistance between the surface electrode and the anode portion in the anode portion of the diode region, a p-type contact layer having a high impurity concentration is provided on the surface layer of the anode portion (for example, see Patent Document 1). + Patent Document 1: Japanese Patent Application Laid-Open No. 2010-192597

[0003]

[0004] However, there is a problem in that when a p-type contact layer is provided in the anode portion of the diode region, the amount of holes injected from the anode portion increases during diode operation, and the recovery loss increases. + Summary of the Invention

[0005] The present invention has been made to solve the above problems, and an object thereof is to obtain a semiconductor device in which the recovery loss in the diode region of an RC-IGBT is reduced.

[0006] The semiconductor device according to the present invention has a semiconductor substrate having an n-type drift layer between a first main surface and a second main surface opposite to the first main surface, an insulated gate bipolar transistor region and a diode region are adjacently provided, and an emitter electrode is provided on the first main surface of the semiconductor substrate. The semiconductor device is characterized in that in the insulated gate bipolar transistor region, a p-type base layer is provided on the first main surface side compared with the drift layer; an n-type source layer is selectively provided on the first main surface side of the base layer and selectively provided on the surface layer on the first main surface side of the semiconductor substrate; a p-type first contact layer is provided on the first main surface side of the base layer and in the region of the surface layer on the first main surface side of the semiconductor substrate where the source layer is not provided, and the p-type first contact layer is connected to the emitter electrode; a gate trench insulating film is provided on the inner surface of a trench that penetrates the base layer and reaches the drift layer; a gate trench electrode is provided in the trench via the gate trench insulating film; and a p-type collector layer is provided on the surface layer on the second main surface side of the semiconductor substrate. In the diode region, a p-type anode layer is provided on the first main surface side compared with the drift layer; a p-type second contact layer is provided on the first main surface side of the anode layer and on the surface layer on the first main surface side of the semiconductor substrate, and the p-type second contact layer is connected to the emitter electrode; and an n-type cathode layer is provided on the surface layer on the second main surface side of the semiconductor substrate, and the second contact layer contains aluminum as a p-type impurity.

[0007] Effects of the Invention

[0008] The semiconductor device according to the present invention has the effect of obtaining a semiconductor device in which the recovery loss in the diode region is reduced because the second contact layer provided in the diode region of the RC-IGBT contains aluminum as a p-type impurity. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 It is a top view showing the semiconductor device of Embodiment 1.

[0010] Figure 2 It is a top view showing another structure of the semiconductor device of Embodiment 1.

[0011] Figure 3 It is a partially enlarged top view showing the structure of the IGBT region of the semiconductor device of Embodiment 1.

[0012] Figure 4 It is a cross-sectional view taken along line A-A showing the structure of the IGBT region of the semiconductor device of Embodiment 1.

[0013] Figure 5 It is a cross-sectional view taken along line B-B showing the structure of the IGBT region of the semiconductor device of Embodiment 1.

[0014] Figure 6 It is a partial enlarged top view showing the structure of the diode region of the semiconductor device of Embodiment 1.

[0015] Figure 7 It is a C-C cross-sectional view showing the structure of the diode region of the semiconductor device of Embodiment 1.

[0016] Figure 8 It is a D-D cross-sectional view showing the structure of the diode region of the semiconductor device of Embodiment 1.

[0017] Figure 9 It is a G-G cross-sectional view showing the structure of the boundary between the IGBT region and the diode region of the semiconductor device of Embodiment 1.

[0018] Figure 10 It is a cross-sectional view showing the structure of the end region of the semiconductor device of Embodiment 1.

[0019] Figure 11 It is the first diagram showing the manufacturing method of the semiconductor device of Embodiment 1.

[0020] Figure 12 It is the second diagram showing the manufacturing method of the semiconductor device of Embodiment 1.

[0021] Figure 13 It is the third diagram showing the manufacturing method of the semiconductor device of Embodiment 1.

[0022] Figure 14 It is the fourth diagram showing the manufacturing method of the semiconductor device of Embodiment 1.

[0023] Figure 15 It is the fifth diagram showing the manufacturing method of the semiconductor device of Embodiment 1.

[0024] Figure 16 It is the sixth diagram showing the manufacturing method of the semiconductor device of Embodiment 1.

[0025] Figure 17 It is a G-G cross-sectional view showing the structure of the boundary between the IGBT region and the diode region of the semiconductor device of Embodiment 2.

[0026] Figure 18 It is a G-G cross-sectional view showing the structure of the boundary between the IGBT region and the diode region of the modified example of the semiconductor device of Embodiment 2.

[0027] Figure 19 It is a G-G cross-sectional view showing the structure of the boundary between the IGBT region and the diode region of the semiconductor device of Embodiment 3.

[0028] Figure 20 It is a G-G cross-sectional view showing the structure of the boundary between the IGBT region and the diode region of the semiconductor device according to Embodiment 4.

[0029] Figure 21 It is a G-G cross-sectional view showing the structure of the boundary between the IGBT region and the diode region of the semiconductor device according to Embodiment 5.

[0030] Figure 22 It is a G-G cross-sectional view showing the structure of the boundary between the IGBT region and the diode region of the semiconductor device according to Embodiment 6. Detailed Embodiments

[0031] Hereinafter, the embodiments will be described based on the drawings. In addition, in the following drawings, the same or corresponding parts are denoted by the same reference numerals, and their descriptions are not repeated. Also, in the following description, terms indicating specific directions such as "upper" or "lower" are used for convenience only and have nothing to do with the actual implementation direction.

[0032] In the following description, n and p represent the conductivity types of semiconductors. In addition, n - represents a concentration lower than that of n, and n + represents a concentration higher than that of n. Similarly, p - represents a concentration lower than that of p, and p + represents a concentration higher than that of p.

[0033] Embodiment 1.

[0034] Using Figures 1 to 16 , the semiconductor device according to Embodiment 1 and the manufacturing method of the semiconductor device will be described.

[0035] First, using Figure 1 and Figure 2 , the overall structure of the semiconductor device according to Embodiment 1 will be described. Figure 1 It is a top view showing the semiconductor device 100 as an RC-IGBT. In addition, Figure 2 is a top view showing the semiconductor device 101 as an RC-IGBT with another structure.

[0036] Figure 1 The semiconductor device 100 shown is a semiconductor device in which the IGBT region 10 and the diode region 20 are arranged in a strip shape, and can be simply referred to as "strip type". Regarding Figure 2 the semiconductor device 101 shown, a plurality of diode regions 20 are provided in the longitudinal and lateral directions, and the IGBT region 10 is provided around the diode region 20, and can be simply referred to as "island type".

[0037] In Figure 1 , the semiconductor device 100 has an IGBT region 10 and a diode region 20 within one semiconductor device. The IGBT region 10 and the diode region 20 extend from one end side to the other end side of the semiconductor device 100, and are alternately arranged in stripes in a direction orthogonal to the extending direction of the IGBT region 10 and the diode region 20. In Figure 1 , a structure is shown in which there are 3 IGBT regions and 2 diode regions, and all the diode regions 20 are sandwiched by the IGBT regions 10. However, the numbers of the IGBT region 10 and the diode region 20 are not limited to this. The number of the IGBT region 10 can be greater than or equal to 3, or can be less than or equal to 3. The number of the diode region 20 can also be greater than or equal to 2, or can be less than or equal to 2. In addition, it can also be a structure in which the positions of the IGBT region 10 and the diode region 20 in Figure 1 are exchanged, or a structure in which all the IGBT regions 10 are sandwiched by the diode regions 20. In addition, the IGBT region 10 and the diode region 20 can also be arranged such that they are adjacent to each other one by one respectively.

[0038] As Figure 1 shown, a pad region 40 is arranged adjacent to the IGBT region 10 on the lower side of the paper surface. The pad region 40 is a region where a control pad 41 for controlling the semiconductor device 100 is arranged. The IGBT region 10 and the diode region 20 are collectively referred to as a cell region. In order to maintain the breakdown voltage of the semiconductor device 100, an end region 30 is arranged around the region after combining the cell region and the pad region 40. A known breakdown voltage maintaining structure can be appropriately selectively arranged in the end region 30. The breakdown voltage maintaining structure can be constituted, for example, by arranging an FLR (Field Limiting Ring) that surrounds the cell region by a p-type end well layer of a p-type semiconductor and a VLD (Variation of Lateral Doping) that surrounds the cell region by a p-type well layer having a concentration gradient on the surface side, i.e., the first main surface side, of the semiconductor device 100. The number of the annular p-type end well layers used for the FLR and the concentration distribution used for the VLD can be appropriately selected according to the breakdown voltage design of the semiconductor device 100. In addition, a p-type end well layer can be arranged over substantially the entire region of the pad region 40, or IGBT cells and diode cells can be arranged in the pad region 40.

[0039] The control pad 41 can be, for example, a current sensing pad 41a, a Kelvin emitter pad 41b, a gate pad 41c, a temperature sensing diode pad 41d, 41e. The current sensing pad 41a is a control pad for detecting the current flowing in the cell region of the semiconductor device 100, and is a control pad electrically connected to a part of the IGBT cell or diode cell in the cell region. When current flows in the cell region of the semiconductor device 100, a current of one fraction to one ten-thousandth of the current flowing through the entire cell region flows through this control pad.

[0040] The Kelvin emitter pad 41b and the gate pad 41c are control pads for applying a gate drive voltage for on / off control of the semiconductor device 100. The Kelvin emitter pad 41b is electrically connected to the p-type base layer of the IGBT cell, and the gate pad 41c is electrically connected to the gate trench electrode of the IGBT cell. The Kelvin emitter pad 41b and the p-type base layer can also be electrically connected via a p-type contact layer. The temperature sensing diode pads 41d, 41e are control pads electrically connected to the anode and cathode of the temperature sensing diode provided in the semiconductor device 100. The voltage between the anode and cathode of the temperature sensing diode (not shown) provided in the cell region is measured to measure the temperature of the semiconductor device 100.

[0041] In Figure 2 the semiconductor device 101 has an IGBT region 10 and a diode region 20 in one semiconductor device. A plurality of diode regions 20 are arranged side by side in the longitudinal and lateral directions within the semiconductor device, and the periphery of the diode region 20 is surrounded by the IGBT region 10. That is, a plurality of diode regions 20 are provided in an island shape within the IGBT region 10. In Figure 2 a structure is shown in which the diode regions 20 are arranged in a matrix having 4 columns in the left-right direction of the paper surface and 2 rows in the upper limit direction of the paper surface, but the number and arrangement of the diode regions 20 are not limited to this, as long as one or more diode regions 20 are scattered within the IGBT region 10 and the periphery of each diode region 20 is surrounded by the IGBT region 10.

[0042] As Figure 2 shown, a pad region 40 is provided adjacent to the lower side of the paper surface of the IGBT region 10, and an end region 30 is provided around the region after combining the pad region 40 and the cell region including the IGBT region 10 and the diode region 20 for maintaining the breakdown voltage of the semiconductor device 101. The structures of the pad region 40 and the end region 30 can also be the same as those of the semiconductor device 100 shown in Figure 1 shown.

[0043] Next, use Figures 3 to 5, details of the structure of the IGBT region of the semiconductor device according to the first embodiment are described. Figure 3 This is a partially enlarged top view showing the structure of the RC-IGBT, i.e., the IGBT region of the semiconductor device. Figure 4 and Figure 5 It is a cross-sectional view showing the structure of an IGBT region of a semiconductor device which is an RC-IGBT. Figure 3 Enlarge Figure 1 The semiconductor device 100 or Figure 2 The semiconductor device 101 is shown with a region surrounded by a dotted line 82 . Figure 4 yes Figure 3 A cross-sectional view of the semiconductor device 100 or the semiconductor device 101 taken along the dashed line AA is shown. Figure 5 yes Figure 3 The semiconductor device 100 or the semiconductor device 101 is shown in a cross-sectional view taken along the dashed line BB.

[0044] like Figure 3 As shown, in the IGBT region 10, the active trench gate 11 and the dummy trench gate 12 are arranged in a strip shape. In the semiconductor device 100, the active trench gate 11 and the dummy trench gate 12 extend in the length direction of the IGBT region 10, and the length direction of the IGBT region 10 becomes the length direction of the active trench gate 11 and the dummy trench gate 12. On the other hand, in the semiconductor device 101, the difference between the length direction and the width direction at the IGBT region 10 is not particularly limited, and the left-right direction of the paper can be set as the length direction of the active trench gate 11 and the dummy trench gate 12, and the up-down direction of the paper can also be set as the length direction of the active trench gate 11 and the dummy trench gate 12.

[0045] The active trench gate 11 is formed by providing a gate trench electrode 11a in a trench formed in a semiconductor substrate via a gate trench insulating film 11b. The dummy trench gate 12 is formed by providing a dummy trench electrode 12a in a trench formed in a semiconductor substrate via a dummy trench electrode 12b. The gate trench electrode 11a of the active trench gate 11 is electrically connected to the gate pad 41c. The dummy trench electrode 12a of the dummy trench gate 12 is electrically connected to an emitter electrode provided on the first main surface of the semiconductor device 100 or the semiconductor device 101.

[0046] n + The type source layer 13 is provided so as to be in contact with the gate trench insulating film 11b on both sides in the width direction of the active trench gate 11. + The source layer 13 is a semiconductor layer containing, for example, arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is 1.0E+17 / cm 3 ~1.0E+ 20 / cm 3 .n+ The p-type source layer 13 is alternately provided with the p-type contact layer 14 along the extension direction of the active trench gate 11. The p-type contact layer 14 is also provided between two adjacent dummy trench gates 12. The p-type contact layer 14 is a semiconductor layer having aluminum as a p-type impurity, and the concentration of aluminum as a p-type impurity is preferably 1.0E+12 / cm 3 ~1.0E+18 / cm 3 .

[0047] like Figure 3 As shown, in the IGBT region 10 of the semiconductor device 100 or the semiconductor device 101, three dummy trench gates 12 are arranged next to three parallel active trench gates 11, and three active trench gates 11 are arranged next to three parallel dummy trench gates 12. The IGBT region 10 is configured such that the groups of active trench gates 11 and the groups of dummy trench gates 12 are alternately arranged as described above. Figure 3 In the figure, the number of active trench gates 11 included in one group of active trench gates 11 is 3, but it only needs to be greater than or equal to 1. In addition, the number of dummy trench gates 12 included in one group of dummy trench gates 12 may be greater than or equal to 1, and the number of dummy trench gates 12 may also be 0. That is, all trenches provided in the IGBT region 10 may also be set as active trench gates 11.

[0048] Figure 4 is the semiconductor device 100 or the semiconductor device 101 Figure 3 The cross-sectional view taken along the dotted line AA in FIG. 1 is a cross-sectional view of the IGBT region 10. The semiconductor device 100 or the semiconductor device 101 has an IGBT region 10 formed of a semiconductor substrate. - Type drift layer 1. n - The drift layer 1 is a semiconductor layer containing, for example, arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is 1.0E +12 / cm 3 ~1.0E+15 / cm 3 , n - The concentration of n-type impurities in the p-type drift layer 1 is lower than the concentration of p-type impurities in the p-type contact layer 14. Figure 4 In the + The range from the p-type source layer 13 and the p-type contact layer 14 to the p-type collector layer 16. Figure 4 Medium +The upper end of the paper surface of the p-type source layer 13 and the p-type contact layer 14 is referred to as the first main surface of the semiconductor substrate, and the lower end of the paper surface of the p-type collector layer 16 is referred to as the second main surface of the semiconductor substrate. The first main surface of the semiconductor substrate is the main surface on the surface side of the semiconductor device 100, and the second main surface of the semiconductor substrate is the main surface on the back side of the semiconductor device 100. In the unit region, that is, the IGBT region 10 of the semiconductor device 100, an n - -type drift layer 1 is provided between the first main surface and the second main surface opposite to the first main surface.

[0049] As Figure 4 shown, in the IGBT region 10, an n-type carrier accumulation layer 2 with a higher concentration of n-type impurities than that of the n - -type drift layer 1 is provided on the first main surface side of the n-type drift layer 1. The n-type carrier accumulation layer 2 is a semiconductor layer having, for example, arsenic or phosphorus as the n-type impurity, and the concentration of the n-type impurity is 1.0E+13 / cm - ~1.0E+17 / cm 3 . In addition, the semiconductor device 100 or the semiconductor device 101 may also be a structure in which the n-type carrier accumulation layer 2 is not provided, and the n-type drift layer 1 is also provided in the region of the n-type carrier accumulation layer 2 as 3 shown. By providing the n-type carrier accumulation layer 2, the conduction loss when current flows in the IGBT region 10 can be reduced. The n-type carrier accumulation layer 2 and the n Figure 4 -type drift layer 1 may also be combined and referred to as the drift layer. - The n-type carrier accumulation layer 2 is formed by implanting n-type impurity ions into the semiconductor substrate constituting the n - -type drift layer 1, and then diffusing the implanted n-type impurities into the n

[0050] -type drift layer 1, that is, the semiconductor substrate, by annealing. - On the first main surface side of the n-type carrier accumulation layer 2, a p-type base layer 15 is provided. The p-type base layer 15 is a semiconductor layer having, for example, boron or aluminum as the p-type impurity, and the concentration of the p-type impurity is 1.0E+12 / cm - ~1.0E+18 / cm

[0051] . The p-type base layer 15 is in contact with the gate trench insulating film 11b of the active trench gate 11. An n 3 -type source layer 13 is provided in contact with the gate trench insulating film 11b of the active trench gate 11 on the first main surface side of the p-type base layer 15, and a p-type contact layer 14 is provided in the remaining region. n 3 -type source layer 13, in the remaining region, a p-type contact layer 14 is provided. n + -type source layer 13, in the remaining region, a p-type contact layer 14 is provided. n +The p-type source layer 13 and the p-type contact layer 14 constitute the first main surface of the semiconductor substrate. In addition, the p-type contact layer 14 is a region where the concentration of p-type impurities is higher than that of the p-type base layer 15. When it is necessary to distinguish between the p-type contact layer 14 and the p-type base layer 15, they can be called separately, or the p-type contact layer 14 and the p-type base layer 15 can be collectively referred to as the p-type base layer.

[0052] As Figure 3 and Figure 4 shown, the p-type contact layer 14 is formed on the surface layer between the trenches and is a semiconductor layer containing aluminum as p-type impurities. By containing aluminum as p-type impurities in the p-type contact layer 14, the thickness can be formed smaller than that of the n- + type source layer 13, and preferably has a thickness less than or equal to 1 / 2 of the thickness of the n- + type source layer 13. In addition, the impurity concentration of aluminum in the p-type contact layer 14 is preferably 1.0E+12 / cm 3 ~1.0E+18 / cm 3 . As a method of doping aluminum, aluminum ions can be implanted from the first main surface side, or an electrolytic solution containing aluminum can also be used. In addition, it is sufficient that the p-type contact layer 14 is formed on at least a part of the surface layer between the trenches.

[0053] In addition, in the semiconductor device 100 or the semiconductor device 101, an n-type buffer layer 3 with a higher concentration of n-type impurities than that of the n- - type drift layer 1 is provided on the second main surface side of the n-type drift layer 1. The n-type buffer layer 3 is provided to suppress the breakdown of the depletion layer extending to the second main surface side from the p-type base layer 15 when the semiconductor device 100 is in an off state. The n-type buffer layer 3 can be formed by implanting phosphorus (P) or protons (H - + ) for example, or can be formed by implanting both phosphorus (P) and protons (H + ). The concentration of n-type impurities in the n-type buffer layer 3 is 1.0E+12 / cm 3 ~1.0E+18 / cm 3 .

[0054] In addition, the semiconductor device 100 or the semiconductor device 101 may not be provided with the n-type buffer layer 3, and an n- Figure 4 type drift layer 1 is also provided in the region of the n-type buffer layer 3 as shown. In addition, the n-type buffer layer 3 and the n- - type drift layer 1 can also be collectively referred to as the drift layer. - type drift layer 1 can also be collectively referred to as the drift layer.

[0055] The semiconductor device 100 or the semiconductor device 101 is provided with a p-type collector layer 16 on the second main surface side of the n-type buffer layer 3. That is, on the n- - ​A p-type collector layer 16 is provided between the drift layer 1 and the second main surface. The p-type collector layer 16 is a semiconductor layer containing, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is 1.0E+16 / cm 3 ~1.0E+20 / cm 3 The p-type collector layer 16 constitutes the second main surface of the semiconductor substrate. The p-type collector layer 16 is provided not only in the IGBT region 10 but also in the terminal region 30, and the portion of the p-type collector layer 16 provided in the terminal region 30 constitutes a p-type terminal collector layer 16a. In addition, the p-type collector layer 16 may be provided so that a portion thereof extends from the IGBT region 10 to the diode region 20.

[0056] like Figure 4 As shown, in the semiconductor device 100 or the semiconductor device 101, a first main surface of the semiconductor substrate is formed through the p-type base layer 15 to reach the n-type base layer 15. - The active trench gate 11 is formed by providing a gate trench electrode 11a in the trench via a gate trench insulating film 11b. The gate trench electrode 11a is connected to the n-type drift layer 1 via the gate trench insulating film 11b. - The dummy trench electrode 12a is disposed in the trench via the dummy trench insulating film 12b, thereby forming the dummy trench gate 12. The dummy trench electrode 12a is disposed via the dummy trench insulating film 12b and the n type drift layer 1. - The gate trench insulating film 11b of the active trench gate 11 is opposite to the p-type base layer 15 and the n-type base layer 16. + The active trench gate 11 is in contact with the p-type source layer 13. When a gate driving voltage is applied to the gate trench electrode 11a, a channel is formed in the p-type base layer 15 in contact with the gate trench insulating film 11b of the active trench gate 11.

[0057] like Figure 4 As shown in FIG. 1 , an interlayer insulating film 4 is provided on the gate trench electrode 11a of the active trench gate 11. A barrier metal 5 is formed on the region of the first main surface of the semiconductor substrate where the interlayer insulating film 4 is not provided and on the interlayer insulating film 4. The barrier metal 5 is preferably formed of titanium (Ti) or a titanium alloy, and may be, for example, a conductor containing titanium, such as titanium nitride, or TiSi obtained by alloying titanium and silicon (Si). Figure 4 As shown, the barrier metal 5 and n + The p-type source layer 13, the p-type contact layer 14 and the dummy trench electrode 12a make ohmic contact with the n-type source layer 13, the p-type contact layer 14 and the dummy trench electrode 12a. + The p-type source layer 13, the p-type contact layer 14 and the dummy trench electrode 12a are electrically connected.

[0058] An emitter electrode 6 is provided on the barrier metal 5. The emitter electrode 6 can be formed of, for example, an aluminum alloy such as an aluminum-silicon alloy (Al-Si alloy), or can also be an electrode composed of a multi-layer metal film in which a coating film is formed by electroless plating or electroplating on an electrode formed of an aluminum alloy. The coating film formed by electroless plating or electroplating can be, for example, a nickel (Ni) coating film, or can also be a copper (Cu) coating film. By forming the emitter electrode 6 with copper or a copper alloy having high mechanical strength such as a copper coating film, the effect of improving the power cycle tolerance is achieved. In addition, the emitter electrode 6 can also have a gold (Au) coating film on the nickel coating film or on the copper coating film.

[0059] In addition, in a case where there is a minute region such as between adjacent interlayer insulating films 4, that is, a region where good embedding by the emitter electrode 6 cannot be performed, tungsten having better embedding properties than the emitter electrode 6 can be disposed in the minute region, and the emitter electrode 6 can be provided on the tungsten. In addition, it is also possible to provide the barrier metal 5 only on an n-type semiconductor layer such as the n-type source layer 13. The barrier metal 5 and the emitter electrode 6 can be collectively referred to as the emitter electrode. In addition, + a diagram showing that the interlayer insulating film 4 is not provided on the dummy trench electrode 12a of the dummy trench gate 12 is shown in Figure 4 , but the interlayer insulating film 4 can also be formed on the dummy trench electrode 12a of the dummy trench gate 12. In a case where the interlayer insulating film 4 is formed on the dummy trench electrode 12a of the dummy trench gate 12, the emitter electrode 6 and the dummy trench electrode 12a can be electrically connected in other cross-sections.

[0060] In addition, in the semiconductor device of the present embodiment, the structure having the barrier metal 5 is described, but the barrier metal 5 can also be not provided, and the emitter electrode 6 can be provided on the n + type source layer 13, the p-type contact layer 14, and the dummy trench electrode 12a. Since the energy barrier height of titanium constituting the barrier metal with respect to p-type silicon is high, in the past, by setting the impurity concentration of the p-type contact layer high, an ohmic contact between the barrier metal and p-type silicon, that is, the p-type contact layer, could be achieved. On the other hand, the barrier height of aluminum constituting the emitter electrode with respect to p-type silicon is lower than that of titanium, and an ohmic contact between the emitter electrode and p-type silicon, that is, the p-type contact layer, can be achieved even when the p-type impurity concentration is low.

[0061] A collector electrode 7 is provided on the second main surface side of the p-type collector layer 16. The collector electrode 7 can also be formed of an aluminum alloy, an aluminum alloy and a coating film, in the same manner as the emitter electrode 6. In addition, the collector electrode 7 can also have a structure different from that of the emitter electrode 6. The collector electrode 7 makes an ohmic contact with the p-type collector layer 16 and is electrically connected to the p-type collector layer 16.

[0062] Figure 5 of the semiconductor device 100 or the semiconductor device 101Figure 3 The cross-sectional view at the dotted line BB in FIG. 1 is a cross-sectional view of the IGBT region 10. Figure 4 The cross-sectional view at the dashed line AA shown is different in the following aspects, namely, Figure 5 In the cross section at the dotted line BB of FIG. 1 , no n-type transistor provided on the first main surface side of the semiconductor substrate and in contact with the active trench gate 11 is observed. + Type source layer 13. That is, Figure 3 As shown, n + The p-type source layer 13 is selectively provided on the first main surface side of the p-type base layer. The p-type base layer referred to here means a p-type base layer in which the p-type base layer 15 and the p-type contact layer 14 are collectively referred to.

[0063] Next, use Figures 6 to 8 , details of the structure of the diode region of the semiconductor device of embodiment 1 are described. Figure 6 This is a partially enlarged top view showing the structure of the diode region of the RC-IGBT, i.e., the semiconductor device. Figure 7 and Figure 8 It is a cross-sectional view showing the structure of a diode region of a semiconductor device, which is an RC-IGBT. Figure 6 Enlarge Figure 1 The semiconductor device 100 or the semiconductor device 101 is shown as a region surrounded by a dotted line 83 . Figure 7 yes Figure 6 The semiconductor device 100 is shown in cross-sectional view along the dashed line CC. Figure 8 yes Figure 6 FIG. 1 is a cross-sectional view of the semiconductor device 100 taken along a dashed line DD.

[0064] The diode trench gate 21 extends from one end side of the unit region, i.e., the diode region 20, to the other end side opposite thereto along the first main surface of the semiconductor device 100 or the semiconductor device 101. The diode trench gate 21 is formed by providing a diode trench electrode 21a in a trench formed in the semiconductor substrate of the diode region 20 via a diode trench insulating film 21b. The diode trench electrode 21a is connected to the n-type diode through the diode trench insulating film 21b. - The p-type drift layer 1 is opposite. A p-type contact layer 24 and a p-type anode layer 25 are provided between two adjacent diode trench gates 21. The p-type contact layer 24 is a semiconductor layer having aluminum as a p-type impurity. The concentration of aluminum as a p-type impurity is preferably 1.0E+12 / cm 3 ~1.0E+18 / cm 3 The p-type anode layer 25 is a semiconductor layer containing, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is 1.0E+12 / cm 3 ~1.0E+18 / cm3 . The p-type contact layer 24 and the p-type anode layer 25 are alternately arranged in the longitudinal direction of the diode trench gate 21.

[0065] Figure 7 It is a cross-sectional view taken along the dashed line C-C in Figure 6 the semiconductor device 100 or the semiconductor device 101, and it is a cross-sectional view of the diode region 20. The semiconductor device 100 or the semiconductor device 101 also has an n- - type drift layer 1 formed of a semiconductor substrate in the diode region 20 in the same manner as the IGBT region 10. The n- - type drift layer 1 in the diode region 20 and the n- - type drift layer 1 in the IGBT region 10 are continuously formed as one body and are formed by the same semiconductor substrate. In Figure 7 the semiconductor substrate ranges from the p-type contact layer 24 to the n- + type cathode layer 26. The upper end of the p-type contact layer 24 on the paper surface in Figure 7 is referred to as the first main surface of the semiconductor substrate, and the lower end of the n- + type cathode layer 26 on the paper surface is referred to as the second main surface of the semiconductor substrate. The first main surface of the diode region 20 and the first main surface of the IGBT region 10 are the same surface, and the second main surface of the diode region 20 and the second main surface of the IGBT region 10 are the same surface.

[0066] As Figure 7 shown, in the diode region 20, in the same manner as the IGBT region 10, an n- - type carrier accumulation layer 2 is provided on the first main surface side of the n-type drift layer 1, and an n- - type buffer layer 3 is provided on the second main surface side of the n-type drift layer 1. The n-type carrier accumulation layer 2 and the n-type buffer layer 3 provided in the diode region 20 have the same structure as the n-type carrier accumulation layer 2 and the n-type buffer layer 3 provided in the IGBT region 10. In addition, it is not necessary to provide an n-type carrier accumulation layer 2 in the IGBT region 10 and the diode region 20. When an n-type carrier accumulation layer 2 is provided in the IGBT region 10, it can also be configured not to provide an n-type carrier accumulation layer 2 in the diode region 20. Additionally, in the same manner as the IGBT region 10, the n- - type drift layer 1, the n-type carrier accumulation layer 2, and the n-type buffer layer 3 can be collectively referred to as the drift layer.

[0067] A p-type anode layer 25 is provided on the first main surface side of the n-type carrier accumulation layer 2. The p-type anode layer 25 is provided on the n- -Between the p-type drift layer 1 and the first main surface. The concentration of the p-type impurity in the p-type anode layer 25 can also be set to the same concentration as that of the p-type base layer 15 in the IGBT region 10, and the p-type anode layer 25 and the p-type base layer 15 are formed simultaneously. Additionally, it can also be configured such that the concentration of the p-type impurity in the p-type anode layer 25 is set lower than the concentration of the p-type impurity in the p-type base layer 15 in the IGBT region 10, so as to reduce the amount of holes injected into the diode region 20 during diode operation. By reducing the amount of holes injected during diode operation, the recovery loss during diode operation can be reduced.

[0068] A p-type contact layer 24 is provided on the first main surface side of the p-type anode layer 25. The concentration of aluminum as the p-type impurity in the p-type contact layer 24 can be set to the same concentration as that of aluminum as the p-type impurity in the p-type contact layer 14 in the IGBT region 10, or can be set to a different concentration. The p-type contact layer 24 constitutes the first main surface of the semiconductor substrate. In addition, the p-type contact layer 24 is a region where the concentration of the p-type impurity is higher than that of the p-type anode layer 25. In the case where it is necessary to distinguish between the p-type contact layer 24 and the p-type anode layer 25, they can be individually named, or the p-type contact layer 24 and the p-type anode layer 25 can be collectively referred to as the p-type anode layer.

[0069] In the diode region 20, an n + -type cathode layer 26 is provided on the second main surface side of the n-type buffer layer 3. n + -type cathode layer 26 is provided between the n - -type drift layer 1 and the second main surface. The n + -type cathode layer 26 is a semiconductor layer having, for example, arsenic or phosphorus as the n-type impurity, and the concentration of the n-type impurity is 1.0E+16 / cm 3 ~1.0E+21 / cm 3 . As Figure 2 shown, the n + -type cathode layer 26 is provided in a part or all of the diode region 20. The n + -type cathode layer 26 constitutes the second main surface of the semiconductor substrate. In addition, although not shown, p-type impurities can also be selectively injected into the region where the n + -type cathode layer 26 is formed as described above, and a part of the region where the n + -type cathode layer 26 is formed is used as a p-type semiconductor to provide a p-type cathode layer.

[0070] As Figure 7 shown, in the diode region 20 of the semiconductor device 100 or the semiconductor device 101, a through hole is formed that penetrates the p-type anode layer 25 from the first main surface of the semiconductor substrate to reach the n -The diode trench gate 21 is formed by providing a diode trench electrode 21a in the trench of the diode region 20 via a diode trench insulating film 21b. The diode trench electrode 21a is connected to the n-type drift layer 1 via the diode trench insulating film 21b. - type drift layer 1 is relative.

[0071] like Figure 7 As shown, a barrier metal 5 is provided on the diode trench electrode 21a and the p-type contact layer 24. The barrier metal 5 makes ohmic contact with the diode trench electrode 21a and the p-type contact layer 24, and is electrically connected to the diode trench electrode 21a and the p-type contact layer 24. The barrier metal 5 may have the same structure as the barrier metal 5 of the IGBT region 10. An emitter electrode 6 is provided on the barrier metal 5. The emitter electrode 6 provided in the diode region 20 is formed continuously with the emitter electrode 6 provided in the IGBT region 10. In addition, as in the case of the IGBT region 10, the barrier metal 5 may not be provided, so that the diode trench electrode 21a and the p-type contact layer 24 make ohmic contact with the emitter electrode 6. In addition, Figure 7 2 shows a diagram in which the interlayer insulating film 4 is not provided on the diode trench electrode 21a of the diode trench gate 21, but the interlayer insulating film 4 may be formed on the diode trench electrode 21a of the diode trench gate 21. When the interlayer insulating film 4 is formed on the diode trench electrode 21a of the diode trench gate 21, the emitter electrode 6 and the diode trench electrode 21a may be electrically connected in other cross sections.

[0072] In n + The collector electrode 7 is provided on the second main surface side of the n-type cathode layer 26. Similar to the emitter electrode 6, the collector electrode 7 of the diode region 20 is formed continuously with the collector electrode 7 provided in the IGBT region 10. + The cathode layer 26 makes ohmic contact with the n + The cathode layer 26 is electrically connected to the cathode layer.

[0073] Figure 8 is the semiconductor device 100 or the semiconductor device 101 Figure 6 The cross-sectional view at the dotted line DD in FIG. 1 is a cross-sectional view of the diode region 20. Figure 7 The cross-sectional view at the dotted line CC shown is different in that no p-type contact layer 24 is provided between the p-type anode layer 25 and the barrier metal 5, and the p-type anode layer 25 constitutes the first main surface of the semiconductor substrate. Figure 7 The p-type contact layer 24 shown is selectively provided on the first main surface side of the p-type anode layer 25 .

[0074] Here, use Figure 9The boundary region between the IGBT region and the diode region of the semiconductor device of Embodiment 1 will be described. Figure 9 It is a cross-sectional view showing the structure of the boundary between the IGBT region and the diode region of an RC-IGBT, i.e., a semiconductor device. Figure 9 It is Figure 1 A cross-sectional view taken along the dashed line G-G in the semiconductor device 100 or the semiconductor device 101 shown. Additionally, Figure 9 It is as Figure 3 shown by the dashed line A-A, and is a cross-sectional view at a location having an n + -type source layer 13 in this cross-section.

[0075] As Figure 9 shown, a p-type collector layer 16 provided on the second main surface side of the IGBT region 10 is set to extend a distance U1 from the boundary between the IGBT region 10 and the diode region 20 toward the diode region 20 side. In this way, by setting the p-type collector layer 16 to extend into the diode region 20, the distance between the n + -type cathode layer 26 of the diode region 20 and the active trench gate 11 can be made large. Even when a gate drive voltage is applied to the gate trench electrode 11a during the operation of the freewheeling diode, it is possible to suppress the current from flowing from the channel formed adjacent to the active trench gate 11 in the IGBT region 10 to the n + -type cathode layer 26. The distance U1 can be, for example, 100 μm. In addition, depending on the use of the RC-IGBT, i.e., the semiconductor device 100 or the semiconductor device 101, the distance U1 can also be zero or a distance smaller than 100 μm.

[0076] Additionally, as Figure 9 shown, a p-type contact layer 24 is formed on the surface layer between the trenches and is a semiconductor layer containing aluminum as a p-type impurity. By containing aluminum as a p-type impurity in the p-type contact layer 24, the thickness can be formed smaller than that of the n + -type source layer 13 and preferably has a thickness of 1 / 2 of the thickness of the n + -type source layer 13. As a method of doping aluminum, aluminum ions can be implanted from the first main surface side, or an electrolytic solution containing aluminum can also be used. In addition, it is sufficient that the p-type contact layer 24 is formed on at least a part of the surface layer between the trenches.

[0077] Additionally, the structure of the end region of the semiconductor device of Embodiment 1 will be described using Figure 10 the following. Figure 10 It is a cross-sectional view showing the structure of the end region of an RC-IGBT, i.e., a semiconductor device. Figure 10 (a) It is Figure 1 or Figure 2The cross-sectional view taken along the dashed line E-E is a cross-sectional view from the IGBT region 10 to the end region 30. Additionally, Figure 10 (b) is Figure 1 The cross-sectional view taken along the dashed line F-F is a cross-sectional view from the diode region 20 to the end region 30.

[0078] As Figure 10 (a) and Figure 10 (b) show, the end region 30 of the semiconductor device 100 has an n - -type drift layer 1 between the first main surface and the second main surface of the semiconductor substrate. The first main surface and the second main surface of the end region 30 are the same as the first main surface and the second main surface of the IGBT region 10 and the diode region 20, respectively. Additionally, the n - -type drift layer 1 of the end region 30 has the same structure as the n - -type drift layer 1 of the IGBT region 10 and the diode region 20 and is continuously formed as one body.

[0079] On the first main surface side of the n - -type drift layer 1, that is, between the first main surface of the semiconductor substrate and the n - -type drift layer 1, a p-type end well layer 31 is provided. The p-type end well layer 31 is a semiconductor layer having, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is 1.0E + 14 / cm 3 ~1.0E + 19 / cm 3 . The p-type end well layer 31 is provided to surround the cell region including the IGBT region 10 and the diode region 20. The p-type end well layer 31 is provided in a plurality of rings, and the number of the p-type end well layers 31 provided is appropriately selected according to the breakdown voltage design of the semiconductor device 100 or the semiconductor device 101. Additionally, an n + -type channel cutoff layer 32 is provided on the more peripheral side of the p-type end well layer 31, and the n + -type channel cutoff layer 32 surrounds the p-type end well layer 31.

[0080] A p-type end collector layer 16a is provided between the n - -type drift layer 1 and the second main surface of the semiconductor substrate. The p-type end collector layer 16a is continuously formed as one body with the p-type collector layer 16 provided in the cell region. Therefore, it can also be referred to as the p-type collector layer 16 including the p-type end collector layer 16a. Additionally, in the structure where the diode region 20 is adjacent to the end region 30 as in the semiconductor device 100 shown in Figure 1 , as in Figure 10(b), the p-type end collector layer 16a is arranged such that the end portion on the diode region 20 side extends a distance U2 into the diode region 20. Thus, by arranging the p-type end collector layer 16a to extend into the diode region 20, the distance between the n-type cathode layer 26 and the p-type end well layer 31 in the diode region 20 can be made large, and the p-type end well layer 31 can be prevented from acting as the anode of the diode. The distance U2 can be, for example, 100 μm. + A collector electrode 7 is provided on the second main surface of the semiconductor substrate. The collector electrode 7 is continuously formed integrally from the cell region including the IGBT region 10 and the diode region 20 to the end region 30. On the other hand, an emitter electrode 6 continuous from the cell region and an end electrode 6a separated from the emitter electrode 6 are provided on the first main surface of the semiconductor substrate in the end region 30.

[0081] The emitter electrode 6 and the end electrode 6a are electrically connected via a semi-insulating film 33. The semi-insulating film 33 can be, for example, sinSiN (semi-insulating Silicon Nitride). The end electrode 6a is electrically connected to the p-type end well layer 31 and the n-type channel cutoff layer 32 via contact holes formed in an interlayer insulating film 4 provided on the first main surface of the end region 30. In addition, an end protective film 34 covering the emitter electrode 6, the end electrode 6a, and the semi-insulating film 33 is provided in the end region 30. The end protective film 34 can be formed of, for example, polyimide.

[0082] Then, the manufacturing method of the semiconductor device according to the first embodiment will be described. + FIG. is a diagram showing the manufacturing method of an RC-IGBT, that is, a semiconductor device.

[0083] FIG. is a diagram showing the process of forming the surface side of the semiconductor device 100 or the semiconductor device 101, Figures 11 to 16 and FIG. is a diagram showing the process of forming the back side of the semiconductor device 100 or the semiconductor device 101. Figures 11 to 16 First, as shown in (a), the components for forming the n-type Figures 11 to 14 are prepared. Figure 15 and Figure 16 FIG. is a diagram showing the process of forming the back side of the semiconductor device 100 or the semiconductor device 101.

[0084] First, as Figure 11 (a) shows the preparation of the components for forming the n-type -Semiconductor substrate of the type drift layer 1. For example, a so-called FZ wafer fabricated by the FZ (Floating Zone) method or a so-called MCZ wafer fabricated by the MCZ (Magnetic-fieldapplied CZochralki) method can be used as the semiconductor substrate, and it can be an n-type wafer containing n-type impurities. The concentration of the n-type impurities contained in the semiconductor substrate is appropriately selected according to the breakdown voltage of the fabricated semiconductor device. For example, in a semiconductor device with a breakdown voltage of 1200V, the concentration of the n-type impurities is adjusted so that the relative resistance of the n - type drift layer 1 is about 40 to 120 Ω·cm. As Figure 11 (a) shows, in the process of preparing the semiconductor substrate, the whole of the semiconductor substrate is the n - type drift layer 1, but by injecting p-type or n-type impurity ions from the first main surface side or the second main surface side of such a semiconductor substrate and then diffusing them into the semiconductor substrate through heat treatment or the like, a p-type or n-type semiconductor layer is formed, and the semiconductor device 100 or the semiconductor device 101 is manufactured.

[0085] As Figure 11 (a) shows, the semiconductor substrate constituting the n - type drift layer 1 has regions that become the IGBT region 10 and the diode region 20. In addition, although not shown, there is a region that becomes the terminal region 30 around the regions that become the IGBT region 10 and the diode region 20. Hereinafter, mainly the manufacturing method of the structures of the IGBT region 10 and the diode region 20 of the semiconductor device 100 or the semiconductor device 101 will be described, but the terminal region 30 of the semiconductor device 100 or the semiconductor device 101 can be fabricated by a known manufacturing method. For example, in the case where an FLR having a p-type terminal well layer 51 is formed in the terminal region 30 as a breakdown voltage holding structure, it can be formed by injecting p-type impurity ions before processing the IGBT region 10 and the diode region 20 of the semiconductor device 100 or the semiconductor device 101, or it can be formed by injecting p-type impurity ions simultaneously when injecting p-type impurity ions into the IGBT region 10 or the diode region 20 of the semiconductor device 100.

[0086] Next, as Figure 11As shown in (b), n-type impurities such as phosphorus (P) are injected from the first main surface side of the semiconductor substrate to form an n-type carrier storage layer 2. In addition, p-type impurities such as boron (B) are injected from the first main surface side of the semiconductor substrate to form a p-type base layer 15 and a p-type anode layer 25. The n-type carrier storage layer 2, the p-type base layer 15, and the p-type anode layer 25 are formed by diffusing the impurity ions by heat treatment after impurity ions are injected into the semiconductor substrate. Since the n-type impurities and the p-type impurities are ion-implanted after applying a mask process on the first main surface of the semiconductor substrate, they are selectively formed on the first main surface side of the semiconductor substrate. The n-type carrier storage layer 2, the p-type base layer 15, and the p-type anode layer 25 are formed in the IGBT region 10 and the diode region 20, and are connected to the p-type terminal well layer 51 in the terminal region 30. In addition, mask processing is a process in which a resist is applied to a semiconductor substrate, an opening is formed in a specified area of the resist using photolithography technology, and a mask is formed on the semiconductor substrate in order to perform ion implantation or etching in a specified area of the semiconductor substrate through the opening.

[0087] It is also possible to simultaneously perform ion implantation of p-type impurities to form the p-type base layer 15 and the p-type anode layer 25. In this case, the p-type base layer 15 and the p-type anode layer 25 have the same depth, p-type impurity concentration, and the same structure. Alternatively, it is also possible to perform ion implantation of p-type impurities into the p-type base layer 15 and the p-type anode layer 25 using a mask process, respectively, so that the p-type base layer 15 and the p-type anode layer 25 have different depths and p-type impurity concentrations.

[0088] In addition, the p-type end well layer 51 formed in another cross section may be formed by ion implanting p-type impurities simultaneously with the p-type anode layer 25. In this case, the depth and p-type impurity concentration of the p-type end well layer 51 and the p-type anode layer 25 can be made the same and the structure can be made the same. In addition, the p-type end well layer 51 and the p-type anode layer 25 may be formed by ion implanting p-type impurities simultaneously, and the p-type impurity concentrations of the p-type end well layer 51 and the p-type anode layer 25 may be made different. In this case, the mask of one or both of them may be a grid-shaped mask, and the aperture ratio may be changed. In addition, the p-type impurity ions may be implanted into the p-type end well layer 51 and the p-type anode layer 25 respectively by masking, so that the depth and p-type impurity concentration of the p-type end well layer 51 and the p-type anode layer 25 may be made different. The p-type end well layer 51, the p-type base layer 15, and the p-type anode layer 25 may be formed by ion implanting p-type impurities simultaneously.

[0089] Then, if Figure 12 As shown in FIG. 2( a ), n-type impurities are selectively implanted into the first main surface side of the p-type base layer 15 of the IGBT region 10 by masking to form an n-type base layer. +n-type source layer 13. The implanted n-type impurity may be, for example, arsenic (As) or phosphorus (P). Additionally, through a masking process, p-type impurity, i.e., aluminum, is selectively implanted into the first main surface side of the p-type base layer 15 in the IGBT region to form a p-type contact layer 14. Moreover, through a masking process, p-type impurity, i.e., aluminum, is selectively implanted into the first main surface side of the p-type anode layer 25 in the diode region 20 to form a p-type contact layer 24. At this time, the p-type contact layers 14 and 24 are thinner than the + n-type source layer 13, and are formed, for example, to have a thickness less than or equal to 1 / 2 of the thickness of the + n-type source layer 13. In addition, the p-type contact layer 14 and the p-type contact layer 24 can be formed simultaneously or separately.

[0090] Next, as Figure 12 (b) shows, a trench 8 is formed that penetrates the p-type base layer 15 and the p-type anode layer 25 from the first main surface side of the semiconductor substrate to reach the - n-type drift layer 1. In the IGBT region 10, the + n-type source layer 13 and the p-type contact layer 14 form a part of the sidewall of the trench 8 that penetrates the + n-type source layer 13 and the p-type contact layer 14. After depositing an oxide film such as SiO2 on the semiconductor substrate, an opening is formed in the oxide film at the part where the trench 8 is to be formed through a masking process, and the semiconductor substrate is etched using the oxide film with the opening as a mask to form the trench 8. In Figure 12 (b), the pitch of the trench 8 is formed to be the same in the IGBT region 10 and the diode region 20, but the pitch of the trench 8 can also be made different in the IGBT region 10 and the diode region 20. The pattern of the pitch of the trench 8 in a top view can be appropriately changed using the mask pattern of the masking process.

[0091] Next, as Figure 13 (a) shows, the semiconductor substrate is heated in an oxygen-containing environment to form an oxide film 9 on the inner wall of the trench 8 and the first main surface of the semiconductor substrate. The oxide film 9 formed on the inner wall of the trench 8 in the trench 8 formed in the IGBT region 10 is the gate trench insulating film 11b of the active trench gate 11 and the dummy trench insulating film 12b of the dummy trench gate 12. Additionally, the oxide film 9 formed on the inner wall of the trench 8 in the diode region 20 is the diode trench insulating film 21b. The oxide film 9 formed on the first main surface of the semiconductor substrate is removed through subsequent processes.

[0092] Next, as Figure 13As shown in Fig. (b), polysilicon doped with n-type or p-type impurities is deposited by CVD (chemical vapor deposition) or the like in the groove 8 having the oxide film 9 formed on the inner wall to form the gate trench electrode 11a, the dummy trench electrode 12a, and the diode trench electrode 21a.

[0093] Next, as shown in Figure 14 Fig. (a), after the interlayer insulating film 4 is formed on the gate trench electrode 11a of the active trench gate 11 in the IGBT region 10, the oxide film 9 formed on the first main surface of the semiconductor substrate is removed. The interlayer insulating film 4 can be, for example, SiO2. Then, contact holes are formed in the deposited interlayer insulating film 4 through a mask process. The contact holes are formed above the n + -type source layer 13, above the p-type contact layer 14, above the p-type contact layer 24, above the dummy trench electrode 12a, and above the diode trench electrode 21a.

[0094] Next, as shown in Figure 14 Fig. (b), a barrier metal 5 is formed on the first main surface of the semiconductor substrate and the interlayer insulating film 4, and an emitter electrode 6 is further formed on the barrier metal 5. The barrier metal 5 is formed by depositing titanium nitride by PVD (Physical Vapor Deposition), CVD.

[0095] For example, an aluminum-silicon alloy (Al-Si-based alloy) can be deposited on the barrier metal 5 by PVD such as sputtering or evaporation to form the emitter electrode 6. Alternatively, a nickel alloy (Ni alloy) can be further formed on the formed aluminum-silicon alloy by electroless plating or electroplating as the emitter electrode 6. If the emitter electrode 6 is formed by electroplating, a thick metal film can be easily formed as the emitter electrode 6, so that the heat capacity of the emitter electrode 6 can be increased and the heat resistance can be improved. In addition, when a nickel alloy is further formed by electroplating after the emitter electrode 6 made of an aluminum-silicon alloy is formed by PVD, the electroplating process for forming the nickel alloy can also be performed after the processing on the second main surface side of the semiconductor substrate.

[0096] Next, as shown in Figure 15 Fig. (a), the second main surface side of the semiconductor substrate is polished to thin the semiconductor substrate to a predetermined thickness designed. The thickness of the polished semiconductor substrate can be, for example, 80 μm to 200 μm.

[0097] Next, as shown in Figure 15As shown in Fig. (b), an n-type buffer layer 3 is formed by implanting n-type impurities from the second main surface side of the semiconductor substrate. Further, a p-type collector layer 16 is formed by implanting p-type impurities from the second main surface side of the semiconductor substrate. The n-type buffer layer 3 can be formed in the IGBT region 10, the diode region 20, and the terminal region 30, or can be formed only in the IGBT region 10 or the diode region 20.

[0098] The n-type buffer layer 3 can be formed, for example, by implanting phosphorus (P) ions. Alternatively, it can be formed by implanting protons (H + +). Moreover, it can be formed by implanting both protons and phosphorus. Protons can be implanted from the second main surface of the semiconductor substrate to a deep position with relatively low acceleration energy. Additionally, by changing the acceleration energy, the depth of implanted protons can be changed relatively easily. Therefore, when forming the n-type buffer layer 3 by protons, if multiple implantations are performed while changing the acceleration energy, a wider n-type buffer layer 3 can be formed in the thickness direction of the semiconductor substrate compared to forming it by phosphorus.

[0099] In addition, since phosphorus can achieve a higher activation rate of n-type impurities compared to protons, by forming the n-type buffer layer 3 using phosphorus, even for a thinned semiconductor substrate, depletion layer breakdown can be more reliably suppressed. To further thin the semiconductor substrate, it is preferable to form the n-type buffer layer 3 by implanting both protons and phosphorus. In this case, compared to phosphorus, protons are implanted from the second main surface to a deeper position.

[0100] The p-type collector layer 16 can be formed, for example, by implanting boron (B). The p-type collector layer 16 is also formed in the terminal region 30, and the p-type collector layer 16 in the terminal region 30 becomes the p-type terminal collector layer 16a. After ion implantation from the second main surface side of the semiconductor substrate, laser annealing is performed by irradiating the second main surface with a laser, thereby activating the implanted boron to form the p-type collector layer 16. At this time, the phosphorus for the n-type buffer layer 3 implanted from the second main surface of the semiconductor substrate to a relatively shallow position is also simultaneously activated. On the other hand, since protons are activated at a relatively low annealing temperature of 380°C to 420°C, care needs to be taken not to raise the temperature of the entire semiconductor substrate above 380°C to 420°C except for the process for proton activation after proton implantation. Since laser annealing can make only the vicinity of the second main surface of the semiconductor substrate have a high temperature, it can also be used for the activation of n-type and p-type impurities after proton implantation.

[0101] Next, as Figure 16 (a) shows, an n + -type cathode layer 26 is formed in the diode region 20. The n + -type cathode layer 26 can be formed, for example, by implanting phosphorus (P). As Figure 16As shown in (a), phosphorus is selectively implanted from the second main surface side by mask processing in such a way that the boundary between the p-type collector layer 16 and the n-type cathode layer 26 is located at a position deviated from the boundary between the IGBT region 10 and the diode region 20 by a distance U1 toward the diode region 20 side. The implantation amount of the n-type impurity for forming the n-type cathode layer 26 is larger than the implantation amount of the p-type impurity for forming the p-type collector layer 16. In (a), the depths of the p-type collector layer 16 and the n-type cathode layer 26 from the second main surface are shown to be the same, but the depth of the n-type cathode layer 26 is greater than or equal to the depth of the p-type collector layer 16. Since the region for forming the n-type cathode layer 26 needs to implant n-type impurities into the region where p-type impurities have already been implanted to become an n-type semiconductor, the concentration of the p-type impurities implanted in the entire region for forming the n-type cathode layer 26 is set higher than the concentration of the n-type impurities. + type cathode layer 26 is located at a position deviated from the boundary between the IGBT region 10 and the diode region 20 by a distance U1 toward the diode region 20 side, phosphorus is selectively implanted from the second main surface side by mask processing. The implantation amount of the n-type impurity for forming the n-type cathode layer 26 is larger than the implantation amount of the p-type impurity for forming the p-type collector layer 16. + type cathode layer 26 is larger than the implantation amount of the p-type impurity for forming the p-type collector layer 16. In Figure 16 (a), it is shown that the depths of the p-type collector layer 16 and the n + type cathode layer 26 from the second main surface are the same, but the depth of the n + type cathode layer 26 is greater than or equal to the depth of the p-type collector layer 16. Since the region for forming the n + type cathode layer 26 needs to implant n-type impurities into the region where p-type impurities have already been implanted to become an n-type semiconductor, the concentration of the p-type impurities implanted in the entire region for forming the n + type cathode layer 26 is set higher than the concentration of the n-type impurities.

[0102] Next, as Figure 16 (b) shows, a collector electrode 7 is formed on the second main surface of the semiconductor substrate. The collector electrode 7 is formed over the entire surface of the IGBT region 10, the diode region 20, and the terminal region 30 on the second main surface. In addition, the collector electrode 7 can be formed over the entire surface of the semiconductor substrate, that is, the second main surface of the n-type wafer. The collector electrode 7 can be formed by depositing an aluminum-silicon alloy (Al-Si-based alloy), titanium (Ti), etc. by PVD such as sputtering or evaporation, or can be formed by laminating multiple metals such as an aluminum-silicon alloy, titanium, nickel, or gold. Moreover, the collector electrode 7 can also be formed by performing electroless plating or electroplating on the metal film formed by PVD and further forming a metal film.

[0103] The semiconductor device 100 or the semiconductor device 101 is fabricated through the above-described processes. For the semiconductor device 100 or the semiconductor device 101, since a plurality of them are fabricated in a matrix on one n-type wafer, they are cut into individual semiconductor devices 100 or semiconductor devices 101 by laser cutting or blade cutting, thereby completing the semiconductor device 100 or the semiconductor device 101.

[0104] The effects of the semiconductor device and the manufacturing method of the semiconductor device according to the present embodiment configured as described above will be described.

[0105] Since the semiconductor devices 100 and 101 of the present embodiment use aluminum as the p-type impurity of the p-type contact layer 14 and the p-type contact layer 24, the thicknesses of the p-type contact layer 14 and the p-type contact layer 24 can be set smaller than those of the n +The thickness of the p-type source layer 13 is small. The reason is that the atomic radius of aluminum is larger than that of boron. Therefore, when ion implantation is performed with the same acceleration energy, boron with a smaller atomic radius is implanted deeper, whereas aluminum with a larger atomic radius is implanted to a shallower position than boron. In addition, by using aluminum, which is a metal, as the p-type impurity, the ohmic contact property with the electrode portion can be maintained. Therefore, compared with existing semiconductor devices, the impurity concentration of the p-type contact layer can be reduced, and compared with existing semiconductor devices, the injection of a large number of holes from the p-type contact layer 14 or the p-type contact layer 24 into the n - type drift layer 1 can be suppressed. As a result, the semiconductor devices 100 and 101 of the present embodiment have the following effects: the contact resistance can be suppressed, and the recovery loss in the diode region 20 can be reduced.

[0106] In addition, for the semiconductor devices 100 and 101 of the present embodiment, the thickness ratio of the p-type contact layers 14 and 24 to the n + type source layer 13 is described as being small, but it is not limited thereto, as long as aluminum is used as the p-type impurity in the p-type contact layers 14 and 24. By configuring as described above, at least the ohmic contact property with the electrode portion can be maintained, and thereby the impurity concentration of the p-type contact layer can be reduced. Therefore, it has the following effects: the contact resistance can be suppressed, and the recovery loss in the diode region 20 can be reduced.

[0107] Embodiment 2.

[0108] Use Figure 17 to describe the semiconductor device of Embodiment 2. Figure 17 It is a cross-sectional view showing the structure of the boundary between the IGBT region and the diode region of an RC-IGBT, that is, a semiconductor device. Figure 17 It corresponds to the cross-sectional view at the dashed line G-G in the semiconductor device 100 or the semiconductor device 101 shown in Figure 1 . In addition, Figure 17 As shown by the dashed line A-A in Figure 3 , it is a cross-sectional view of the part having the n + type source layer 13 in this cross-section.

[0109] The semiconductor device of the present embodiment is different from the semiconductor device 100 or 101 of Embodiment 1 in that the p + type contact layer 44 having an impurity concentration higher than that of the p-type contact layer 24 in the diode region 20 is provided in the IGBT region 10. Since other structures of the semiconductor device of the present embodiment are the same as those of the semiconductor device 100 or 101 of Embodiment 1, the following description will focus on the differences from the semiconductor device 100 or 101.

[0110] The p-type contact layer 24 is the same as that in Embodiment 1 and is smaller than the n+ The thickness of the p-type source layer 13 is small, for example, it has a thickness of 1 / 2 of the thickness of the n-type source layer 13. In addition, it is preferable that the impurity concentration of aluminum in the p-type contact layer 24 is 1.0E+12 / cm + to 1.0E+18 / cm 3 . 3

[0111] p + The p-type contact layer 44 is a surface layer formed between the trenches, and is a semiconductor layer having boron as a p-type impurity. The concentration of the p-type impurity is 1.0E+15 / cm 3 to 1.0E+20 / cm 3 . The impurity concentration of the p-type contact layer 44 is higher than that of the p-type contact layer 24. In addition, as shown in Fig. 17, the p-type contact layer 44 is thicker than the n-type source layer 13. For example, it has a thickness of 1.5 times the thickness of the n-type source layer 13 + . + In addition, it is preferable that the p-type contact layer 44 uses boron as the p-type impurity, but it is not limited thereto. Aluminum can be used, or other p-type impurities can also be used. In addition, it is preferable that the thickness of the p-type contact layer 44 is set to be larger than the thickness of the n-type source layer 13, but it can also be set to be equal to the thickness of the n-type source layer 13 + . +

[0112] In the semiconductor device of the present embodiment configured as described above, the impurity concentration of the p-type contact layer 24 formed in the diode region 20 is lower than the impurity concentration of the p-type contact layer 44 formed in the IGBT region 10. Thus, it has the effect of being able to balance the reduction of the recovery loss and the conduction performance of the IGBT region. In addition, during the forward operation of the IGBT, in order to promote the inflow of holes into the p-type contact layer 44 and improve the latch-up tolerance, it is preferable that the thickness of the p-type contact layer 44 in the IGBT region 10 is larger than the thickness of the n-type source layer 13. By using boron or the like as the impurity or making the impurity concentration greater than or equal to 1.0E+15 / cm + , a thick p-type contact layer can be formed + . + + .

[0113] A modification of the semiconductor device of Embodiment 2 will be described + . + In the semiconductor device of the present embodiment configured as described above, the impurity concentration of the p-type contact layer 24 formed in the diode region 20 is lower than the impurity concentration of the p-type contact layer 44 formed in the IGBT region 10. Thus, it has the effect of being able to balance the reduction of the recovery loss and the conduction performance of the IGBT region. In addition, during the forward operation of the IGBT, in order to promote the inflow of holes into the p-type contact layer 44 and improve the latch-up tolerance, it is preferable that the thickness of the p-type contact layer 44 in the IGBT region 10 is larger than the thickness of the n-type source layer 13. By using boron or the like as the impurity or making the impurity concentration greater than or equal to 1.0E+15 / cm + , a thick p-type contact layer can be formed + . 3 + .

[0114] Use Figure 18 to illustrate a modification of the semiconductor device of Embodiment 2 Figure 18 And Figure 1 ​​​​The semiconductor device 100 or the semiconductor device 101 shown in FIG. 1 corresponds to the cross-sectional view taken along the dashed line GG, but is different from the cross-sectional view taken along the dashed line GG. Figure 17 Cross-sectional views Cross-sectional views at different positions. Figure 17 18 is a structure of the boundary between the IGBT region and the diode region of the RC-IGBT semiconductor device, but Figure 17 like Figure 3 The dashed line AA is shown in the cross section with n + A cross-sectional view of a portion of the type source layer 13, Figure 18 like Figure 3 The dashed line BB shows that there is no n + A cross-sectional view of a portion of the type source layer 13.

[0115] like Figure 18 As shown, the semiconductor device according to the modification of the present embodiment is different from the semiconductor device according to the present embodiment in that a p-type contact layer 14 is further formed in the boundary region on the side of the IGBT region 10. Since the other structures of the semiconductor device according to the modification are the same as those of the semiconductor device according to the present embodiment, the following description will focus on the differences.

[0116] The structure of the p-type contact layer 14 is similar to that of the p-type contact layer 14 provided in the semiconductor device of the first embodiment. + The thickness of the source layer 13 is small and has a value less than or equal to n + The thickness of the p-type source layer 13 is 1 / 2 of that of the p-type contact layer 14. In addition, the impurity concentration of aluminum in the p-type contact layer 14 is preferably 1.0E+12 / cm 3 ~1.0E+18 / cm 3 In the semiconductor device of the present embodiment, the p-type contact layer 14 is provided only on the IGBT region 10 side of the boundary region between the IGBT region 10 and the diode region 20 .

[0117] In the second embodiment, the boundary between the IGBT region 10 and the diode region 20 refers to the region closest to the diode region 20 in the IGBT region 10. + The position of the trench closest to the diode region 20 in the trench in contact with the type source layer 13. The n-type source layer 13 in the IGBT region 10 closest to the diode region 20 can be + The trench closest to the diode region 20 among the trenches contacting the source layer 13 is called a boundary trench, and is here referred to as a boundary trench 50. The boundary trench 50 is formed by providing a boundary trench electrode 50a in a trench formed in a semiconductor substrate via a boundary trench insulating film 50b.

[0118] Thus, since the p-type contact layer 14 is provided at a position close to the boundary trench 50, and on the other hand, the p + -type contact layer 44 is provided at a position far from the boundary trench 50, the amount of holes injected from the p-type contact layer of the IGBT region 10 into the n - -type drift layer 1 can be reduced near the boundary trench 50. Therefore, there is an effect that the amount of holes flowing from the IGBT region 10 into the diode region 20 can be reduced, and the recovery loss of the diode region 20 can be further reduced.

[0119] Embodiment 3.

[0120] Use Figure 19 to describe the semiconductor device of Embodiment 3. Figure 19 is a cross-sectional view showing the structure of the boundary between the IGBT region and the diode region of the RC-IGBT, i.e., the semiconductor device. Figure 19 It corresponds to the cross-sectional view taken along the dashed line G-G in the semiconductor device 100 or the semiconductor device 101 shown. In addition, Figure 1 as shown by the dashed line A-A in Figure 19 it is a cross-sectional view at a portion having the n Figure 3 -type source layer 13 in this cross-section. + type source layer 13 in this cross-section.

[0121] The semiconductor device of this embodiment has a p - -type anode layer 45 with aluminum as the p-type impurity below the p-type contact layer 24 in the diode region 20, and is different from the semiconductor device 100 or 101 of Embodiment 1 in that it does not have the n-type carrier accumulation layer 2. Since the other structures of the semiconductor device of this embodiment are the same as those of the semiconductor device 100 or 101 of Embodiment 1, the following description will focus on the differences from the semiconductor device 100 or 101.

[0122] p - -type anode layer 45 has aluminum as the p-type impurity and has a lower p-type impurity concentration than the p-type base layer 15 formed in the IGBT region 10. The p - -type anode layer 45 has an aluminum impurity concentration of 1.0E+12 / cm 3 to 1.0E+17 / cm 3 . In addition, no n-type carrier accumulation layer 2 is formed below the p - -type anode layer 45.

[0123] In addition, p -The p-type anode layer 45 may have an impurity concentration equivalent to that of the p-type base layer 15 formed in the IGBT region 10. However, since it is preferably set to be lower than the p-type impurity concentration of the p-type base layer 15, the recovery loss of the diode region 20 can be further reduced.

[0124] In the semiconductor device of this embodiment configured as described above, the p-type contact layer 24 is formed on a part of the surface layer between the trenches, and the p- - type impurity of the p-type anode layer 45 is aluminum. Therefore, it has the following effect, that is, it can suppress the injection of holes from the p-type contact layer 24 and the p- - type anode layer 45, and can further reduce the recovery loss of the diode region 20.

[0125] Embodiment 4.

[0126] Use Figure 20 to describe the semiconductor device of Embodiment 4. Figure 20 It is a cross-sectional view showing the structure of the boundary between the IGBT region and the diode region of the RC-IGBT, i.e., the semiconductor device. Figure 20 And Figure 1 corresponds to the cross-sectional view at the dashed line G-G in the semiconductor device 100 or the semiconductor device 101 shown. In addition, Figure 20 It is as Figure 3 shown by the dashed line A-A, and it is a cross-sectional view at the part where the n- + type source layer 13 is provided in this cross-section.

[0127] The semiconductor device of this embodiment is different from the semiconductor device 100 or 101 of Embodiment 1 in that the p-type collector layer 16 in the diode region 20 is dispersed in the n- + type cathode layer 26. The p-type collector layer 16 dispersed in the n- + type cathode layer 26 of the diode region 20 can be formed simultaneously with the p-type collector layer 16 of the IGBT region 10. The p-type collector layer 16 dispersed in the n- + type cathode layer 26 of the diode region 20 is in contact with the collector electrode 7 on the second main surface side and in contact with the n-type buffer layer 3 on the first main surface side.

[0128] In the semiconductor device of this embodiment configured as described above, it has the following effect, that is, during the reverse operation of the diode, since holes can be moderately injected into the n- - type drift layer, the diode performance is further improved.

[0129] Embodiment 5.

[0130] Use Figure 21 to describe the semiconductor device of Embodiment 5.Figure 21 It is a cross-sectional view showing the structure of the boundary between the IGBT region and the diode region of an RC-IGBT, i.e., a semiconductor device. Figure 21 It corresponds to the cross-sectional view at the dashed line G-G in the semiconductor device 100 or semiconductor device 101 shown in Figure 1 . Additionally, Figure 21 as shown by the dashed line A-A in Figure 3 , it is a cross-sectional view at the part where the n + -type source layer 13 is present in this cross-section.

[0131] The semiconductor device of this embodiment is different from the semiconductor device 100 or 101 of Embodiment 1 in that no trench is formed in the diode region 20. In addition, "no trench is formed in the diode region 20" means not having a structure such as the diode trench gate 21 described in Embodiment 1, and includes having a boundary trench 50 at the boundary between the IGBT region 10 and the diode region 20.

[0132] In the semiconductor device of this embodiment configured as described above, there is an effect that, by not forming a trench in the diode region 20, the conduction area of carriers becomes larger, current easily flows, and thus the turn-on voltage can be reduced.

[0133] Embodiment 6.

[0134] Use Figure 22 to describe the semiconductor device of Embodiment 6. Figure 22 It is a cross-sectional view showing the structure of the boundary between the IGBT region and the diode region of an RC-IGBT, i.e., a semiconductor device. Figure 22 It corresponds to the cross-sectional view at the dashed line G-G in the semiconductor device 100 or semiconductor device 101 shown in Figure 1 . Additionally, Figure 22 as shown by the dashed line A-A in Figure 3 , it is a cross-sectional view at the part where the n + -type source layer 13 is present in this cross-section.

[0135] The semiconductor device of this embodiment is different from the semiconductor device 100 or 101 of Embodiment 1 in that it has a concave trench contact 46 between adjacent trenches. Since the other structures of the semiconductor device of this embodiment are the same as those of the semiconductor device 100 or 101 of Embodiment 1, the following description will focus on the points different from the semiconductor device 100 or 101.

[0136] In the semiconductor device of the present embodiment, trench contacts 46 are formed recessed from the first main surface between adjacent trenches, and the emitter electrode 6 is buried in the trench contacts 46. A p-type contact layer 17 with aluminum as a p-type impurity is formed on the surface layer of the trench contacts 46 on the IGBT region 10 side, and a p-type contact layer 27 with aluminum as a p-type impurity is formed on the surface layer of the trench contacts 46 on the diode region 20 side. In addition, a barrier metal 5 is formed between the emitter electrode 6 and the p-type contact layer 17 or the p-type contact layer 27 in the trench contacts 46. The bottom of the trench contacts 46 is located on the second main surface side compared to the n + -type source layer 13. In addition, the trench contacts 46 may be formed between all adjacent trenches.

[0137] In the semiconductor device of the present embodiment configured as described above, there are the following effects. That is, since the p-type contact layer 17 is located at the bottom of the trench contacts in the IGBT region 10, the latching tolerance is improved. In addition, there is the following effect. That is, by forming the trench contacts, since the contact surface area becomes larger, the contact resistance can be further reduced.

[0138] In addition, appropriate combination, deformation, and omission of each embodiment are also included within the scope of the present invention.

[0139] Description of reference numerals

[0140] 1n - -type drift layer, 5 barrier metal, 10 IGBT region, 11 active trench gate, 11a gate trench electrode, 11b gate trench insulating film, 12 dummy trench gate, 12a dummy trench electrode, 12b dummy trench insulating film, 13n + -type source layer, 14, 17 p-type contact layer, 15 p-type base layer, 16 p-type collector layer, 16a p-type end collector layer, 20 diode region, 21 diode trench gate, 21a diode trench electrode, 21b diode trench insulating film, 24, 27 p-type contact layer, 25 p-type anode layer, 26n + -type cathode layer, 30 end region, 31 p-type end well layer, 44p + -type contact layer, 45p - -type anode layer, 46 trench contact.

Claims

1. A semiconductor device having a semiconductor substrate with an n-type drift layer between a first main surface and a second main surface opposite to the first main surface, an insulated gate bipolar transistor region and a diode region being provided adjacent to each other, and an emitter electrode being provided on the first main surface of the semiconductor substrate, The semiconductor device is characterized in that, In the insulated gate bipolar transistor region, there are provided: A p-type base layer, which is provided closer to the first main surface side than the drift layer; An n-type source layer, which is selectively provided on the first main surface side of the base layer and selectively provided on the surface layer on the first main surface side of the semiconductor substrate; A p-type first contact layer, which is provided on the first main surface side of the base layer and in the region of the surface layer on the first main surface side of the semiconductor substrate where the source layer is not provided, and this p-type first contact layer is connected to the emitter electrode; A gate trench insulating film, which is provided on the inner surface of a trench that penetrates the base layer and reaches the drift layer; A gate trench electrode, which is provided in the trench via the gate trench insulating film; And A p-type collector layer, which is provided on the surface layer on the second main surface side of the semiconductor substrate, In the diode region, there are provided: A p-type anode layer, which is provided closer to the first main surface side than the drift layer; A p-type second contact layer, which is provided on the first main surface side of the anode layer and on the surface layer on the first main surface side of the semiconductor substrate, and this p-type second contact layer is connected to the emitter electrode; and An n-type cathode layer, which is provided on the surface layer on the second main surface side of the semiconductor substrate, The second contact layer contains aluminum as a p-type impurity, The thickness of the second contact layer is less than or equal to 1 / 2 of the thickness of the source layer.

2. The semiconductor device according to claim 1, wherein, The impurity concentration of the second contact layer is less than 1.0E+18 / cm 3 .

3. The semiconductor device according to claim 1 or 2, wherein, The first contact layer contains aluminum as a p-type impurity.

4. The semiconductor device according to claim 3, wherein, The thickness of the first contact layer is smaller than the thickness of the source layer.

5. The semiconductor device according to claim 4, wherein, The thickness of the first contact layer is less than or equal to 1 / 2 of the thickness of the source layer.

6. The semiconductor device according to claim 3, wherein, The impurity concentration of the first contact layer is less than 1.0E+18 / cm 3 .

7. The semiconductor device according to claim 1 or 2, wherein, There are a plurality of the first contact layers, At least a part of the plurality of the first contact layers is a third contact layer having an impurity concentration higher than the impurity concentration of the second contact layer.

8. A semiconductor device having a semiconductor substrate with an n-type drift layer between a first main surface and a second main surface opposite to the first main surface, an insulated gate bipolar transistor region and a diode region being provided adjacent to each other, and an emitter electrode being provided on the first main surface of the semiconductor substrate, The semiconductor device is characterized in that, In the insulated gate bipolar transistor region, there are provided: A p-type base layer, which is disposed on the first main surface side compared with the drift layer; An n-type source layer, which is selectively disposed on the first main surface side of the base layer and selectively disposed on the surface layer of the first main surface side of the semiconductor substrate; A p-type first contact layer, which is disposed on the first main surface side of the base layer and disposed in the area of the surface layer of the first main surface side of the semiconductor substrate where the source layer is not provided, and this p-type first contact layer is connected to the emitter electrode; A gate trench insulating film, which is disposed on the inner surface of the trench that penetrates the base layer and reaches the drift layer; A gate trench electrode, which is disposed in the trench via the gate trench insulating film; And A p-type collector layer, which is disposed on the surface layer of the second main surface side of the semiconductor substrate, In the diode region, there is provided: A p-type anode layer, which is disposed on the first main surface side compared with the drift layer; A p-type second contact layer, which is disposed on the first main surface side of the anode layer and disposed on the surface layer of the first main surface side of the semiconductor substrate, and this p-type second contact layer is connected to the emitter electrode; and An n-type cathode layer, which is disposed on the surface layer of the second main surface side of the semiconductor substrate, The second contact layer contains aluminum as a p-type impurity, There are a plurality of the first contact layers, At least a part of the first contact layers among the plurality of the first contact layers is a third contact layer with an impurity concentration higher than that of the second contact layer, A part of the first contact layers among the plurality of the first contact layers is a fourth contact layer with an impurity concentration lower than that of the third contact layer, The fourth contact layer is located closer to the diode region side than the third contact layer.

9. A semiconductor device, which has a semiconductor substrate with an n-type drift layer between a first main surface and a second main surface opposite to the first main surface, an insulated gate bipolar transistor region and a diode region are adjacently provided, and an emitter electrode is provided on the first main surface of the semiconductor substrate, The feature of this semiconductor device is that, In the insulated gate bipolar transistor region, there is provided: A p-type base layer, which is disposed on the first main surface side compared with the drift layer; An n-type source layer, which is selectively disposed on the first main surface side of the base layer and selectively disposed on the surface layer of the first main surface side of the semiconductor substrate; A p-type first contact layer, which is disposed on the first main surface side of the base layer and disposed in the area of the surface layer of the first main surface side of the semiconductor substrate where the source layer is not provided, and this p-type first contact layer is connected to the emitter electrode; A gate trench insulating film, which is disposed on the inner surface of the trench that penetrates the base layer and reaches the drift layer; A gate trench electrode, which is disposed in the trench via the gate trench insulating film; And A p-type collector layer, which is disposed on the surface layer of the second main surface side of the semiconductor substrate, In the diode region, there is provided: A p-type anode layer, which is disposed on the first main surface side compared with the drift layer; A p-type second contact layer, which is disposed on the first main surface side of the anode layer and on the surface layer of the first main surface side of the semiconductor substrate, and this p-type second contact layer is connected to the emitter electrode; and An n-type cathode layer, which is disposed on the surface layer of the second main surface side of the semiconductor substrate, The second contact layer contains aluminum as a p-type impurity, There are a plurality of the first contact layers, At least a part of the first contact layers among the plurality of the first contact layers are third contact layers having an impurity concentration higher than the impurity concentration of the second contact layer, The thickness of the third contact layer is larger than the thickness of the source layer.

10. The semiconductor device according to any one of claims 1, 2, 8, and 9, characterized in that The anode layer contains aluminum as a p-type impurity, The impurity concentration of the anode layer is lower than the impurity concentration of the second contact layer.

11. The semiconductor device according to any one of claims 1, 2, 8, and 9, characterized in that The trench is not provided in the diode region.

12. The semiconductor device according to any one of claims 1, 2, 8, and 9, characterized in that The emitter electrode is disposed in contact with the source layer and the first contact layer.

13. The semiconductor device according to any one of claims 1, 2, 8, and 9, characterized in that A copper layer or a copper alloy layer is formed on the aluminum alloy layer of the emitter electrode.

14. The semiconductor device according to any one of claims 1, 2, 8, and 9, characterized in that There is a trench contact recessed from the first main surface between adjacent trenches, The surface layer of the trench contact is the first contact layer or the second contact layer.

15. The semiconductor device according to any one of claims 1, 2, 8, and 9, characterized in that The p-type collector layer is dispersed and disposed in the cathode layer.

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