Three-dimensional isolated super-junction structure field effect transistor and preparation method thereof

Abstract

The application relates to a three-dimensional isolated super-junction structure field effect transistor, which comprises a substrate region, a drift region, a base region, a source region, a shielding gate, a control gate, a trench insulation layer, a source, a drain, a metal gate, a P-type super-junction column and a three-dimensional insulation layer; the P-type super-junction column and the drift region are arranged on the substrate region along a first direction, and the three-dimensional insulation layer is arranged between the P-type super-junction column and the drift region; the base region is arranged above the drift region, so that the top surface of the base region is flush with the top surface of the P-type super-junction column; the source region comprises a P-type source region and an N-type source region; the source region is arranged above the base region and the P-type super-junction column; the control gate and the shielding gate are sequentially arranged on the side of the drift region from top to bottom and are respectively connected with the drift region, the base region, the source region and the P-type super-junction column through the insulation layer; the source is arranged above the source region; the drain is arranged below the substrate region; and the metal gate is arranged above the control gate. The scheme provided by the application can effectively reduce the on-resistance of the transistor.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and in particular to a three-dimensional isolated super junction structure field effect transistor and a preparation method thereof. BACKGROUND

[0002] The shield gate trench field effect transistor (SGT) has the advantages of low specific on-resistance, small static and dynamic loss, and fast switching speed. This is because it can effectively isolate the coupling between the control gate and the drain, and has obvious advantages in channel density, charge compensation effect and shield gate structure.

[0003] In related technologies, in order to further reduce the drain-source on-resistance of the transistor, a shield gate trench field effect transistor is disclosed in the patent document CN102148256B, which includes a drain region, a drift region, a dielectric layer, a split gate, a gate electrode, an n+ layer, a source electrode, a channel region, and a dielectric layer. The K value of the dielectric layer is distributed according to a certain rule, that is, the K value decreases from the source to the drain. By replacing the original side oxygen structure with a dielectric layer with a K value distributed according to a certain rule, and combining the modulation principle that the larger the K value, the stronger the modulation ability, but the smaller the corresponding longitudinal voltage drop, the electric field intensity inside the drift region is approximately uniformly distributed, thereby ensuring the withstand voltage and reducing the drain-source on-resistance.

[0004] However, due to the complex structure of the dielectric layer with a variable trend and the difficulty of processing technology, the above scheme needs to prepare a dielectric layer with a K value distributed according to a certain rule on the transistor, which greatly increases the requirements for the preparation process of the transistor, thereby increasing the time and production cost of the transistor preparation process. SUMMARY

[0005] To overcome the problems in related technologies, the present application provides a three-dimensional isolated super junction structure field effect transistor and a preparation method thereof, which can effectively reduce the on-resistance of the transistor.

[0006] The first aspect of the present application provides a three-dimensional isolated super junction structure field effect transistor, comprising:

[0007] a substrate region 1, a drift region 2, a base region 3, a source region 4, a shield gate 5, a control gate 6, a trench insulating layer 7, a source electrode, a drain electrode 9, a metal gate, a P-type super junction column 9, and a three-dimensional insulating layer 10;

[0008] The P-type super junction column 9 and the drift region 2 are arranged on the substrate region 1 along a first direction, and the three-dimensional insulating layer 10 is arranged between the P-type super junction column 9 and the drift region 2 to isolate the P-type super junction column 9 from the drift region 2; the base region 3 is arranged above the drift region 2, so that the top surface of the base region 3 is flush with the top surface of the P-type super junction column 9.

[0009] The source region 4 comprises P-type source regions 41 and N-type source regions 42 arranged in parallel with each other; the source regions are arranged above the substrate region 3 and the P-type super junction column 9;

[0010] The control gate 6 and the shielding gate 5 are arranged in sequence from top to bottom at the side of the drift region 2, and are respectively connected with the drift region 2, the substrate region 3, the source region 4 and the P-type super junction column 9 through the insulating layer 7;

[0011] The source electrode is arranged above the source region 4; the drain electrode 9 is arranged below the substrate region 1; and the metal gate is arranged above the control gate 6;

[0012] The first direction is the length direction of the control gate 6.

[0013] In an embodiment, the P-type source regions 41 are arranged on the top surface of the P-type super junction column 9, and the N-type source regions 42 are arranged on the top surface of the substrate region 3, so that the arrangement direction of the P-type source regions 41 and the N-type source regions 42 is parallel to the first direction.

[0014] In an embodiment, the bottom surface of the shielding gate 5 is connected with the substrate region 1.

[0015] In an embodiment, the doping type of the shielding gate 5 is P-type doping.

[0016] In an embodiment, the doping concentration of the shielding gate 5 is medium doping concentration.

[0017] In an embodiment, the doping concentration of the P-type source regions 41 and the N-type source regions 42 is heavy doping concentration.

[0018] The doping type of the substrate region 1 is N-type doping, and the doping concentration of the substrate region 1 is heavy doping concentration.

[0019] The doping type of the drift region 2 is N-type doping, and the doping concentration of the drift region 2 is medium doping concentration.

[0020] The doping type of the substrate region 3 is P-type doping, and the doping concentration of the substrate region 3 is medium doping concentration.

[0021] The doping type of the control gate 6 is P-type doping or N-type doping, and the doping concentration of the control gate 6 is heavy doping concentration.

[0022] The second aspect of the present application provides a preparation method of a three-dimensional isolated super junction structure field effect transistor, for preparing the three-dimensional isolated super junction structure field effect transistor as described in any one of the above, comprising:

[0023] The substrate region is made of a semiconductor material;

[0024] A drift region is formed on the substrate region by epitaxy;

[0025] A base region is formed on the drift region by ion implantation or diffusion;

[0026] A first trench and a second trench are etched on both sides of the drift region respectively;

[0027] An oxide and polysilicon are deposited in the first trench to form a trench insulation layer, a shielding gate and a control gate;

[0028] An oxide and a P-type doped semiconductor material are sequentially deposited in the second trench to form a three-dimensional insulation layer and a P-type super junction column;

[0029] A source region is formed on the base region by doping;

[0030] A source electrode is made above the source region;

[0031] A metal gate is formed above the trench;

[0032] A drain electrode is made at the bottom of the substrate region.

[0033] In an embodiment, the deposition of the oxide and the polysilicon in the first trench to form the trench insulation layer, the shielding gate and the control gate comprises:

[0034] The P-type doped semiconductor material, the oxide and the polysilicon are sequentially deposited in the first trench to form the trench insulation layer, the shielding gate and the control gate.

[0035] In an embodiment, in the sequential deposition of the P-type doped semiconductor material, the oxide and the polysilicon in the first trench to form the trench insulation layer, the shielding gate and the control gate, the doping concentration of the P-type doped semiconductor material is a medium doping concentration.

[0036] In an embodiment, the doping of the source region on the base region comprises:

[0037] The base region is doped with an N-type doped semiconductor material to form an N-type source region;

[0038] The P-type super junction column is doped with a P-type doped semiconductor material to form a P-type source region.

[0039] The technical solution provided by the present application can include the following beneficial effects:

[0040] The application provides a three-dimensional isolated super-junction structure field effect transistor, which is distinguished from a conventional shield gate trench field effect transistor, and a P-type super-junction column connected with a source region below and a substrate region above is introduced, and a drift region arranged above the substrate region forms a three-dimensional super-junction structure. The P-type super-junction column is directly connected with the substrate region, and the P-type super-junction column and the drift region forming the three-dimensional super-junction structure are isolated by a three-dimensional insulating layer, which not only effectively inhibits lateral impurity diffusion of the P-type super-junction column and the drift region in a high-temperature process, but also weakens JFET effect and effectively reduces on-resistance of the transistor due to the introduction of the three-dimensional insulating layer to bear part of the lateral voltage drop.

[0041] The P-type super-junction column and the three-dimensional insulating layer only need to be doped with a single concentration of semiconductor material and oxide on the substrate region, and thus the preparation process is simpler, and a field effect transistor with low on-resistance can be obtained compared with the patent document with the publication number CN102148256B.

[0042] It should be understood that the foregoing general description and the following detailed description are only exemplary and explanatory, and cannot limit the application. BRIEF DESCRIPTION OF DRAWINGS

[0043] The above and other objects, features and advantages of the present application will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings, in which like reference characters refer to like parts throughout the figures, and wherein:

[0044] Figure 1 is a structural schematic diagram of a three-dimensional isolated super-junction structure field effect transistor shown in an embodiment of the application;

[0045] Figure 2 is another structural schematic diagram of a three-dimensional isolated super-junction structure field effect transistor shown in an embodiment of the application;

[0046] Figure 3 is a flow schematic diagram of a preparation method of a three-dimensional isolated super-junction structure field effect transistor shown in an embodiment of the application;

[0047] Figure 4 is another flow schematic diagram of a three-dimensional isolated super-junction structure field effect transistor shown in an embodiment of the application. DETAILED DESCRIPTION

[0048] The preferred embodiments of the present application will be described in more detail with reference to the drawings. Although the preferred embodiments of the present application are shown in the drawings, it is understood that the present application can be implemented in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided so that this application will be thorough and complete, and will fully convey the scope of the application to those skilled in the art.

[0049] The terms used in this application are merely for the purpose of describing specific embodiments and are not intended to limit the present application. The singular forms "a", "said" and "the" used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term "and / or" used herein means and includes any or all possible combinations of one or more associated listed items.

[0050] It should be understood that although the terms "first", "second", "third" and the like can be used in this application to describe various information, these information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, the first information can also be referred to as the second information, and similarly, the second information can also be referred to as the first information without departing from the scope of the present application. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise specifically limited.

[0051] Embodiment one

[0052] In order to reduce the on-resistance of the transistor, the patent document with publication number CN102148256B discloses a shield gate trench field effect transistor, the K value of the dielectric layer is distributed according to a certain rule, that is, the K value is smaller and smaller from the source to the drain; however, the structure of the dielectric layer with a change trend is complex, and the processing technology is difficult, and the above scheme needs to prepare a dielectric layer with a K value distributed according to a certain rule on the transistor, which greatly increases the requirements for the preparation process of the transistor, thereby increasing the time and production cost consumed in the preparation process of the transistor.

[0053] In view of the above problems, the embodiments of the present application provide a three-dimensional isolated super junction structure field effect transistor, which can effectively reduce the on-resistance of the transistor and is simple to prepare.

[0054] The technical solutions of the embodiments of the present application will be described in detail below with reference to the drawings.

[0055] Figure 1 is a structure schematic diagram of the three-dimensional isolated super junction structure field effect transistor shown in the embodiments of the present application.

[0056] Referring toFigure 1 A three-dimensional isolated super-junction structure field effect transistor comprises:

[0057] The substrate region 1, the drift region 2, the base region 3, the source region 4, the shield gate 5, the control gate 6, the trench insulation layer 7, the source, the drain 9, the metal gate, the P-type super-junction column 9 and the three-dimensional insulation layer 10.

[0058] In the embodiment of the application, the drift region 2, the base region 3 and the source region 4 are sequentially arranged above the substrate region 1, and the control gate 6 and the shield gate 5 are sequentially arranged from top to bottom at the side of the drift region 2, which is the same as the conventional shield gate trench field effect transistor. However, the three-dimensional isolated super-junction structure field effect transistor of the embodiment of the application further comprises the P-type super-junction column 9 and the three-dimensional insulation layer 10, wherein the P-type super-junction column 9 and the drift region 2 are arranged together on the substrate region 1, and the arrangement direction of the P-type super-junction column 9 and the drift region 2 is the first direction, i.e. the length direction of the control gate 6; the three-dimensional insulation layer 10 is arranged between the P-type super-junction column 9 and the drift region 2, and is used to isolate the P-type super-junction column 9 from the drift region 2.

[0059] In the embodiment of the application, the base region 3 is arranged above the drift region 2, so that the top surface of the base region 3 is flush with the top surface of the P-type super-junction column 9, i.e. in the embodiment of the application, the P-type super-junction column 9 and the three-dimensional insulation layer 10 replace part of the drift region and the base region in the conventional shield gate trench field effect transistor, thereby forming the three-dimensional isolated super-junction structure field effect transistor shown in the embodiment of the application.

[0060] In the three-dimensional isolated super-junction structure field effect transistor shown in the embodiment of the application, the source region 4 comprises the P-type source region 41 and the N-type source region 42 which are arranged in parallel with each other; the source region is arranged above the base region 3 and the P-type super-junction column 9.

[0061] In the embodiment of the application, the control gate 6 is connected to the side surface of the base region 3, the source region 4 and the P-type super-junction column 9 through the insulation layer 7, and the shield gate 5 is connected to the side surface of the drift region 2 and the P-type super-junction column 9 through the insulation layer 7.

[0062] The source is arranged above the source region 4; the drain 9 is arranged below the substrate region 1; and the metal gate is arranged above the control gate 6.

[0063] In the embodiment of the application, the doping concentration of the P-type source region 41 and the N-type source region 42 is a heavy doping concentration; the doping type of the substrate region 1 is N-type doping, and the doping concentration of the substrate region 1 is a heavy doping concentration; the doping type of the drift region 2 is N-type doping, and the doping concentration of the drift region 2 is a medium doping concentration; the doping type of the base region 3 is P-type doping, and the doping concentration of the base region 3 is a medium doping concentration; the doping type of the control gate 6 is P-type doping or N-type doping, and the doping concentration of the control gate 6 is a heavy doping concentration.

[0064] In the embodiment of the present application, the middle doping concentration ranges from 1x1015cm-3 to 5x1016cm-3. 17 cm -3 18 cm -3 ; the heavy doping concentration ranges from 1x1018cm-3 to 5x1019cm-3. 19 cm -3 20 cm -3 .

[0065] Further, in the embodiment of the present application, the P-type super junction pillar 9 and the drift region 2 can be set to the same doping concentration.

[0066] In the embodiment of the present application, the P-type super junction pillar 9 under the source region and the drift region 2 form a three-dimensional super junction structure, the P-type super junction pillar 9 is directly connected with the N-type heavily doped substrate region 1, and the P-type super junction pillar 9 and the drift region 2 constituting the three-dimensional super junction structure are also isolated by the three-dimensional insulating layer 10, which not only effectively suppresses the lateral impurity diffusion of the P-type super junction pillar 9 and the drift region 2 during high temperature process, but also weakens the JFET effect due to the introduction of the three-dimensional insulating layer 10 to bear part of the lateral pressure drop, effectively reducing the on-resistance of the transistor.

[0067] Embodiment two

[0068] On the basis of the three-dimensional isolated super junction structure field effect transistor shown in embodiment one, the embodiment of the present application provides another three-dimensional isolated super junction structure field effect transistor, which can effectively improve the avalanche withstand and breakdown voltage of the transistor.

[0069] The technical solutions of the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0070] Figure 2 is another structure diagram of the three-dimensional isolated super junction structure field effect transistor shown in the embodiment of the present application.

[0071] Referring to Figure 2 , a three-dimensional isolated super junction structure field effect transistor comprises:

[0072] a substrate region 1, a drift region 2, a base region 3, a source region 4, a shielding gate 5, a control gate 6, a trench insulating layer 7, a source, a drain 9, a metal gate, a P-type super junction pillar 9, and a three-dimensional insulating layer 10;

[0073] ​​The source region 4 includes P-type source regions 41 and N-type source regions 42 arranged in parallel; the P-type source regions 41 are arranged on the top surface of the P-type super-junction column 9, and the N-type source regions 42 are arranged on the top surface of the substrate region 3, so that the arrangement direction of the P-type source regions 41 and the N-type source regions 42 is parallel to the first direction, that is, compared with the source region structure in the conventional shield gate trench type field effect transistor, the arrangement direction of the P-type source regions 41 and the N-type source regions 42 in the embodiment of the application is rotated by 90 degrees, so that the structure in which the length directions of the P-type source regions 41, the N-type source regions 42 and the control gate 6 are parallel is changed into a structure in which the length directions of the P-type source regions 41 and the N-type source regions 42 are perpendicular to the length direction of the control gate 6, so that the hole current generated due to avalanche flows into the P-type source regions 41 through a shorter path when the transistor is in an avalanche state, a lower positive bias voltage is obtained under the same avalanche current, the opening of the parasitic transistor is inhibited, and the avalanche resistance of the transistor is improved.

[0074] Further, in the embodiment of the application, the bottom surface of the shield gate 5 is directly connected with the substrate region 1; the doping type of the shield gate 5 is set as P-type doping; and the doping concentration of the shield gate 5 is set as medium doping concentration, so that the electric field distribution in the drift region 2 can be further improved, the electric field peak at the corner is inhibited, and the breakdown voltage of the transistor is improved.

[0075] It should be noted that, in addition to the structure of the source region 4 and the structure of the shield gate 5 described above, the remaining structure of the three-dimensional isolated super-junction structure field effect transistor shown in the embodiment of the application has been described in detail in the first embodiment, and will not be described here again.

[0076] The three-dimensional isolated super-junction structure field effect transistor shown in the embodiment of the application is different from the conventional shield gate trench type field effect transistor in that the arrangement direction of the P-type source regions and the N-type source regions in the source region is changed from being perpendicular to the first direction to being parallel to the first direction, so that the hole current generated due to avalanche flows into the P-type source regions through a shorter path when the transistor is in an avalanche state, the opening of the parasitic transistor is inhibited, and the avalanche resistance of the transistor is improved. In addition, the shield gate is changed from being composed of a heavily doped polysilicon to being a P-type medium doping structure directly connected with the substrate region, so that the electric field distribution in the drift region is further improved, and the breakdown voltage of the transistor is improved.

[0077] Embodiment three

[0078] Corresponding to the foregoing three-dimensional isolated super-junction structure field effect transistor embodiments, the application further provides a preparation method of a three-dimensional isolated super-junction structure field effect transistor and corresponding embodiments.

[0079] Figure 3is a flowchart of a preparation method of a three-dimensional isolated super-junction structure field effect transistor shown in the embodiments of the present application.

[0080] Referring to Figure 3 A preparation method of a three-dimensional isolated super-junction structure field effect transistor, comprising:

[0081] 301, making a substrate region with a semiconductor material;

[0082] In the embodiments of the present application, the substrate region is made of N-type heavily doped semiconductor material, that is, the doping type of the substrate region is set to N-type doping, and the doping concentration is a heavy doping concentration.

[0083] 302, epitaxially forming a drift region on the substrate region;

[0084] In the embodiments of the present application, different epitaxial processes can be used according to actual needs, including but not limited to: vapour phase epitaxy (VPE) or chemical vapor deposition (CVD).

[0085] 303, forming a base region on the drift region by ion implantation or diffusion;

[0086] The ion implantation process is a process of doping silicon material. In actual application, the power device product is placed at one end of the ion implanter, and the doping ion source is arranged at the other end of the ion implanter. At the end of the doping ion source, the doping atoms are ionized and thus have a certain charge, and are accelerated to a super-high speed by an electric field, penetrate the surface layer of the product, and use the momentum of the atoms to implant the doping atoms into the power device to form a doped region.

[0087] The diffusion process is a process of doping pure impurity atoms on the surface of silicon material. In actual application, diborane or phosphine is usually used as the ion source, and the pure impurity atoms are doped into the surface of the silicon material by using intermittent diffusion or replacement diffusion.

[0088] It should be noted that the preparation method of the base region is not strictly limited in the embodiments of the present application, and in actual process, the preparation of the base region can be completed by selecting the above different processes according to actual needs.

[0089] 304, etching a first trench and a second trench on both sides of the drift region, respectively;

[0090] In the embodiments of the present application, the drift region is etched by a photolithography process, and the remaining photoresist is removed by wet etching or dry etching.

[0091] In the embodiment of the present application, the second trench is etched to the top surface of the substrate region, that is, the top surface of the substrate region serves as the bottom of the second trench, and the depth of the second trench is equal to the sum of the depths of the base region and the drift region.

[0092] 305. Depositing oxide and polysilicon in the first trench to form a trench insulation layer, a shield gate and a control gate;

[0093] In the embodiment of the present application, oxide, heavily doped polysilicon, oxide and heavily doped polysilicon can be sequentially deposited in the first trench to form the trench insulation layer, the shield gate and the control gate, or oxide, medium doped polysilicon, oxide and heavily doped polysilicon can be sequentially deposited in the first trench to form the trench insulation layer, the shield gate and the control gate, which can be adjusted according to actual needs, and is not limited herein.

[0094] 306. Depositing oxide and P-type doped semiconductor material in the second trench to form a three-dimensional insulation layer and a P-type super junction column;

[0095] In the embodiment of the present application, the doping concentration of the P-type doped semiconductor material used in step 306 is medium doping concentration.

[0096] It should be noted that the execution timing of step 305 and step 306 in the embodiment of the present application is not strictly limited, that is, step 306 can also be executed before step 305, or the two can be executed in parallel.

[0097] 307. Doping to form a source region on the base region;

[0098] Specifically, N-type heavily doped semiconductor material and P-type heavily doped semiconductor material are respectively doped to form N-type source regions and P-type source regions on the base region.

[0099] 308. Fabricating a source electrode above the source region;

[0100] 309. Forming a metal gate above the trench;

[0101] 310. Fabricating a drain electrode at the bottom of the substrate region.

[0102] It should be noted that the execution timing of steps 308 to 310 in the embodiment of the present application is not strictly limited, and in actual application, steps 308 to 310 can be executed in any order, or the three can be executed in parallel.

[0103] The embodiment of the present application provides a preparation method of a three-dimensional isolated super-junction structure field effect transistor, a first groove and a second groove are etched on two sides of a drift region, an oxide and a P-type doped semiconductor material are sequentially deposited in the second groove, a three-dimensional insulating layer and a P-type super-junction column are formed, a three-dimensional super-junction structure is formed with the drift region, and the preparation process is simple; since the second groove is directly etched to the top surface of the substrate region, the P-type super-junction column is directly connected with the substrate region, the P-type super-junction column and the drift region constituting the three-dimensional super-junction structure are further isolated by the three-dimensional insulating layer, the lateral impurity diffusion of the P-type super-junction column and the drift region in a high-temperature process is effectively inhibited, and since the three-dimensional insulating layer bears part of the lateral pressure drop, the JFET effect is weakened, and the on-resistance of the transistor is effectively reduced.

[0104] Embodiment four

[0105] The embodiment of the present application provides a preparation method of a three-dimensional isolated super-junction structure field effect transistor and an embodiment, which is used for preparing the three-dimensional isolated super-junction structure field effect transistor in the above-mentioned embodiment two.

[0106] Figure 4 Another flowchart of the preparation method of the three-dimensional isolated super-junction structure field effect transistor is shown in the embodiment of the present application.

[0107] Referring to Figure 4 A preparation method of a three-dimensional isolated super-junction structure field effect transistor, comprising:

[0108] 401, a substrate region is made of a semiconductor material;

[0109] In the embodiment of the present application, the step 401 is consistent with the step 301 in the embodiment three, and details are not repeated here.

[0110] 402, a drift region is formed on the substrate region by epitaxy;

[0111] In the embodiment of the present application, the step 402 is consistent with the step 302 in the embodiment three, and details are not repeated here.

[0112] 403, a base region is formed on the drift region by ion implantation or diffusion;

[0113] In the embodiment of the present application, the step 403 is consistent with the step 303 in the embodiment three, and details are not repeated here.

[0114] 404, a first groove and a second groove are etched on two sides of the drift region respectively;

[0115] In the embodiment of the present application, the first groove is etched to the top surface of the substrate region, that is, the groove bottom of the first groove is the top surface of the substrate region, that is, the groove depth of the first groove is equal to the sum of the depth of the base region and the depth of the drift region.

[0116] 405. Depositing P-type doped semiconductor material, oxide and polysilicon in the first trench in sequence to form trench insulating layer, shielding gate and control gate;

[0117] In the embodiment of the present application, P-type medium doped semiconductor material, oxide and heavily doped polysilicon are deposited in the first trench in sequence to form trench insulating layer, shielding gate and control gate, so that the bottom surface of the shielding gate is directly connected with the substrate region.

[0118] 406. Depositing oxide and P-type doped semiconductor material in the second trench in sequence to form three-dimensional insulating layer and P-type super junction column;

[0119] In the embodiment of the present application, the P-type doped semiconductor material used in step 406 has medium doping concentration.

[0120] It should be noted that the execution sequence of step 405 and step 406 in the embodiment of the present application is not strictly limited, that is, step 406 can also be executed before step 405, or the two can be executed in parallel.

[0121] 407. Forming N-type source region by doping N-type doped semiconductor material on the substrate region;

[0122] 408. Forming P-type source region by doping P-type doped semiconductor material on the P-type super junction column;

[0123] In the embodiment of the present application, the semiconductor material used in step 407 and step 408 is heavily doped semiconductor material.

[0124] It should be noted that the execution sequence of step 407 and step 408 in the embodiment of the present application is not strictly limited, that is, step 408 can also be executed before step 407, or the two can be executed in parallel.

[0125] 409. Manufacturing source electrode above the source region;

[0126] 410. Forming metal gate above the trench;

[0127] 411. Manufacturing drain electrode at the bottom of the substrate region.

[0128] It should be noted that the execution sequence of step 409 to step 411 in the embodiment of the present application is not strictly limited, and in actual application process, step 409 to step 411 can be executed in any order, or the three can be executed in parallel.

[0129] The embodiment of the present application provides a preparation method of a three-dimensional isolated super junction structure field effect transistor, a first groove is etched on one side of a drift region, and the first groove is directly etched to the top surface of a substrate region, after P-type doped semiconductor material, oxide and polysilicon are sequentially deposited in the first groove, a groove insulating layer, a control gate and a shielding gate directly connected with the substrate region are formed, the electric field distribution in the drift region is further improved, and the breakdown voltage of the transistor is improved; in addition, an N-type source region is formed by doping N-type doped semiconductor material on the base region, and a P-type source region is formed by doping P-type doped semiconductor material on the P-type super junction column, so that the arrangement direction of the P-type source region and the N-type source region is a first direction, i.e. the length direction of the control gate, so that the hole current generated by the avalanche flows into the P-type source region in a shorter path when the transistor is in an avalanche state, the opening of a parasitic transistor is inhibited, and the avalanche resistance of the transistor is improved.

[0130] As to the device in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment related to the method, and will not be described in detail here.

[0131] The scheme of the present application has been described in detail above with reference to the drawings. In the above embodiments, the description of each embodiment is focused on, and the parts not described in detail in a certain embodiment can be referred to the relevant description of other embodiments. It should also be known by those skilled in the art that the actions and modules involved in the specification are not necessarily required by the present application. In addition, it can be understood that the steps in the method of the embodiments of the present application can be adjusted, combined and reduced in sequence according to actual needs, and the modules in the device of the embodiments of the present application can be combined, divided and reduced according to actual needs.

[0132] The flowcharts and block diagrams in the drawings show the possible implementation architecture, function and operation of the system and method according to the embodiments of the present application. In this regard, each block in the flowchart or block diagram can represent a module, a program segment or a part of code containing one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks can also occur in different order from that marked in the drawings. For example, two consecutive blocks can actually be executed substantially in parallel, and they can also be executed in reverse order in some cases, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, and the combination of blocks in the block diagram and / or flowchart, can be implemented by a dedicated hardware-based system performing the specified function or operation, or can be implemented by a combination of special-purpose hardware and computer instructions.

[0133] Having described various embodiments of the application, it is to be understood that the above description is meant not to limit and not to encompass all of the possible embodiments. Many modifications and variations of this application can be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. It is intended that the scope of the application be defined by the scope of the patent and by the claims as allowed by the patent office, which can include adaptations based on the description, equivalents, and / or substitutions of elements individually or collectively to the entire disclosure.

Claims

1. A three-dimensional isolated superjunction field-effect transistor, characterized in that, include: Substrate region (1), drift region (2), substrate region (3), source region (4), shielding gate (5), control gate (6), trench insulating layer (7), source, drain (8), metal gate, P-type superjunction pillar (9) and three-dimensional insulating layer (10); The P-type superjunction pillar (9) and the drift region (2) are disposed on the substrate region (1) along the first direction. The three-dimensional insulating layer (10) is disposed between the P-type superjunction pillar (9) and the drift region (2) to isolate the P-type superjunction pillar (9) from the drift region (2). The substrate region (3) is disposed above the drift region (2) such that the top surface of the substrate region (3) is flush with the top surface of the P-type superjunction pillar (9). The top surface of the substrate region (3) and the top surface of the P-type superjunction pillar (9) are both in contact with the bottom surface of the source region. The bottom surface of the P-type superjunction pillar (9) and the bottom surface of the drift region (2) are directly in contact with the substrate region (1). The source region (4) includes a P-type source region (41) and an N-type source region (42) arranged in parallel with each other; the source region is located above the substrate region (3) and the P-type superstructure column (9); The control gate (6) and the shielding gate (5) are arranged sequentially from top to bottom on the side of the drift region (2), and are connected to the drift region (2), the substrate region (3), the source region (4) and the P-type superjunction pillar (9) respectively through the insulating layer (7). The bottom surface of the shielding gate (5) is connected to the substrate region (1), and the doping type of the shielding gate (5) is P-type doping. The source electrode is disposed above the source region (4); the drain electrode (8) is disposed below the substrate region (1); and the metal gate electrode is disposed above the control gate (6). The first direction is the length direction of the control gate (6).

2. The three-dimensional isolated superjunction field-effect transistor according to claim 1, characterized in that, The P-type source region (41) is disposed on the top surface of the P-type superstructure column (9), and the N-type source region (42) is disposed on the top surface of the substrate region (3), such that the arrangement direction of the P-type source region (41) and the N-type source region (42) is parallel to the first direction.

3. The three-dimensional isolated superjunction field-effect transistor according to claim 1, characterized in that, The doping concentration of the shielding gate (5) is medium.

4. The three-dimensional isolated superjunction field-effect transistor according to claim 1, characterized in that, The doping concentrations of the P-type source region (41) and the N-type source region (42) are both heavily doped. The substrate region (1) is N-type doped, and the doping concentration of the substrate region (1) is a heavily doped concentration. The drift region (2) is N-type doped, and the doping concentration of the drift region (2) is medium. The substrate region (3) is P-type doped, and the doping concentration of the substrate region (3) is medium. The doping type of the control gate (6) is P-type doping or N-type doping, and the doping concentration of the control gate (6) is a heavy doping concentration.

5. A method for fabricating a three-dimensional isolated superjunction field-effect transistor, characterized in that, The method for fabricating a three-dimensional isolated superjunction field-effect transistor as described in any one of claims 1-4 includes: The substrate region is fabricated using semiconductor materials; A drift region is epitaxially formed on the substrate region; A matrix region is formed on the drift region by ion implantation or diffusion. A first groove and a second groove are respectively etched on both sides of the drift region; Oxides and polysilicon are deposited in the first trench to form a trench insulating layer, a shielding gate, and a control gate; Oxide and P-type doped semiconductor material are sequentially deposited in the second trench to form a three-dimensional insulating layer and a P-type superjunction pillar; A source region is formed by doping on the substrate region; A source electrode is fabricated above the source region; A metal gate is formed above the trench; A drain electrode is fabricated at the bottom of the substrate region.

6. The method for fabricating a three-dimensional isolated superjunction field-effect transistor according to claim 5, characterized in that, The deposition of oxide and polysilicon within the first trench to form a trench insulating layer, a shielding gate, and a control gate includes: P-type doped semiconductor material, oxide and polysilicon are sequentially deposited in the first trench to form the trench insulating layer, the shielding gate and the control gate.

7. The method for fabricating a three-dimensional isolated superjunction field-effect transistor according to claim 6, characterized in that, In the process of sequentially depositing P-type doped semiconductor material, oxide, and polysilicon in the first trench to form the trench insulating layer, the shielding gate, and the control gate, the doping concentration of the P-type doped semiconductor material is medium.

8. The method for fabricating a three-dimensional isolated superjunction field-effect transistor according to claim 5, characterized in that, The doping of the substrate region to form the source region includes: An N-type source region is formed by doping the substrate region with an N-type doped semiconductor material. A P-type source region is formed on the P-type superjunction pillar by doping with a P-type doped semiconductor material.

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