A mos device with an extended drain region and a method of manufacturing the same

Abstract

The application discloses a MOS device with extended drain and a manufacturing method thereof. The MOS device comprises a substrate, an epitaxial layer, a gate, the epitaxial layer is arranged on the substrate and has the same conductive type as the substrate, the epitaxial layer is formed with a well region, a channel doped region, an extended drain region, a drain region and a source region; the gate is formed on the epitaxial layer; the channel doped region is located below the gate, and the conductive type of the channel doped region is opposite to that of the epitaxial layer; the well region is located below the channel doped region and is in contact with the extended drain region, and the conductive type of the well region is the same as that of the epitaxial layer; and the conductive type of the source region is opposite to that of the substrate. The application reduces the thermal process of processing, simplifies the process, improves the device consistency, suppresses the hot carrier injection effect of the device, improves the doping concentration of the extended drain region, further reduces the on-resistance of the device, and improves the device performance.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of power semiconductor devices, and particularly relates to a MOS device with extended drain region and a manufacturing method thereof. BACKGROUND

[0002] Figure 1 is a structural schematic diagram of a traditional power application LDMOS device, in which the source region 13, the drift region 14 and the drain region 15 are of the same conductivity type, the conductivity type of the channel region below the gate region 11 is the same as that of the body region and opposite to that of the source region 13, and the drift region 14 increases the breakdown voltage of the LDMOS, thereby increasing the output power of the device.

[0003] The traditional LDMOS device forms a well region 17 by ion implantation, and through long-time high-temperature annealing, the body region is laterally diffused and in contact with the drift region 14 to form the channel of the device. Figure 1 Long-time high-temperature annealing increases the thermal process of the device, reduces the consistency of the device, and causes the junction depth of the device to be deep, thereby increasing the capacitance of the device. The traditional LDMOS device is prone to hot carrier injection effect in a high-voltage and large-current scenario, carriers enter the gate oxide layer 12 region, intensifies the changes of parameters such as on-resistance, saturation current, threshold voltage and breakdown voltage of the device, and reduces the service life of the device. Moreover, with the increase of the doping concentration of the drift region 14, the hot carrier effect is intensified. In order to improve the efficiency of the device, the designer wants to increase the doping concentration of the drift region 14, and the traditional LDMOS device is trapped in the hot carrier injection effect, and cannot reduce the on-resistance to improve the performance of the device.

[0004] How to provide an LDMOS device with reduced on-resistance and improved device performance is an urgent problem to be solved. SUMMARY

[0005] The main purpose of the present application is to provide a MOS device with extended drain region, so as to overcome the shortcomings of the prior art.

[0006] Another purpose of the present application is to provide a manufacturing method of the MOS device with extended drain region.

[0007] In order to achieve the above-mentioned purpose of the application, the technical scheme adopted by the present application comprises: a MOS device with extended drain region, comprising:

[0008] a substrate,

[0009] an epitaxial layer arranged on the substrate and having the same conductivity type as the substrate, and a well region, a channel doping region, a drain extension region, a drain region and a source region are formed in the epitaxial layer;

[0010] a gate formed on the epitaxial layer;

[0011] The channel doping region is located below the gate, and the conductivity type of the channel doping region is the same as that of the drain extension region, the drain region and the source region, and is opposite to that of the epitaxial layer;

[0012] The well region is located below the channel doping region and in contact with the drain extension region, and the conductivity type of the well region is the same as that of the epitaxial layer;

[0013] The conductivity type of the source region is opposite to that of the substrate, and the conductivity types of the drain extension region, the drain region and the source region are the same.

[0014] In a preferred embodiment, the MOS device further comprises a well region contact region arranged in the epitaxial layer, the well region contact region is located above the well region and in contact with the source region, and the conductivity type of the well region contact region is the same as that of the well region.

[0015] In a preferred embodiment, the thickness of the epitaxial layer is 2um-50um.

[0016] In a preferred embodiment, the well region is formed by ion implantation, the energy range of the ion implantation is 100KEV-800KEV, and the concentration range is 5E12-5E14.

[0017] In a preferred embodiment, the channel doping region is formed by ion implantation, the energy range of the ion implantation is 15KEV-250KEV, and the concentration range is 1E11-5E12.

[0018] In a preferred embodiment, the MOS device comprises a gate oxide layer and a polysilicon gate, the gate oxide layer is arranged on the epitaxial layer and above the channel doping region, the polysilicon gate is arranged on the gate oxide layer, and the polysilicon gate forms the gate through etching.

[0019] In a preferred embodiment, the thickness of the gate oxide layer is 5nm-30nm.

[0020] Embodiments of the present application provide a manufacturing method of a MOS device with drain extension, the method comprising:

[0021] S100, growing an epitaxial layer on a substrate, the conductivity type of the epitaxial layer is the same as that of the substrate;

[0022] S200, implanting a well region on the epitaxial layer by ion implantation process, the conductivity type of the well region is the same as that of the epitaxial layer;

[0023] S300, implanting a channel doping region on the epitaxial layer by ion implantation process, the conductivity type of the channel doping region is opposite to that of the epitaxial layer;

[0024] S400, depositing a gate oxide layer on the epitaxial layer, depositing a polysilicon gate above the gate oxide layer, and etching the polysilicon gate to form a gate;

[0025] S500, forming a well contact region, a source region, a drain region extension and a drain region on the epitaxial layer by an ion implantation process, the well contact region having the same conductivity type as the well region, the source region having a conductivity type opposite to that of the substrate, the drain region extension, the drain region and the source region having the same conductivity type.

[0026] Compared with the prior art, the present application has at least the following beneficial effects: the present application adopts a double-channel design, reduces the thermal process of processing, simplifies the process, improves the consistency of the device, more importantly, suppresses the hot carrier injection effect of the device, increases the doping concentration of the drain region extension, further reduces the on-resistance of the device, and improves the performance of the device. The on-resistance of the device of the present application is reduced by 40%, and the current density is about 2.1 times that of the traditional LDMOS device. BRIEF DESCRIPTION OF DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings described below are only some embodiments described in the present application, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of these drawings.

[0028] Figure 1 is a structural schematic diagram of a traditional power application LDMOS device;

[0029] Figure 2 is a structural schematic diagram of a MOS device of the drain region extension of the present application;

[0030] Figure 3 is a structural schematic diagram corresponding to step S100 of the present application;

[0031] Figure 4 is a structural schematic diagram corresponding to step S200 of the present application;

[0032] Figure 5 is a structural schematic diagram corresponding to step S300 of the present application;

[0033] Figure 6 is a structural schematic diagram corresponding to step S400 of the present application;

[0034] Figure 7 is a flowchart of the manufacturing method of the present application.

[0035] Reference signs:

[0036] 21. Gate, 22. Gate oxide layer, 23. Source region, 24. Drain extension region, 25. Drain region, 26. Well contact region, 27. Well region, 28. Epitaxial layer, 29. Substrate, 210. Channel doping region. DETAILED DESCRIPTION

[0037] The present invention will be more fully understood through the following detailed description, which should be read in conjunction with the accompanying drawings. Detailed embodiments of the present invention are disclosed herein; however, it should be understood that the disclosed embodiments are merely exemplary of the present invention, which can be embodied in various forms. Therefore, the specific functional details disclosed herein should not be construed as limiting, but rather as a basis for the claims and as a representative basis for teaching those skilled in the art to employ the present invention in various ways in virtually any appropriately detailed embodiment.

[0038] like Figure 2 As shown, a MOS device with an extended drain region 25 disclosed in an embodiment of the present invention includes a substrate 29, an epitaxial layer 28, a gate oxide layer 22, a gate 21, a well region 27, a channel doping region 210, a drain extension region 24, a drain region 25, a source region 23 and a well region contact region 26, wherein the epitaxial layer 28 is formed on the substrate 29, specifically grown on the substrate 29, the thickness of the epitaxial layer 28 is preferably 2um~50um, and the conductivity type of the epitaxial layer 28 is the same as the conductivity type of the substrate 29.

[0039] A gate oxide layer 22 is formed on the epitaxial layer 28. Specifically, the gate oxide layer 22 is deposited on the epitaxial layer 28. The thickness of the gate oxide layer 22 is preferably in the range of 5 nm to 30 nm. A polysilicon gate is formed above the gate oxide layer 22. Specifically, a polysilicon gate is deposited on the gate oxide layer 22 and then etched to form the gate 21.

[0040] The well region 27, channel doping region 210, drain extension region 24, drain region 25, source region 23, and well contact region 26 are formed in the epitaxial layer 28 through ion implantation. First, the well region 27 is implanted in the epitaxial layer 28. The conductivity type of the well region 27 is the same as that of the epitaxial layer 28. The energy range of the ion implantation in the well region 27 is 100KEV to 800KEV, and the concentration range is 5E12 to 5E14.

[0041] The channel doping region 210 is formed in the epitaxial layer 28 by an ion implantation process, and is located above the well region 27 and close to one end of the gate 21 arranged on the epitaxial layer 28, and is located below the gate 21, the conductivity type of the channel doping region 210 is opposite to that of the epitaxial layer 28, and is the same as that of the drain extension region 24, the drain region 25 and the source region 23 before the formation of the gate 21. The energy range of the ion implantation of the channel doping region 210 is 15KEV-250KEV, and the concentration range is 1E11-5E12.

[0042] The source region 23 and the well contact region 26 are both formed above the well region 27 by an ion implantation process, the well contact region 26 and the source region 23 are in contact, the source region 23 and the well region 27 are in contact with the drain extension region 24, and the conductivity type of the well contact region 26 is the same as that of the well region 27, the conductivity type of the source region 23 is opposite to that of the substrate 29, and the conductivity types of the drain extension region 24, the drain region 25 and the source region 23 are the same.

[0043] As shown in Figure 7 , a manufacturing method of a drain extension MOS device disclosed by the embodiment of the present application comprises the following steps:

[0044] As shown in Figure 3 , S100, an epitaxial layer 28 is grown on a substrate 29, and the conductivity type of the epitaxial layer 28 is the same as that of the substrate 29.

[0045] In the embodiment, the thickness of the epitaxial layer 28 is preferably 2um-50um.

[0046] As shown in Figure 4 , S200, a well region 27 is implanted on the epitaxial layer 28 by an ion implantation process, and the conductivity type of the well region 27 is the same as that of the epitaxial layer 28.

[0047] As shown in Figure 5 , S300, a channel doping region 210 is implanted on the epitaxial layer 28 by an ion implantation process, and the conductivity type of the channel doping region 210 is opposite to that of the epitaxial layer 28.

[0048] In the embodiment, the channel doping region 210 is located above the well region 27 and is the same as the conductivity types of the drain extension region 24, the drain region 25 and the source region 23 before the formation of the gate 21.

[0049] As shown in Figure 6 , S400, a gate 21 oxide layer is deposited on the epitaxial layer 28, a polysilicon gate is deposited above the gate 21 oxide layer, and the gate 21 is etched on the polysilicon gate.

[0050] In this embodiment, the thickness of the gate 21 oxide layer is preferably in the range of 5nm to 30nm.

[0051] S500, by ion implantation process on the epitaxial layer 28, the well contact region 26, the source region 23, the drain extension region 24 and the drain region 25 are formed, the conductivity type of the well contact region 26 is the same as the well region 27, the conductivity type of the source region 23 is opposite to the conductivity type of the substrate 29, and the conductivity type of the drain extension region 24, the drain region 25 and the source region 23 is the same.

[0052] In this embodiment, the source region 23 and the well contact region 26 are both formed above the well region 27, the well contact region 26 and the source region 23 are in contact, and the source region 23 and the well region 27 are in contact with the drain extension region 24. The conductivity type of the well contact region 26 is the same as the well region 27, the conductivity type of the source region 23 is opposite to the conductivity type of the substrate 29, and the conductivity type of the drain extension region 24, the drain region 25 and the source region 23 is the same.

[0053] The present application adopts a double channel design. When the gate 21 voltage is slightly higher than the threshold voltage, the channel of the device is located in the body, away from the silicon surface, and the current path is also away from the silicon surface. Under the condition of the gate voltage that is most likely to cause hot carrier injection effect, the probability of hot carrier injection is reduced. When the threshold voltage is further increased, the channel is located on the silicon surface like a traditional LDMOS, which ensures the transconductance and performance of the device when the gate voltage is high. The double channel device structure of the present application reduces the potential difference between the gate 21 and the channel when the gate 21 voltage is slightly higher than the threshold voltage, and the potential difference is equivalent when the gate 21 voltage is high, thereby reducing the probability of hot carrier injection effect of the device and greatly improving the current density of the device. In addition, the device structure of the present application reduces the high-temperature thermal annealing process of the well region 27, thereby improving the consistency of the device.

[0054] Aspects, embodiments, features, and examples of the present application are to be considered in all respects as illustrative only and not restrictive, the scope of the present application being defined only by the claims. Other embodiments, modifications, and uses will occur to those skilled in the art upon consideration of the specification, and are intended to be included within the scope of the application as defined by the claims. It will be apparent to one of ordinary skill in the art that aspects, embodiments, features, and examples of the present application can be practiced in other ways than those specifically set forth herein without departing from the spirit and scope of the claimed application.

[0055] The use of the title and sections in the present application does not imply a limitation on the present application; each section can be applied to any aspect, embodiment or feature of the present application.

[0056] Unless specifically stated otherwise, the use of the terms "comprise", "comprises", "comprising", "have", "has", "having", or "includes" or "including" shall not be construed as being limited to the inclusion of only the recited elements or steps, but rather, the use of these terms shall be interpreted as specifying the existence of the recited elements or steps without excluding the presence of one or more additional elements or steps.

[0057] It should be understood that the order of steps or order for performing certain actions is immaterial so long as the present teachings remain operable. Moreover, two or more steps or actions can be conducted simultaneously or

[0058] While the present application has been described with reference to illustrative embodiments, those with ordinary skill in the art will understand that various other modifications can be made, and numerous apparatus other than those described herein can be utilized according to the teachings of the present application. Additionally, the steps and / or actions of a method or algorithm described in connection with the present application can be carried out in the reverse order, and / or certain steps and / or actions can be performed concurrently, omitted, and / or substituted for one another, and / or additional steps and / or actions can be added, without departing from the scope of the present application. Accordingly, the present application is not intended to be limited to the particular disclosed embodiment, as such, but is intended to cover all modifications and equivalents falling within the scope of the present application. Furthermore, any use of the terms first, second, etc. do not denote any order or importance, but rather the terms first, second, etc. are used to distinguish one element from another.

Claims

1. A MOS device with an extended drain region, characterized in that: include: substrate, an epitaxial layer, disposed on the substrate and having the same conductivity type as the substrate, wherein the epitaxial layer is formed with a well region, a channel doping region, a drain extension region, a drain region, and a source region; a gate formed on the epitaxial layer; The channel doping region is located below the gate, and the conductivity type of the channel doping region is the same as the conductivity type of the drain extension region, the drain region, and the source region, and is opposite to the conductivity type of the epitaxial layer, and a portion of the channel doping region is located within the drain extension region; The well region is located below the channel doping region and in contact with the drain extension region, and the conductivity type of the well region is the same as that of the epitaxial layer; The conductivity type of the source region is opposite to that of the substrate, and the conductivity types of the drain extension region, the drain region and the source region are the same; The MOS device has a dual-channel device structure. When the gate voltage is higher than the threshold voltage, the channel of the MOS device is located in the body, away from the silicon surface, and the current path is also away from the silicon surface; when the threshold voltage is increased, the channel of the MOS device is located on the silicon surface.

2. The MOS device with an extended drain region according to claim 1, wherein: The MOS device further includes a well region contact region disposed in the epitaxial layer. The well region contact region is located above the well region and in contact with the source region. The conductivity type of the well region contact region is the same as that of the well region.

3. The MOS device with an extended drain region according to claim 1, wherein: The thickness of the epitaxial layer is 2um~50um.

4. The MOS device with an extended drain region according to claim 1, wherein: The well region is formed by ion implantation, and the energy range of the ion implantation is 100KEV to 800KEV.

5. The MOS device with an extended drain region according to claim 1, wherein: The channel doping region is formed by ion implantation, and the energy range of the ion implantation is 15KEV to 250KEV.

6. The MOS device with an extended drain region according to claim 1, wherein: The MOS device includes a gate oxide layer and a polysilicon gate. The gate oxide layer is arranged on the epitaxial layer and located above the channel doping region. The polysilicon gate is arranged on the gate oxide layer, and the polysilicon gate is etched to form the gate.

7. The MOS device with an extended drain region according to claim 6, wherein: The thickness of the gate oxide layer is in the range of 5 nm to 30 nm.

8. A method for manufacturing a MOS device with an extended drain region, characterized in that: The method comprises: S100, growing an epitaxial layer on a substrate, wherein the conductivity type of the epitaxial layer is the same as that of the substrate; S200, implanting an ion implantation process into a well region on the epitaxial layer, wherein the conductivity type of the well region is the same as that of the epitaxial layer; S300, implanting a channel doping region into the epitaxial layer using an ion implantation process, wherein the conductivity type of the channel doping region is opposite to that of the epitaxial layer, and a portion of the channel doping region is located in the drain extension region; S400, depositing a gate oxide layer on the epitaxial layer, depositing a polysilicon gate on the gate oxide layer, and etching the polysilicon gate to form a gate; S500, forming a well contact region, a source region, a drain extension region, and a drain region on the epitaxial layer by an ion implantation process, wherein the well contact region has the same conductivity type as the well region, the source region has a conductivity type opposite to that of the substrate, and the drain extension region, the drain region, and the source region have the same conductivity type; The MOS device has a dual-channel device structure. When the gate voltage is higher than the threshold voltage, the channel of the MOS device is located in the body, away from the silicon surface, and the current path is also away from the silicon surface; when the threshold voltage is increased, the channel of the MOS device is located on the silicon surface.

9. The method for manufacturing a MOS device with an extended drain region according to claim 8, wherein: The thickness of the epitaxial layer is 2um-50um, and the thickness of the gate oxide layer is 5nm-30nm.

10. The method for manufacturing a MOS device with an extended drain region according to claim 8, wherein: The well region is formed by ion implantation, and the energy range of the ion implantation is 100KEV to 800KEV; the channel doping region is formed by ion implantation, and the energy range of the ion implantation is 15KEV to 250KEV.

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