A capacitor, manufacturing method and electronic device

Abstract

The present application relates to a capacitor, a manufacturing method and an electronic device. The capacitor comprises: a bottom electrode, the bottom electrode comprising a plurality of stacked cylindrical portions, the plurality of stacked cylindrical portions gradually decreasing in diameter from bottom to top; a dielectric film, covering the outside of the bottom electrode; and a top electrode, covering the outside of the dielectric film. The plurality of stacked cylindrical portions gradually decreasing in diameter from bottom to top form the bottom electrode, so that the height of the bottom electrode is easy to adjust during manufacturing, and the bottom electrode is not easy to collapse when the height is higher.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically to a capacitor, a manufacturing method, and an electronic device. Background Technology

[0002] As the integration density of semiconductor devices increases, the horizontal area of ​​a single cell on the semiconductor substrate gradually decreases. Even with this decrease, a sufficiently high capacitance needs to be maintained to store charge in the semiconductor device. However, to maintain this capacitance, the height of the lower electrode needs to be increased to expand the contact area between the lower electrode and the dielectric layer. However, this increased height can cause the lower electrode to collapse due to an excessively large aspect ratio. Furthermore, the high aspect ratio can cause bending in the middle or upper part of the lower electrode, leading to contact between adjacent lower electrodes. Therefore, a structure is needed that allows the capacitor to have a large capacitance while also being resistant to collapse.

[0003] Therefore, there is a need for a capacitor, manufacturing method, and electronic device that can have a large capacitance while being resistant to collapse. Summary of the Invention

[0004] To address the aforementioned problems, this application provides a capacitor comprising: a bottom electrode comprising a plurality of stacked cylindrical portions, the diameter of which gradually decreases from bottom to top; a dielectric film covering the bottom electrode; and a top electrode covering the dielectric film.

[0005] To address the aforementioned problems, this application also provides a method for manufacturing a capacitor, comprising the following steps: forming a bottom electrode, the bottom electrode comprising a plurality of stacked cylindrical portions, the diameter of the plurality of cylindrical portions gradually decreasing from bottom to top; forming a dielectric film on the outside of the bottom electrode; and depositing a top electrode on the dielectric film.

[0006] To address the aforementioned problems, this application also provides an electronic device, including the aforementioned capacitor structure.

[0007] The advantage of this application is that the stacked cylindrical portions with diameters gradually decreasing from bottom to top form the bottom electrode, making the height of the bottom electrode easy to adjust during manufacturing, and it is not easy to collapse when the height is high. Attached Figure Description

[0008] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0009] Figure 1 A schematic diagram of the capacitor structure according to an embodiment of this application is shown;

[0010] Figure 2 A schematic diagram illustrating the steps of a method for manufacturing a capacitor according to an embodiment of this application is shown;

[0011] Figure 3 This paper shows a schematic diagram of a structure in which a bottom electrode layer is formed on a semiconductor substrate according to an embodiment of the present application;

[0012] Figure 4 A schematic diagram of the structure of the first layer electrode according to an embodiment of this application is shown;

[0013] Figure 5 A schematic diagram of the structure in which a bottom electrode layer is formed on the first electrode layer according to an embodiment of this application is shown;

[0014] Figure 6 A schematic diagram of the structure in which the third layer of electrodes is formed according to an embodiment of this application is shown;

[0015] Figure 7 A schematic diagram of the structure for forming the bottom electrode according to an embodiment of this application is shown. Detailed Implementation

[0016] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0017] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0018] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0019] Figure 1 A schematic diagram of the capacitor structure according to an embodiment of this application is shown, such as... Figure 1 The bottom electrode 110A shown comprises three cylindrical portions stacked sequentially, with their diameters gradually decreasing from bottom to top. The bottommost cylindrical portion (first layer electrode) 111a has the largest diameter, the middle cylindrical portion (second layer electrode) 111b has a smaller diameter than the bottommost cylindrical portion 111a, and the topmost cylindrical portion (third layer electrode) 111c has a smaller diameter than the middle cylindrical portion 111b. A dielectric film 120 covers the bottom electrode 110A, and a top electrode 130 covers the dielectric film 120. The structure of the bottom electrode 110B is the same as that of the bottom electrode 110A, and will not be described further here.

[0020] Figure 2 A method for manufacturing a capacitor is illustrated. An example method begins with operation 201, forming a bottom electrode 110A. The bottom electrode 110A includes a plurality of stacked cylindrical portions, the diameter of which gradually decreases from bottom to top. Figure 3 As shown, a first inter-metal dielectric (IMD) 101 is deposited on a semiconductor substrate 100. The first IMD 101 is etched to form a trench. A bottom electrode material is deposited in the trench to form a bottom electrode layer 115a. Figure 4 As shown, the bottom electrode layer 115a and the first intermetallic dielectric layer 101 are planarized, and a first layer electrode 111a with a cylindrical bottom electrode 110A is formed in the first intermetallic dielectric layer.

[0021] Secondly, such as Figure 1 As shown, multiple intermetallic dielectric layers are sequentially deposited on the first electrode 111a, and a subsequent electrode with a smaller diameter than the previous electrode is formed in each intermetallic dielectric layer and stacked on top of the previous electrode, until the last electrode is formed. The stacked electrodes form a cylindrical bottom electrode 110A. Figure 5 As shown, a subsequent intermetallic dielectric layer 102 is deposited on the first electrode 111a. The subsequent intermetallic dielectric layer 102 is etched to form a hole on the first electrode 111a that corresponds to the first electrode 111a and has a diameter smaller than the first electrode 111a. Bottom electrode material is deposited in the hole to form a subsequent bottom electrode layer 115b that is stacked on and in contact with the first electrode 111a.

[0022] After planarization, a bottom electrode layer 115b and a subsequent intermetallic dielectric layer 102 are formed. In the subsequent intermetallic dielectric layer 102, a subsequent electrode with a diameter smaller than the previous electrode 111b is formed and stacked on top of the previous electrode 111b. This process is repeated until the last electrode layer is formed, and the stacked electrode layers form a cylindrical bottom electrode 110A. (Example...) Figure 6 As shown, a subsequent intermetallic dielectric layer 103 is deposited on the bottom electrode layer 111b, and a subsequent electrode 111c with a smaller diameter than the previous electrode 111b and stacked on top of the previous electrode 111b is formed in the subsequent intermetallic dielectric layer 103. Figure 7 As shown, after the last electrode layer is formed, the intermetallic dielectric layers are etched to expose the stacked bottom electrode 110A.

[0023] Continue with step 202, forming a dielectric film 120 outside the bottom electrode. Continue with step 203, depositing a top electrode 130 on the dielectric film 120. Figure 1 The bottom electrodes shown include 110A and 110B.

[0024] Methods for etching the intermetallic dielectric layers include wet etching and etch-back. Materials for the intermetallic dielectric layers include oxides and silicon-based spin-on hard masks (SOH). Electrode materials include elemental metals, metal alloys, and metal nitrides. Elemental metals include Co, Ni, Cu, Al, Pd, Pt, Ru, Re, Mo, Ta, Ti, Hf, Zr, W, Ir, Eu, Nd, Er, and La. Metal alloys include alloys of these elemental metals. Metal nitrides include oxides of these elemental metals.

[0025] In one embodiment, an electronic device may include the semiconductor structure described above.

[0026] This electronic device includes smartphones, computers, tablets, wearable smart devices, artificial intelligence devices, power banks, etc.

[0027] The method in this application forms a bottom electrode by gradually reducing the pattern and / or size of a design rule. Multiple cylindrical portions with progressively decreasing diameters from bottom to top are stacked. This bottom electrode is less prone to collapse even at higher heights, reducing the defect rate. Furthermore, controlling the etch-back of the intermetallic dielectric layer allows adjustment of the height of each cylindrical portion, thereby adjusting the height of the bottom electrode. Because the diameter of each cylindrical portion in the bottom electrode gradually decreases from bottom to top, the resulting air gap after removing the intermetallic dielectric layer also gradually decreases from bottom to top. This structure also has advantages in capping processes.

[0028] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0029] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A method for manufacturing a capacitor, characterized in that, The steps include the following: A bottom electrode is formed, the bottom electrode comprising a plurality of stacked cylindrical portions, the diameter of the plurality of cylindrical portions gradually decreasing from bottom to top; A dielectric film is formed outside the bottom electrode; A top electrode is deposited on the dielectric film; The process of forming a bottom electrode, comprising a plurality of stacked cylindrical portions, wherein the diameter of the plurality of cylindrical portions gradually decreases from bottom to top, includes the following steps: The first electrode layer forming a columnar bottom electrode in a first intermetallic dielectric layer on a semiconductor substrate specifically includes: depositing a first intermetallic dielectric layer on the semiconductor substrate; etching the first intermetallic dielectric layer to form a groove; depositing a bottom electrode material in the groove to form a bottom electrode layer; planarizing the bottom electrode layer and the first intermetallic dielectric layer to form a first electrode layer with a columnar bottom electrode in the first intermetallic dielectric layer. Multiple intermetallic dielectric layers are sequentially deposited on the first electrode layer, and a subsequent electrode layer with a smaller diameter than the previous electrode layer is formed in each intermetallic dielectric layer layer and stacked on the previous electrode layer layer, until the last electrode layer is formed. The stacked electrodes form a cylindrical bottom electrode. The dielectric layers between the metals are etched to expose the stacked bottom electrodes.

2. The method for manufacturing a capacitor as described in claim 1, characterized in that, The step of sequentially depositing multiple intermetallic dielectric layers on the first electrode layer and forming a subsequent electrode with a smaller diameter than the previous electrode layer in each intermetallic dielectric layer, stacked on top of the previous electrode layer, until the last electrode layer is formed, with the stacked electrode layers forming a cylindrical bottom electrode, includes the following steps: A subsequent intermetallic dielectric layer is deposited on the first electrode layer; After etching, an intermetallic dielectric layer is formed on the first electrode, and the hole with a diameter smaller than the first electrode is formed on the first electrode. A bottom electrode material is deposited in the hole to form a second bottom electrode layer that is stacked on top of and in contact with the first electrode layer. Planarize the bottom electrode layer and the intermetallic dielectric layer, and form a bottom electrode with a smaller diameter than the previous electrode and stacked on the previous electrode in the intermetallic dielectric layer. This process continues until the last layer of electrodes is formed, and the stacked layers of electrodes form a cylindrical bottom electrode.

3. The method for manufacturing a capacitor as described in claim 1, characterized in that, The methods for etching the dielectric layers between the metals include wet etching and back etching.

4. The method for manufacturing a capacitor as described in claim 1, characterized in that, The material of the intermetallic dielectric layer includes oxides.

5. The method for manufacturing a capacitor as described in claim 1, characterized in that, The materials of the electrodes include: elemental metals, metal alloys, and metal nitrides.

6. The method for manufacturing a capacitor as described in claim 1, characterized in that, The dielectric film is made of silicon oxide or silicon nitride.

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