Structure comprising a polycrystalline resistor having a polycrystalline region containing a dopant underneath

Abstract

The present disclosure relates to a structure including a polycrystalline resistor having a polycrystalline region containing a dopant underneath. The structure includes: a semiconductor substrate; and a polycrystalline resistor region located above the semiconductor substrate. The polycrystalline resistor region includes semiconductor material in a polycrystalline form. The dopant-containing polycrystalline region is located between the polycrystalline resistor region and the semiconductor substrate.

Description

Technical Field

[0001] The present disclosure relates to resistors, and more particularly, to polycrystalline resistors having an underlying polycrystalline region containing dopants. Background Art

[0002] Resistors are used in integrated circuit (IC) structures for a variety of purposes. For example, in radio frequency (RF) applications such as power amplifiers, increases in current density can lead to instabilities. To address these instabilities, ballast polycrystalline resistors can be provided to help regulate the voltage flowing through the IC structure to avoid overloads. For example, as the current flowing through the ballast resistor increases, its resistance increases, while as the current flowing through the ballast resistor decreases, its resistance decreases.

[0003] One challenge with ballast and other polycrystalline resistors is that they typically include a polycrystalline portion located above an oxide layer. The oxide layer can be relatively thick and prevent adequate heat transfer, which can cause the device to overheat. For example, the oxide can be provided as shallow trench isolation (STI). One way to improve heat transfer is to thin the oxide, for example to the thickness typically used for a gate dielectric layer. Unfortunately, using thinner oxides for polycrystalline resistors can cause the oxide to decompose, which can result in electrical noise being transmitted into the substrate and degrading performance. Summary of the Invention

[0004] One aspect of the present disclosure relates to a structure comprising: a semiconductor substrate; a polycrystalline resistor region located above the semiconductor substrate, the polycrystalline resistor region comprising a semiconductor material in a polycrystalline form; and a dopant-containing polycrystalline region located between the polycrystalline resistor region and the semiconductor substrate, wherein the dopant of the dopant-containing polycrystalline region comprises an inert gas element.

[0005] Another aspect of the present disclosure includes a structure comprising: a semiconductor substrate; a polycrystalline resistor region located above the semiconductor substrate, the polycrystalline resistor region comprising semiconductor material in a polycrystalline form; an argon-containing polycrystalline region located between the polycrystalline resistor region and the semiconductor substrate; and an active device located above the semiconductor substrate, wherein the active device comprises a single crystalline body and the argon-containing polycrystalline region extends below the active device.

[0006] Yet another aspect of the present disclosure relates to a method comprising: implanting an inert gas element into a first single crystal region in a semiconductor substrate to form a first dopant-containing polycrystalline region, and one of: implanting into an oxide layer in the semiconductor substrate to form a dopant-containing polycrystalline region below the oxide layer, and implanting into a second single crystal region in the semiconductor substrate to form a second dopant-containing polycrystalline region; annealing to reform an upper portion of the first dopant-containing polycrystalline region into a reformed single crystal active region, leaving a portion of the first dopant-containing polycrystalline region below the reformed single crystal active region as an isolation layer; and forming an active device above the reformed single crystal active region, and forming a polycrystalline resistor above one of the oxide layer and the second dopant-containing polycrystalline region, and wherein the oxide layer is part of one of a trench isolation arrangement and a gate dielectric layer.

[0007] The foregoing and other features of the present disclosure will become apparent from the following more particular description of embodiments of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Embodiments of the present disclosure will be described in detail with reference to the following drawings, wherein like reference numerals represent like elements, and wherein:

[0009] Figure 1 A cross-sectional view of a polycrystalline resistor on a bulk semiconductor substrate according to an embodiment of the present disclosure is shown.

[0010] Figure 2 A cross-sectional view of a polycrystalline resistor on a bulk semiconductor substrate according to another embodiment of the present disclosure is shown.

[0011] Figure 3 A cross-sectional view of a polycrystalline resistor on a bulk semiconductor substrate according to other embodiments of the present disclosure is shown.

[0012] Figure 4 A cross-sectional view of a polycrystalline resistor on a bulk semiconductor substrate according to further embodiments of the present disclosure is shown.

[0013] Figure 5 An enlarged cross-sectional view of a silicide layer over a polysilicon resistor is shown according to an embodiment of the present disclosure.

[0014] Figure 6 An enlarged cross-sectional view of a silicide layer over a polysilicon resistor according to other embodiments of the present disclosure is shown.

[0015] Figure 7 A cross-sectional view of a polycrystalline resistor on an SOI semiconductor substrate according to an embodiment of the present disclosure is shown.

[0016] Figure 8A cross-sectional view of a polycrystalline resistor on an SOI semiconductor substrate according to another embodiment of the present disclosure is shown.

[0017] Figure 9 A cross-sectional view of a polycrystalline resistor on an SOI semiconductor substrate according to other embodiments of the present disclosure is shown.

[0018] Figure 10 A cross-sectional view of a polycrystalline resistor on an SOI semiconductor substrate according to another embodiment of the present disclosure is shown.

[0019] Figure 11 A cross-sectional view illustrating implantation of dopants into a preliminary structure for application of a method according to an embodiment of the present disclosure is shown.

[0020] Figure 12 A cross-sectional view of annealing for recrystallizing a region of a structure is shown in accordance with an embodiment of the present disclosure.

[0021] Figure 13 A cross-sectional view illustrating the removal of a nitride cap from a region of a structure according to an embodiment of the present disclosure.

[0022] Figure 14 A cross-sectional view is shown in which active devices and polysilicon resistors are formed in a region of a structure according to an embodiment of the present disclosure.

[0023] It should be noted that the drawings of the present disclosure are not necessarily drawn to scale. The drawings are intended to depict only typical aspects of the present disclosure and therefore should not be considered to limit the scope of the present disclosure. In the drawings, like reference numerals represent like elements between the drawings. DETAILED DESCRIPTION

[0024] In the following description, reference is made to the accompanying drawings which form a part of the present invention and which illustrate, by way of illustration, specific exemplary embodiments in which the present teachings may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present teachings, and it is understood that other embodiments may be used and changes may be made without departing from the scope of the present teachings. Therefore, the following description is illustrative only.

[0025] It will be understood that when an element, such as a layer, region, or substrate, is referred to as being "on" or "over" another element, it can be directly on the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly on" or "directly over" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or there may be intervening elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0026] References in the specification to "one embodiment" or "an embodiment" of the present disclosure and other variations thereof mean that the specific features, structures, characteristics, etc. described in conjunction with the embodiment are included in at least one embodiment of the present disclosure. Therefore, the phrases "in one embodiment" or "in an embodiment" and any other variations appearing throughout the specification do not necessarily refer to the same embodiment. It should be understood that the use of any of " / ", "and / or", and "at least one" in the context of, for example, "A / B", "A and / or B", and "at least one of A and B" is intended to include selecting only the first listed option (A), or only the second listed option (B), or both options (A and B). As another example, in the context of "A, B, and / or C" and "at least one of A, B, and C," these phrases are intended to encompass selecting only the first listed option (A), or only the second listed option (B), or only the third listed option (C), or only the first and second listed options (A and B), or only the first and third listed options (A and C), or only the second and third listed options (B and C), or all three options (A, B, and C). As will be apparent to one of ordinary skill in the art, this scenario can be extended to many of the listed options.

[0027] Embodiments of the present disclosure include a structure comprising a semiconductor substrate and a polycrystalline resistor region located above the semiconductor substrate. The polycrystalline resistor region includes a semiconductor material in a polycrystalline form. A dopant-containing polycrystalline region is located between the polycrystalline resistor region and the semiconductor substrate. The dopant may include an inert gas element. The dopant-containing polycrystalline layer eliminates the need to thin the oxide layer below the polysilicon resistor and improves the self-cooling characteristics of the resistor by improving heat dissipation to the substrate. The dopant-containing polysilicon isolation region located below the active device also reduces parasitic losses to the semiconductor substrate, ultimately providing thermal conductivity with reduced substrate coupling and improved frequency response. The dopant-containing polycrystalline layer can be used alone for the polycrystalline resistor. Alternatively, the dopant-containing polycrystalline layer can be used below the gate dielectric layer for the polycrystalline resistor, or below the shallow trench isolation (STI) for the polycrystalline resistor. The dopant-containing polycrystalline layer can also be used for the polycrystalline resistor above the well region.

[0028] Figure 1-4 and Figure 7-10 1 and 2. Cross-sectional views of structures 100 according to various embodiments of the present disclosure are shown. Each figure shows a corresponding structure 100 including a polycrystalline resistor 106 adjacent to an optional active device 102 (e.g., a field effect transistor). As will be described, the formation of a dopant-containing polycrystalline region 104 for the polycrystalline resistor 106 may affect the structure of the active device 102.

[0029] An embodiment of the structure 100 includes a semiconductor substrate. Figure 1-4 According to some embodiments of the present disclosure, the structure 100 may include a bulk semiconductor substrate 110. The semiconductor substrate 110 may include, but is not limited to, silicon, germanium, silicon germanium, silicon carbide, and one or more semiconductor materials having a chemical formula of Al X1 Ga X2 In X3 As Y1 P Y2 N Y3 Sb Y4 A material composed of a III-V compound semiconductor of a defined composition, wherein X1, X2, X3, Y1, Y2, Y3 and Y4 represent relative proportions, each of which is greater than or equal to zero and X1+X2+X3+Y1+Y2+Y3+Y4=1 (1 is the total relative molar amount). Other suitable substrates include those having a composition of Zn A1 Cd A2 Se B1 Te B2 II-VI compound semiconductors, wherein A1, A2, B1, and B2 are relative proportions, each greater than or equal to zero, and A1+A2+B1+B2=1 (1 is the total molar amount). In addition, part or all of the semiconductor substrate may be deformed.

[0030] Structure 100 may optionally include active devices 102. Active devices 102 may include any now known or later developed transistors. Figure 1 A non-limiting example of an active device 102 is shown. For clarity, the reference numerals for active devices 102 are only in FIG. Figure 1 . The active device 102 may include, for example, source / drain regions 112, a channel region 114, a gate 116, a gate dielectric layer 118 located between the gate 116 and the channel region 114, and a gate spacer 120 located around the gate 116. The source / drain regions 112 may include any suitable dopant located within the semiconductor substrate 110. The gate 116 may include polysilicon. A gate cap (not shown), such as nitride, may also be formed over the gate region. Alternatively, the active device 102 may include, for example, a capacitor, a diode junction, a resistor, and / or other electrically active elements.

[0031] The gate dielectric layer 118 may include any now known or later developed gate dielectric material, such as, but not limited to, hafnium silicate (HfSiO), hafnium oxide (HfO2), zirconium silicate (ZrSiO x), zirconium oxide (ZrO2), silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), a high-k material, or any combination thereof. Spacer 120 may include any currently known or later developed spacer material, such as silicon nitride. Contacts 122 may be provided through interlayer dielectric 124 to source / drain regions 112 and gate 116. Contacts 122 may include any currently known or later developed contact structure and material.

[0032] Active device 102 is separated from polysilicon resistor 106 by trench isolation 130. Trench isolation (TI) 130 comprises a trench etched into semiconductor substrate 110 and filled with an insulating material, such as an oxide, to isolate one region of the substrate from an adjacent region of the substrate. One or more transistors and / or passive devices (e.g., polysilicon resistor 106, inductor, etc.) can be disposed in the region isolated by TI 130. Each TI 130 may be formed of any now known or later developed substance to provide electrical insulation, and may include, for example: silicon nitride (Si3N4), silicon oxide (SiO2), fluorinated SiO2 (FSG), hydrogenated silicon oxycarbon (SiCOH), porous SiCOH, borophosphosilicate glass (BPSG), silsesquioxane, carbon (C) doped oxides including atoms of silicon (Si), carbon (C), oxygen (O) and / or hydrogen (H) (i.e., organosilicates), thermosetting polyarylene ether, spin-on silicon-carbon-containing polymer materials, near frictionless carbon (NFC), or layers thereof. TI 130 may be provided as shallow trench isolation (STI) or deep trench isolation (DTI). In Figure 1-4 In embodiments of the structure, the active device 102 may include a single crystalline body 132 (eg, silicon) and the dopant-containing polycrystalline region 104 may extend under the active device 102 , eg, under the single crystalline body 132 and the TI 130 .

[0033] The structure 100 also includes a polycrystalline resistor 106 having a polycrystalline resistor region 140 located above the semiconductor substrate 110. The polycrystalline resistor region 140 can include a semiconductor material 142 in a polycrystalline form. The semiconductor material 142 can be any polycrystalline material described herein for the semiconductor substrate 110. In some embodiments, the semiconductor material 142 includes polycrystalline silicon, and the semiconductor substrate 110 includes silicon (single crystal). As shown, the active device 102 can include a polycrystalline gate 116, which, as previously described, is in the same layer as the resistor region 140. Therefore, the resistor region 140 is not necessarily embedded in the semiconductor substrate 110. The TI 130 electrically isolates the active device 102 from the polycrystalline resistor 106.

[0034] The structure 100 also includes a dopant-containing polycrystalline region 104 located between the polycrystalline resistor region 140 and the semiconductor substrate 110. Figure 1 In the embodiment of the present invention, the dopant-containing polycrystalline region 104 contacts the underside 144 of the polycrystalline resistor region 140. That is, the dopant-containing polycrystalline region 104 (hereinafter referred to as "polycrystalline region 104") is in direct contact with the underside 144 of the polycrystalline resistor region 140 (hereinafter referred to as "resistor region 140") without any intervening material. The polycrystalline region 104 improves the self-cooling characteristics of the resistor by improving heat dissipation to the substrate.

[0035] As will be described, the polycrystalline region 104 can be formed by any now known or later developed doping process (e.g., ion implantation). The dopant in the polycrystalline region 104 can include an inert gas element, such as helium (He), neon (Ne), argon (Ar), krypton (Kr), xenon (Xe), radon (Rn), or a combination thereof. In a specific embodiment, the dopant can include argon (Ar). Thus, the polycrystalline region 104 can be an argon-containing polycrystalline region. The spacer 126 can be positioned adjacent to the polycrystalline region 140 located above the semiconductor substrate 110. The spacer 126 can include, for example, silicon nitride.

[0036] Figure 2 and 3 Cross-sectional views of other embodiments of the resistor region 140 are shown. In each of these embodiments, an oxide layer 146 is located between the resistor region 140 and the polycrystalline region 104. Here, the polycrystalline region 104 provides additional resistance and isolation for the resistor region 140 without increasing the thermal resistance to heat transfer that would cause the resistor region 140 to overheat. Figure 2 One embodiment is shown in which the oxide layer 146 is part of the gate dielectric layer 118. That is, the gate dielectric layer 118, which may be formed with the active device 102, remains above the polycrystalline region 104 and below the resistor region 140. Figure 3 An embodiment is shown in which oxide layer 146 is part of a trench isolation arrangement. In this example, oxide layer 146 can be part of TI 130 formed to, for example, isolate active device 102 from other structures.

[0037] Figure 4 A cross-sectional view of another embodiment of a structure 100 is shown. Figure 4 Shown with Figure 1 The structure shown is similar to structure 100, but also includes a well region 150 located in the semiconductor substrate 110 below the polycrystalline region 104. Here, the resistor region 140 can also be used with the polycrystalline region 104 located above the well region 150 (i.e., the well implant) in the semiconductor substrate 110. The well region 150 can include any desired dopant, such as a particular polarity suitable for the active device 102.

[0038] like Figure 1-4As shown, the structure 100 may further include a first contact 152 and a second contact 154 on the resistor region 140. The first and second contacts 152, 154 are spatially separated. The distance between the contacts 152, 154 may control the resistance value provided by the resistor region 140. Figure 1-4 As shown, in some embodiments, the structure 100 may include a silicide layer 158 located on the resistor region 140. In one embodiment, as shown in FIG. Figure 5 As shown, the silicide layer 158 includes an uninterrupted silicide layer 160 extending from the first contact 152 to the second contact 154. This arrangement can enable the resistor region 140 to be used, for example, as a ballast resistor, where the low sheet resistance of the silicide can form a low impedance resistor for device ballasting purposes. Figure 6 As shown, in other embodiments, the structure 100 may have first and second contacts 152 and 154 located on a discontinuous silicide layer 162 within a silicide barrier layer 164. The discontinuous silicide layer 162 and the silicide barrier layer 164 are located on the resistor region 140. The silicide layers 160, 162 may be formed using any now known or later developed technique, such as performing an in-situ pre-clean, depositing a metal (e.g., titanium, nickel, cobalt, etc.), performing an anneal to react the metal with the polysilicon, and removing unreacted metal.

[0039] Figure 7-10 The semiconductor-on-insulator (SOI) substrate 210 is shown instead of the bulk semiconductor substrate 110 ( Figure 1-4 ) are used in embodiments of the structure 100. In these embodiments, the active device 102 can be constructed as described above, or as a fin field effect transistor. The SOI substrate 210 includes a semiconductor-on-insulator (SOI) layer 212 located on a buried insulator layer 214, which is located on a bulk semiconductor substrate 216. The SOI layer 212 and substrate 216 may include the semiconductor substrate 110 ( Figure 1-4 ) and any semiconductor material listed above. The choice of insulator layer 214 depends largely on the target application, with sapphire being used for radiation-sensitive applications and silicon oxide being preferred for improving performance and reducing short channel effects in microelectronic devices. The exact thickness of the buried insulator layer 214 and the SOI layer 212 also vary widely depending on the target application. In these embodiments, the structure 100 may also include active devices 102 located on the SOI substrate 210. However, in the case of an SOI substrate 210, the polycrystalline region 104 does not extend below the active devices 102.

[0040] Figure 7A cross-sectional view of an SOI embodiment is shown in which the polycrystalline region 104 contacts the underside 144 of the resistor region 140. That is, the polycrystalline region 104 is in direct contact with the underside 144 of the resistor region 140 without intervening materials.

[0041] Figure 8 and 9 A cross-sectional view of the structure 100 is shown with an SOI substrate 210, wherein an oxide layer 146 is located between the resistor region 140 and the polycrystalline region 104. Here, the polycrystalline region 104 improves the self-cooling characteristics of the resistor by improving heat dissipation to the substrate. Figure 8 An embodiment is shown in which the oxide layer 146 is part of the gate dielectric layer 118. That is, the gate dielectric layer 118 may be formed with the active device 102 and remain above the polycrystalline region 104 and below the resistor region 140. Figure 9 An embodiment is shown in which oxide layer 146 is part of a trench isolation arrangement. In this example, oxide layer 146 is part of TI 130 formed to, for example, isolate active device 102 from other structures.

[0042] Figure 10 A cross-sectional view of another embodiment of the structure 100 using an SOI substrate 210 is shown. Figure 10 As shown, structure 100 also includes a well region 150 in SOI layer 210 below poly region 104. Here, resistor region 140 may also be used with poly region 104 located above well region 150 (ie, well implant) in SOI layer 112.

[0043] As previously described, contacts 152, 154 and silicide layer 160 may also be used on SOI substrate 210, such as Figure 7-10 shown.

[0044] refer to Figure 11-14 , a method of forming the structure 100 according to an embodiment of the present disclosure will now be described. It should be noted that although the bulk semiconductor substrate 110 ( Figure 1-4 ) describes the method, but it is also applicable to SOI substrate 210 ( Figure 7-10 ). Figure 11-14 The structure 100 is shown formed at multiple lateral positions ( Figure 1-4 、 Figure 7-10 ) to illustrate the formation of the active device 102 and the various resistor regions 140 and the polycrystalline region 104.

[0045] Figure 11A cross-sectional view of a preliminary structure 220 is shown. At this stage, the TI 130 has been formed in the semiconductor substrate 110 using any now known or later developed technique to create a plurality of electrically isolated regions 222, 224, 226. Region 222 is used for active devices 102 ( Figure 1-4 ) and includes a first single crystal region 223 (dashed box). Region 224 is used for the polycrystalline resistor 106 ( Figure 2-3 For illustrative purposes, region 224 has an oxide layer 146 shown as TI 130, as shown in FIG. Figure 3 As shown, it should be appreciated that the oxide layer 146 may also include the gate dielectric layer 118, as shown. Figure 2 As shown. Region 226 is used for another embodiment of the polysilicon resistor 106 ( Figure 1 ). The region 226 includes a second single crystal region 227 (dashed line frame) located in the semiconductor substrate 110 for the polycrystalline resistor 106 without an oxide layer ( Figure 1 ). Region 226 also includes a nitride cap 228 located thereon. Any nitride caps located over regions 222, 224 have been removed at this stage.

[0046] Figure 11 Also shown is the introduction of an inert gas element, for example via ion implantation of an inert gas (arrows), into: a first single-crystal region 223 in the semiconductor substrate 110 to form a first dopant-containing polycrystalline region 240. Additionally, depending on the form and number of regions 224, 226 provided on the substrate 110, the inert gas element may be implanted into: the region 224 and the oxide layer 146 in the semiconductor substrate 110 to create a dopant-containing polycrystalline region 242 below the oxide layer 146; and / or the region 226 and the second single-crystal region 227 in the semiconductor substrate 110 to create a second dopant-containing polycrystalline region 244. The dopant-containing polycrystalline regions 240, 242, 244 ultimately provide the polycrystalline region 104 ( Figure 1-4 、 Figure 7-10 ). Any form of mask 246 may be used to guide the implantation.

[0047] In implantation (or doping), the dose and energy level are specified and / or the final doping level can be specified. 2 ) and energy level (specified in keV (kiloelectronvolts)), giving the number of atoms per cubic centimeter (atoms / cm 3) is the doping level (concentration in the substrate). The atomic number is usually specified in exponential notation, where a number such as "3E15" means 3 times 10 to the 15th power, or "3" followed by 15 zeros (3,000,000,000,000,000). Specifically, per cubic centimeter (cm 3 ) of water has approximately 1E23 (100,000,000,000,000,000,000) hydrogen and oxygen atoms. An example of doping is approximately 1E12 to 1E13 atoms / cm 2 The dose and energy of about 40 to 80 keV are used to implant argon (Ar) to produce 1E17 to 1E18 atoms / cm 3 Doping level (atoms / cm 3 Can also be written as cm 3 The energy level can be controlled in a known manner to control the depth of penetration of the dopant into the semiconductor substrate 110. As indicated, the polycrystalline region 104 ( Figure 1-4 、 Figure 7-10 The doping of the polycrystalline regions 240, 242, 243 may include implanted inert gas ions, such as helium (He), neon (Ne), argon (Ar), krypton (Kr), xenon (Xe), radon (Rn), or a combination thereof. In a specific embodiment, the dopant may include implanted argon (Ar) ions. That is, the polycrystalline region 104 is an argon-containing polycrystalline region.

[0048] Figure 12 The first dopant-containing polycrystalline region 240 ( Figure 11 ) is reformed into a reformed single crystal active region 252 (ie, for active device 102 ( Figure 1 )) is a cross-sectional view of an anneal (curved arrow) of the first active region 252. The anneal can be of any duration and temperature necessary to achieve the desired amount of recrystallization. The anneal leaves the first dopant-containing polycrystalline region 240 ( Figure 11 ) as an isolation layer 254. The isolation layer 254 below the active device 102 reduces parasitic losses to the semiconductor substrate 110 and ultimately provides thermal conductivity with reduced substrate coupling and improved frequency response. Figure 7-10 ), due to the presence of the buried insulator layer 214, the isolation layer 254 is not formed, see e.g. Figure 7-10 . Figure 12 Also shown is reforming of the gate dielectric layer 118 in region 222 , for example by performing a deposition after annealing.

[0049] Figure 13The nitride cap 228 is shown removed from over the second dopant-containing polycrystalline region 244, for example, via a hot phosphorus wet etch. At this stage, any well implant formation may be performed, for example to create the well region 150 (e.g., Figure 13 shown, which is removed in subsequent figures).

[0050] Figure 14 The active device 102 is shown formed over the reformed single crystal active region 252, and the polycrystalline resistor 140 is formed over the oxide layer 146 (region 224) and / or the second dopant-containing polycrystalline region 244. As noted, the oxide layer 146 may be a TI 130 arrangement ( Figure 14 ), or the gate dielectric layer 118 ( Figure 2 ) part. The active device 102 and the polycrystalline resistor 140 may be implemented using any now known or later developed process, for example, performing polycrystalline material deposition and patterning and forming the spacers 120, 126. Although Figure 14 1 and 2. It is not shown, but it should be appreciated that the polycrystalline resistor 140 having the gate dielectric layer 118 or the well region 150 (respectively as Figure 2 and Figure 4 shown) can also be formed in this way.

[0051] Next is the middle-of-line (MOL) and back-end-of-line (BEOL) processing, which includes forming a silicide layer 158 ( Figure 1 、 Figure 5 and Figure 6 ) contacts 122, 152, 154, vias, and wiring for coupling to the interconnect structure of the active device 102 and / or the polysilicon resistor 140.

[0052] Embodiments of structure 100 eliminate the need to thin oxide layers, such as STI, beneath polysilicon resistors and improve the self-cooling characteristics of the resistors by improving heat dissipation to the substrate. The dopant-containing polycrystalline region beneath the active device reduces parasitic losses to the semiconductor substrate, ultimately providing thermal conductivity with reduced substrate coupling and improved frequency response.

[0053] The above-described structures and methods are used for integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in raw wafer form as bare chips (i.e., as a single wafer with multiple unpackaged chips) or in packaged form. In the latter case, the chip is mounted in a single-chip package (such as a plastic carrier whose leads are fixed to a motherboard or other higher-level carrier) or a multi-chip package (such as a ceramic carrier with one or both of surface interconnects and / or buried interconnects). In any case, the chip is then integrated with other chips, discrete circuit elements and / or other signal processing devices as part of (a) an intermediate product (such as a motherboard) or (b) a final product. The final product can be any product that includes an integrated circuit chip, from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices and central processing units.

[0054] The terms used herein are only used to describe the purpose of specific embodiments and are not intended to limit the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms "a", "an" and "said" are intended to also include the plural forms. It will also be understood that when used in this specification, the terms "include" and / or "comprising" specify the presence of stated features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or their, groups. "Optional" or "optionally" means that the event or situation described subsequently may or may not occur, and the description includes examples of events occurring and examples of events not occurring.

[0055] As used herein throughout the specification and claims, approximate language may be applied to modify any quantitative representation that may permissibly vary without resulting in a change in the basic function to which it relates. Accordingly, a value modified by a term or terms such as "about," "approximately," and "substantially" is not limited to the precise value specified. In at least some cases, approximate language may correspond to the precision of the instrument used to measure the value. Here and throughout the specification and claims, range limitations may be combined and / or interchanged, and unless context or language indicates otherwise, such ranges are identified and include all subranges contained therein. "Approximately" applied to a particular value of a range applies to both values ​​and may indicate + / - 10% of the stated value unless otherwise dependent upon the precision of the instrument used to measure the value.

[0056] The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing that function in combination with other claimed elements for which protection is specifically claimed. The description of the present disclosure has been presented for purposes of illustration and description, but is not intended to be exhaustive or to limit the disclosure to the forms disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the disclosure. The embodiments were chosen and described in order to best explain the principles and practical applications of the disclosure and to enable others of ordinary skill in the art to understand the disclosure of various embodiments with various modifications suitable for the intended specific use.

Claims

1. A resistor structure comprising: semiconductor substrates; a polycrystalline resistor region located on the semiconductor substrate, the polycrystalline resistor region comprising a semiconductor material in a polycrystalline form; as well as a dopant-containing polycrystalline region located between the polycrystalline resistor region and the semiconductor substrate, The dopant in the dopant-containing polycrystalline region includes an inert gas element.

2. The resistor structure according to claim 1, wherein The dopant-containing polycrystalline region contacts an underside of the polycrystalline resistor region.

3. The resistor structure according to claim 1 , further comprising: An oxide layer is located between the polycrystalline resistor region and the dopant-containing polycrystalline region.

4. The resistor structure according to claim 3, wherein The oxide layer is part of a trench isolation arrangement.

5. The resistor structure according to claim 3, wherein The oxide layer is part of the gate dielectric layer.

6. The resistor structure according to claim 1 , further comprising: A first contact and a second contact are located on the polycrystalline resistor region, the first contact and the second contact being spatially separated.

7. The resistor structure according to claim 6, further comprising: A silicide layer is located on the polycrystalline resistor region, the silicide layer extending from the first contact to the second contact.

8. The resistor structure according to claim 6, wherein The first contact to the second contact are located on a discontinuous silicide layer located on the polycrystalline resistor region.

9. The resistor structure according to claim 1, wherein The polycrystalline resistor region includes polycrystalline silicon, and the semiconductor substrate includes single crystal silicon.

10. The resistor structure according to claim 1, wherein The dopant includes argon (Ar).

11. The resistor structure of claim 1 , further comprising: an active device located above the semiconductor substrate, and wherein the active device comprises a single crystalline body and the dopant-containing polycrystalline region extends below the active device, The active device includes a polycrystalline gate located at the same layer as the polycrystalline resistor region.

12. The resistor structure according to claim 1, wherein The semiconductor substrate comprises a semiconductor-on-insulator (SOI) substrate comprising a semiconductor-on-insulator (SOI) layer over a buried insulator layer over a bulk semiconductor substrate, and The resistor structure further includes an active device located above the SOI substrate, and wherein the dopant-damaged polycrystalline region does not extend below the active device.

13. The resistor structure of claim 1 , further comprising: A well region is located in the semiconductor substrate below the dopant-containing polycrystalline region.

14. A resistor structure comprising: semiconductor substrates; a polycrystalline resistor region located on the semiconductor substrate, the polycrystalline resistor region comprising a semiconductor material in a polycrystalline form; an argon-containing polycrystalline region located between the polycrystalline resistor region and the semiconductor substrate; as well as An active device is located above the semiconductor substrate, wherein the active device includes a single crystalline body and the argon-containing polycrystalline region extends below the active device.

15. The resistor structure according to claim 14, wherein The argon-containing polycrystalline region contacts an underside of the polycrystalline resistor region.

16. The resistor structure of claim 14, further comprising: An oxide layer is located between the polycrystalline resistor region and the argon-containing polycrystalline region, and wherein the oxide layer is part of one of: a trench isolation arrangement and a gate dielectric layer.

17. The resistor structure of claim 14, further comprising: a first contact and a second contact located on the polycrystalline resistor region, the first contact and the second contact being spatially separated, and The resistor structure further includes a silicide layer on the polycrystalline resistor region, the silicide layer extending from the first contact to the second contact.

18. The resistor structure of claim 14, further comprising: A well region is located in the semiconductor substrate below the argon-containing polycrystalline region.

19. A method of forming a resistor structure, comprising: Injecting an inert gas element into a first single crystal region in a semiconductor substrate to form a first polycrystalline region containing a dopant, and one of: injecting an inert gas element into an oxide layer in the semiconductor substrate to form a polycrystalline region containing a dopant below the oxide layer, and injecting an inert gas element into a second single crystal region in the semiconductor substrate to form a second polycrystalline region containing a dopant; performing annealing to reform an upper portion of the first dopant-containing polycrystalline region into a reformed single-crystalline active region, leaving a portion of the first dopant-containing polycrystalline region below the reformed single-crystalline active region as an isolation layer; as well as forming an active device over the reformed single crystalline active region and forming a polycrystalline resistor over one of the oxide layer and the second dopant-containing polycrystalline region, and wherein the oxide layer is part of one of a trench isolation arrangement and a gate dielectric layer.

20. The method according to claim 19, further comprising: Prior to forming the active device, the nitride cap is removed from over the second dopant-containing polycrystalline region.

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