A circuit structure and method for prohibiting charging of a single battery at 0V

Abstract

The present invention discloses a circuit structure and method for prohibiting charging of a single battery at 0V. The circuit structure is aimed at the current battery protection circuit. When the battery is detected to be in a low voltage state, the substrate voltage of the MOS switch tube M0 is used to drive the detection circuit to work, and judge whether the voltage at the battery end is lower than the set threshold voltage. If it is lower than the threshold voltage given by the detection circuit, the detection circuit gives a corresponding signal to prohibit the charger from charging the single battery. The circuit structure can prevent the charger from continuing to charge the battery when the battery is damaged, thereby protecting the battery.

Description

Technical Field

[0001] The invention belongs to the technical field of single-cell battery protection, and in particular relates to a circuit structure and method for prohibiting charging of a single-cell battery at 0V. Background Art

[0002] With the increasing application of batteries, their protection becomes more and more important. Among them, undervoltage and overvoltage protection of batteries during charging and prohibiting charging are very important. When monitoring and protecting the battery, if the battery is found to be damaged (the battery voltage is too low, such as lower than 1.2V), it does not need to be charged. At this time, a battery 0V prohibiting charging circuit is needed to detect whether the battery voltage at this time is lower than the set threshold. If it is lower than the threshold, the charging path is cut off.

[0003] During battery protection, when the battery voltage is very low, a detection circuit is needed to prohibit the charger from charging the battery. When the battery voltage is very low, the battery cannot provide power to the circuit to make it work. At this time, it is very important to take measures to detect the battery voltage and cut off the charging path of the charger. Summary of the invention

[0004] The purpose of the present invention is to overcome the shortcomings of the above-mentioned prior art and provide a circuit structure and method for prohibiting charging of a single battery at 0V, so as to solve the problem that the charger continues to charge the battery when the battery is damaged (the battery voltage is lower than 1.2V), and how to make the monitoring circuit continue to work when the battery voltage is too low to provide the power required for the chip to work.

[0005] In order to achieve the above object, the present invention adopts the following technical solutions:

[0006] A circuit structure for prohibiting charging of a single battery at 0V, comprising a monitoring unit, a logic unit, a driving unit, a battery and a charger;

[0007] The battery and the charger are connected in parallel, and the grounds of the monitoring unit, the logic unit and the driving unit are all connected to the negative electrode of the battery; the input terminal of the monitoring unit is connected to the positive electrode of the battery;

[0008] A switch MOS tube is provided between the positive electrode of the battery and the positive electrode of the charger, the switch MOS tube is connected in parallel with a switch K1 and a switch K2, and the switch K1 and the switch K2 are connected in series; the connection point of the switch K1 and the switch K2 is connected to the substrate of the switch MOS tube, and the switch MOS tube is connected to the driving unit electrical signal; the logic unit electrical signal is connected to the switch K1 and the switch K2;

[0009] The monitoring unit is connected to the logic unit by electrical signals, and the logic unit is connected to the driving unit by electrical signals.

[0010] A further improvement of the present invention is:

[0011] Preferably, the monitoring unit is powered by a charger.

[0012] Preferably, the power supplies of the logic unit and the driving circuit are both from the highest power supply.

[0013] Preferably, the monitoring circuit includes a monitoring unit MOS tube, a resistor and an inverter.

[0014] Preferably, the MOS tubes include M1, M2, M3, M4, M5, M6, M7, M8 and M9, the resistors include R1, R2 and R3, and the inverters include INV1, INV2 and INV3;

[0015] The two ends of the resistor R1 are connected to VBAT and VIN respectively, the other end of VIN is connected to the resistor R2, and the other end of the resistor R2 is connected to GND; the gate end of the MOS tube M1 is connected to VBAT, the source end is connected to VOUT, the drain end is connected to the resistor R3, and the substrate is connected to VOUT; the other end of the resistor R3 is connected to the drain end of the MOS tube M2, the gate end of the MOS tube M3, and the gate ends of the MOS tubes M4, MOS tubes M5, MOS tubes M6, and MOS tubes M7, the gate end of the MOS tube M2 is connected to VIN, the source end and the substrate are grounded; the source end, drain end and substrate of the MOS tube M3 are grounded; the source end and substrate of the MOS tube M4 are connected to VOUT, and the drain end is connected to the MOS tube M The substrate of the MOS tube M5 is connected to VOUT, and the drain is connected to the drain of the MOS tube M6 and the input of the inverter INV1; the substrate of the MOS tube M6 is grounded, and the source terminal is connected to the drain of the MOS tube M7 and the drain of the MOS tube M9; the substrate and source terminal of the MOS tube M7 are grounded; the substrate and source terminal of the MOS tube M8 are connected to VOUT, and the gate terminal is connected to the output of the inverter INV1, the input of the inverter INV2 and the gate terminal of the MOS tube M9; the source terminal and substrate of the MOS tube M9 are grounded, the output of the inverter INV2 is connected to the input of the inverter INV3, and the output of the inverter INV3 is connected to OUT.

[0016] Preferably, the MOS tube M1, MOS tube M4, MOS tube M5 and MOS tube M8 are PMOS tubes.

[0017] Preferably, the MOS tube M2, MOS tube M3, MOS tube M6, MOS tube M7 and MOS tube M9 are NMOS tubes.

[0018] Preferably, the single-cell battery 0V means that the voltage of the single-cell battery is lower than 1.2V.

[0019] A working method of the circuit structure of prohibiting charging of a single battery at 0V as described above, comprising the following steps: a monitoring unit monitors the voltage of the battery and outputs a signal to a logic unit; the logic unit outputs a signal to a switch K1 and a switch K2 to control the opening and closing of the switch K1 and the opening and closing of the switch K2; the logic unit outputs a signal to a driving unit; the driving unit outputs a signal to a switch MOS tube to control its on and off state;

[0020] When the battery voltage is lower than the set threshold, the switch MOS tube is turned off, switch K2 is closed, switch K1 is opened, and the charger no longer charges the battery.

[0021] Preferably, when the charger stops charging the battery, the monitoring unit, the logic unit and the driving unit continue to operate.

[0022] Compared with the prior art, the present invention has the following beneficial effects:

[0023] The present invention discloses a circuit structure for prohibiting charging of a single battery at 0V. The circuit structure is aimed at the current battery protection circuit. When the battery is detected to be in a low voltage state, the substrate voltage of the MOS switch tube M0 is used to drive the detection circuit to work, and judge whether the voltage at the battery end is lower than the set threshold voltage. If it is lower than the threshold voltage given by the detection circuit, the detection circuit gives a corresponding signal to prohibit the charger from charging the single battery. The circuit structure can prevent the charger from continuing to charge the battery when the battery is damaged, thereby protecting the battery.

[0024] Furthermore, the monitoring unit, the logic unit and the driving unit are provided with respective power supplies, so that when the battery voltage is too low to provide the power required for the chip to work, the monitoring circuit can continue to work.

[0025] The present invention also discloses a working method of a circuit structure for prohibiting charging of a single-cell battery at 0V. The working method realizes protection of the single-cell battery by setting a monitoring and driving unit, monitoring the voltage of the battery, and driving the opening and closing of a switch. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 This is the overall block diagram of the battery 0V charging prohibited of the present invention;

[0027] Figure 2 is a practical circuit implementation diagram of the monitoring unit of the present invention;

[0028] Figure 3 is a practical circuit implementation diagram of the logic unit of the present invention;

[0029] Figure 4 FIG. 4 is a diagram showing a practical circuit implementation of the driving unit of the present invention.

[0030] Specifically: 1-monitoring unit; 2-logic unit; 3-drive unit; 4-charger; 5-battery. DETAILED DESCRIPTION

[0031] The present invention is further described in detail below in conjunction with the accompanying drawings:

[0032] In the description of the present invention, it should be noted that the orientations or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inside", "outside", etc. are based on the orientations or positional relationships shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention; the terms "first", "second", and "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance; in addition, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection or a detachable connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the internal communication of two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0033] See also Figure 1 In one embodiment provided by the present invention, a circuit structure for prohibiting charging of a single battery at 0V is disclosed, and the circuit structure includes a circuit frame structure including a monitoring unit 1, a logic unit 2, a driving unit 3, a switch MOS tube M0, two switches (K1 and K2), a charger 4 and a battery 5. 0V in the present invention refers to the situation where the voltage of a single battery is lower than 1.2V, that is, the voltage of a single battery lower than 1.2V is called 0V.

[0034] Specifically, the circuit framework structure includes a monitoring unit, a logic unit, a driving unit, a switch MOS tube, a charger and a battery. A switch MOS tube is arranged between the positive poles of the battery and the charger, and the switch MOS tube is connected in parallel with a switch K1 and a switch K2. The switch K1 and the switch K2 are connected in series, and the connection point of the switch K1 and the switch K2 is connected to the substrate of the switch MOS tube. One end of the switch K1 is connected to the positive pole of the battery 5, and the other end of the switch K2 is connected to one end of the charger 4. The ground ends of the three units of the monitoring unit, the logic unit and the driving unit are connected to the negative pole of the battery and the negative pole of the charger, and the connection ends are grounded at the same time. One end of the monitoring unit is connected to the positive pole of the battery at the same time. The signal input end of the monitoring unit is electrically connected to the positive pole of the battery for detecting the positive pole voltage of the battery, the signal output end of the monitoring unit is connected to the signal input end of the logic unit, the signal output end of the logic unit is connected to the signal input end of the driving unit, and the signal output end of the driving unit is connected to the gate end of the switch MOS tube. The logic unit is connected to the switch K1 and the switch K2 at the same time, and is used to control the opening and closing of the switch K1 and the switch K2. The power supply of the monitoring unit comes from the charger end, and the power supply of the logic unit and the driving circuit comes from the substrate end of M1. The power supply of the substrate end comes from the highest power supply in the circuit.

[0035] In one embodiment provided by the present invention, a working method of the above structure is provided. Specifically, the monitoring unit monitors the voltage at the battery terminal, and then outputs a corresponding signal to the logic judgment circuit. The logic judgment circuit outputs a corresponding signal to the switch K1 and the switch K2 and the driving unit. The driving unit outputs a corresponding signal to the switch MOS tube M0 to control its on and off state. The monitoring unit is used to determine whether the battery voltage is lower than a set threshold value. Then the logic unit drives the circuit according to the signal from the monitoring terminal. If it is lower than the set threshold value, M0 will be turned off. That is, when it is determined that the voltage at the battery terminal is too low, the logic unit will also control the switching actions of the switches K1 and K2, close the switch K2, and open the switch K1 so that the charger cannot charge the battery.

[0036] In the present invention, when the monitoring unit detects that the battery voltage is lower than 1.2V, the switch MOS tube M0 is turned off, K1 is opened and K2 is closed, thereby blocking the charger from charging the battery, thereby achieving the purpose of prohibiting charging at 0V.

[0037] The monitoring unit determines the state of the battery voltage, whether it is normal, undervoltage, overvoltage or too low voltage; more specifically, the battery voltage is compared with the set threshold voltage through the corresponding circuit. When it is found that the battery voltage is too low, a corresponding signal will be generated to the logic control unit. The logic unit makes the next operation judgment based on the signal of the monitoring unit and outputs the corresponding operation instruction to the switches K1, K2 and the driving unit.

[0038] The logic control unit makes the next action according to the signal given by the monitoring unit to judge the switch status of K1 and K2 and control the next action of the driving unit on the switch MOS tube M0;

[0039] The driving unit determines the next operation of the switch MOS tube M0 according to the signal given by the logic unit, whether to turn on the switch MOS tube M0 to allow the charger to charge or to turn off the switch MOS tube M0 to prohibit charging;

[0040] The switch MOS tube unit allows the charger to charge the battery or prohibits charging according to when it is turned on or off; specifically, when charging, the MOS tube M0 is turned on, the switch K1 is closed, and the switch K2 is opened; when charging is prohibited, the MOS tube M0 is turned off, the switch K1 is opened, and the switch K2 is closed.

[0041] The circuits in the logic unit and the driving unit in the present invention are both existing conventional circuit structures, and they only need to achieve their respective functions.

[0042] In another embodiment of the present invention, a specific monitoring unit circuit is provided, see Figure 2 , M1, M4, M5, and M8 are PMOS tubes, M2, M3, M6, M7, and M9 are NMOS tubes, R1, R2, and R3 are resistors, and INV1, INV2, and INV3 are inverters.

[0043] Specifically, Figure 2It is one of the circuit embodiments of a specific monitoring unit (monitoring unit, detection), MOS tubes M1, MOS tube M4, MOS tube M5, MOS tube M8 are PMOS tubes, MOS tubes M2, MOS tube M3, MOS tube M6, MOS tube M7, MOS tube M9 are NMOS tubes, resistors R1, resistor R2, resistor R3 are resistors, INV1, INV2, INV3 are inverters, and the connection relationship is: the two ends of the resistor R1 are connected to VBAT and VIN respectively, the other end of VIN is connected to the resistor R2, the other end of the resistor R2 is connected to GND, the gate terminal of the MOS tube M1 is connected to VBAT, the source terminal is connected to VOUT, the drain terminal is connected to the resistor R3, and the substrate is connected to VOUT, the other end of the resistor R3 is connected to the drain end of the MOS tube M2, the gate end of the MOS tube M3, and the MOS tubes M4, MOS tubes M5, M The gate terminals of MOS tubes M6 and M7, the gate terminal of MOS tube M2 are connected to VIN, the source terminal and substrate are grounded, the source terminal, drain terminal and substrate of MOS tube M3 are grounded, the source terminal and substrate of MOS tube M4 are connected to VOUT, the drain terminal is connected to the source terminal of MOS tube M5 and the drain terminal of MOS tube M8, the substrate of MOS tube M5 is connected to VOUT, the drain is connected to the drain of MOS tube M6 and the input of inverter INV1, the substrate of MOS tube M6 is grounded, the source terminal is connected to the drain terminal of MOS tube M7 and the drain terminal of MOS tube M9, the substrate and source terminal of MOS tube M7 are grounded, the substrate and source terminal of MOS tube M8 are connected to VOUT, the gate terminal is connected to the output of inverter INV1, the input of inverter INV2 and the gate terminal of MOS tube M9, the source terminal and substrate of MOS tube M9 are grounded, the output of inverter INV2 is connected to the input of inverter INV3, and the output of inverter INV3 is connected to OUT.

[0044] Figure 2 The circuit VIN is related to VBAT, and VIN is derived from the voltage division of VBAT. , then the VBAT voltage is low and the VIN is low. When the battery voltage is too low, the MOS tube M1 is turned on and the MOS tube M2 is turned off. At this time, a logic high level is generated at the drain end of the MOS tube M2. The following MOS tubes M4, M5, M6, M7, M8, M9, INV1 and INV2 form a Schmitt trigger. The waveform generated at the drain end of the integer MOS tube M2 is output to the OUT end through the inverter INV3. The OUT end will control K1 and K2 in the circuit block diagram. Figure 1The logic unit (logic) in the circuit opens K1 and closes K2. When the battery voltage returns to normal (VBAT voltage becomes high), MOS tube M1 is turned off and MOS tube M2 is turned on. At this time, a logic low level is generated at the drain end of MOS tube M2. After being shaped by the Schmitt trigger, it is also output to the OUT end through the inverter INV3. This is opposite to the logic when the battery voltage is too low. At this time, the OUT end will control K1 and K2 in the circuit block diagram to perform opposite switching operations. Figure 1 The logic unit (logic) in closes K1 and opens K2.

[0045] In another embodiment of the present invention, a specific logic unit circuit is provided, see Figure 3 , INV4 and INV5 are inverters, NAND1 and NAND2 are two-input NAND gates, and Buffer1 and Buffer2 are buffer circuits.

[0046] Specifically, Figure 3 Describes Figure 1 The logical units in the connection relationship are: Figure 2 The output end OUT of the monitoring unit is connected to the input end of the inverter INV4, the output of the inverter INV4 is connected to one input of the two-input NAND gate NAND1 and the input of the inverter INV5, the other input of the two-input NAND gate NAND1 is connected to the output of Buffer2, the output of the inverter INV5 is connected to one input of the two-input NAND gate NAND2, the other input of the two-input NAND gate NAND2 is connected to the output of Buffer1, the input of Buffer1 is connected to the output of the two-input NAND gate NAND1, and the input of Buffer2 is connected to the output of NAND2.

[0047] Figure 3 Buffer1 connection in Figure 1 K1, Buffer2 connection Figure 1 K2, when the battery voltage is too low, Figure 2 From the description, we can see that Figure 2 The OUT terminal of the battery outputs a high level, then Buffer1 outputs a high level, K1 is a PMOS tube, and it will be turned off (that is, the opening described above), and Buffer2 outputs a low level, K2 is a PMOS tube, and it will be turned on (that is, the closing described above). When the battery voltage recovers, the above Figure 2 From the description, we can see that Figure 2 The OUT end of Buffer1 outputs a low level, and K1 is a PMOS tube, which will be turned on (that is, the closure described above). Buffer2 outputs a high level, and K2 is a PMOS tube, which will be turned off (that is, the opening described above).

[0048] In another embodiment of the present invention, a specific driving unit circuit is provided, see Figure 4 , M10, M11, M12, and M13 are MOS tubes.

[0049] Specifically, Figure 4 Describes Figure 1 In the middle drive unit, M10 and M12 are PMOS tubes, M11 and M13 are NMOS tubes, and the connection relationship is: Figure 2 The output terminal OUT of the monitoring unit is connected to the gate terminals of the MOS tubes M10 and M11, the source terminal of the MOS tube M10 is connected to the substrate, the source terminal of the MOS tube M12 is connected to the substrate and connected to V sub (Right now Figure 1 Medium V sub ), the drain end of MOS tube M10, the drain end of MOS tube M11, the gate end of MOS tube M12, and the gate end of MOS tube M13 are connected, the source end of MOS tube M11 and the substrate, the source end of MOS tube M13 and the substrate are connected and connected to GND (i.e. Figure 1 The drain end of MOS tube M12 is connected to the drain end of MOS tube M13 to output signal control Figure 1 Middle MOS tube M0.

[0050] Figure 4 The circuit constitutes a Buffer circuit. Figure 1 The output terminal OUT is connected to the gate terminal of MOS tube M10 and MOS tube M11 as the input Figure 4 The input of the circuit, when the battery voltage is too low, Figure 2 From the description, we can see that Figure 2 The OUT terminal outputs a high level, then Figure 4 The circuit outputs a high level at the drain end of MOS tube M12 and the drain end of MOS tube M13 to shut down. Figure 1 The middle MOS tube M0 (PMOS) is powered by the above Figure 2 From the description, we can see that Figure 2 The OUT terminal outputs a low level, then Figure 4 The circuit outputs a low level at the drain end of MOS tube M12 and the drain end of MOS tube M13 to turn on Figure 1 Middle MOS tube M0 (PMOS).

[0051] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A circuit structure for prohibiting charging of a single battery at 0V, characterized in that: It comprises a monitoring unit (1), a logic unit (2), a driving unit (3), a battery (5) and a charger (4); The battery (5) and the charger (4) are connected in parallel, and the grounds of the monitoring unit (1), the logic unit (2) and the driving unit (3) are all connected to the negative electrode of the battery (5); the input end of the monitoring unit (1) is connected to the positive electrode of the battery (5); A switch MOS tube is provided between the positive electrode of the battery (5) and the positive electrode of the charger (4), the switch MOS tube being connected in parallel with a switch K1 and a switch K2, and the switch K1 and the switch K2 being connected in series; the connection point between the switch K1 and the switch K2 is connected to the substrate of the switch MOS tube, and the switch MOS tube is electrically signal connected to the drive unit (3); the logic unit (2) is electrically signal connected to the switch K1 and the switch K2; The monitoring unit (1) and the logic unit (2) are connected via electrical signals, and the logic unit (2) and the driving unit (3) are connected via electrical signals.

2. A circuit structure for prohibiting charging of a single battery at 0V according to claim 1, characterized in that: The monitoring unit (1) is powered by a charger (4).

3. A circuit structure for prohibiting charging of a single battery at 0V according to claim 1, characterized in that: The power supplies of the logic unit (2) and the drive unit (3) are both from the highest power supply.

4. A circuit structure for prohibiting charging of a single battery at 0V according to claim 1, characterized in that: The monitoring unit (1) comprises a monitoring unit MOS tube, a resistor and an inverter.

5. A circuit structure for prohibiting charging of a single battery at 0V according to claim 4, characterized in that: The monitoring unit MOS tubes include M1, M2, M3, M4, M5, M6, M7, M8 and M9, the resistors include R1, R2 and R3, and the inverters include INV1, INV2 and INV3; The two ends of the resistor R1 are connected to VBAT and VIN respectively, the other end of VIN is connected to the resistor R2, and the other end of the resistor R2 is connected to GND; the gate end of the MOS tube M1 is connected to VBAT, the source end is connected to VOUT, the drain end is connected to the resistor R3, and the substrate is connected to VOUT; the other end of the resistor R3 is connected to the drain end of the MOS tube M2, the gate end of the MOS tube M3, and the gate ends of the MOS tubes M4, MOS tubes M5, MOS tubes M6, and MOS tubes M7, the gate end of the MOS tube M2 is connected to VIN, the source end and the substrate are grounded; the source end, the drain end and the substrate of the MOS tube M3 are grounded; the source end and the substrate of the MOS tube M4 are connected to VOUT, and the drain end is connected to the MOS tube M The substrate of the MOS tube M5 is connected to VOUT, and the drain is connected to the drain of the MOS tube M6 and the input of the inverter INV1; the substrate of the MOS tube M6 is grounded, and the source terminal is connected to the drain of the MOS tube M7 and the drain of the MOS tube M9; the substrate and source terminal of the MOS tube M7 are grounded; the substrate and source terminal of the MOS tube M8 are connected to VOUT, and the gate terminal is connected to the output of the inverter INV1, the input of the inverter INV2 and the gate terminal of the MOS tube M9; the source terminal and substrate of the MOS tube M9 are grounded, the output of the inverter INV2 is connected to the input of the inverter INV3, and the output of the inverter INV3 is connected to OUT.

6. A circuit structure for prohibiting charging of a single battery at 0V according to claim 5, characterized in that: The MOS tube M1 , MOS tube M4 , MOS tube M5 and MOS tube M8 are PMOS tubes.

7. A circuit structure for prohibiting charging of a single battery at 0V according to claim 5, characterized in that: The MOS transistor M2 , MOS transistor M3 , MOS transistor M6 , MOS transistor M7 and MOS transistor M9 are NMOS transistors.

8. A circuit structure for prohibiting charging of a single battery at 0V according to any one of claims 1 to 7, characterized in that: The single-cell battery 0V means that the voltage of the single-cell battery is lower than 1.2V.

9. A method for operating the circuit structure of prohibiting charging of a single battery at 0V according to claim 1, characterized in that: The following steps are involved: The monitoring unit (1) monitors the voltage of the battery (5) and outputs a signal to the logic unit (2); the logic unit (2) outputs a signal to the switch K1 and the switch K2 to control the opening and closing of the switch K1 and the opening and closing of the switch K2; the logic unit (2) outputs a signal to the drive unit (3); the drive unit (3) outputs a signal to the switch MOS tube to control its on and off state; When the voltage of the battery (5) is lower than the set threshold, the switch MOS tube is turned off, the switch K2 is closed, the switch K1 is opened, and the charger (4) no longer charges the battery (5).

10. The working method according to claim 9, characterized in that: When the charger (4) stops charging the battery (5), the monitoring unit (1), the logic unit (2) and the driving unit (3) continue to work.

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