External object detection sensing circuit for wireless power transmission systems

Abstract

This disclosure relates to a sensing circuit for detecting external objects in a wireless power transmission system. A wireless power circuit is operable in transceiver mode and Q-factor measurement mode, and includes a bridge circuit coupled to a coil and having an output coupled to a rectified voltage node. In Q-factor measurement mode, an excitation circuit drives the coil with a pulse signal. A protection circuit couples the coil to a first node in Q-factor measurement mode and decouples the coil from the first node in transceiver mode. The Q-factor sensing circuit includes an amplifier having inputs coupled to the first node and a common-mode voltage (Vcm), and the amplifier generates an output signal with an output voltage. A comparator generates a comparison output indicating the voltage at a first terminal of the coil, a processing circuit generates an enable signal based on the comparison output, and an analog-to-digital converter, when enabled, digitizes the output voltage for calculating the Q-factor of the coil.

Description

Technical Field

[0001] This invention relates to the field of wireless power transmission, and more particularly to an external object detection sensing circuit for a wireless power transmission system. Background Technology

[0002] Portable electronic devices (such as smartphones, smartwatches, audio output devices (earphones, headphones), and wearable devices) operate using battery power, rather than wired power and power distribution systems transmitted to them via wired transmission lines. Batteries used in such devices are typically rechargeable, thus requiring a method for charging them.

[0003] Most portable electronic devices include a charging port, typically compliant with Micro USB or USB-C standards, into which a power cord can be plugged to charge its battery. However, such charging ports may make it difficult to improve the water resistance of electronic devices and are easily damaged by repeated use. Furthermore, some smaller portable electronic devices (such as earbuds and smartwatches) may lack the available space to provide a charging port. Additionally, some users may find it inconvenient to plug a power cord into the charging port of an electronic device to charge its battery.

[0004] Therefore, to address these issues, wireless power transmission has been developed. As shown, the wireless power transmission system 10 may include a first device 11 and a second device 15. The first device 11 may be a device capable of wireless power transmission (TX) (e.g., a smartphone) and / or a device capable of wireless power reception (RX) (e.g., a device for wireless charging, such as a charging case for a pair of wireless earbuds or an active stylus), and the second device 15 may be a device capable of both wireless power transmission and wireless power reception, such as a smartphone.

[0005] The first device 11 includes a coil Ls (considered secondary when receiving power; capacitor Cs represents the tuning capacitor of the coil Ls) and hardware 12, in which a time-varying current is induced by a time-varying electric field when receiving power. The hardware 12 rectifies, regulates and utilizes the time-varying current induced in the coil Ls to power the device 11, for example, to charge its battery.

[0006] The second device 15 includes a controlled switching bridge circuit (operable as a bridge rectifier or a DC-AC inverter) 16 coupled to the transceiver coil Lxcvr at nodes Ac1 and Ac2, wherein a discrete capacitor Cxcvr is used to tune the second device 15. The controlled switching bridge circuit 16 includes transistors T1-T4 controlled by gate voltages G1-G4.

[0007] A tank capacitor Ctank is coupled between node Nin and node N. Voltage regulator 17 has an input coupled to node Nin and an output coupled to node Nout. Battery 18 is selectively coupled between node Nout and node N via switch SW1, and selectively coupled between node N and node Nin via switch SW2. Switches SW1 and SW2 operate out of phase with each other; when the second device 15 operates as a receiver in power receiving mode, switch SW1 is closed and switch SW2 is open, wherein in power receiving mode, circuit 16 acts as an AC-DC rectifier and the regulator is used to generate a regulated voltage Vreg to charge the battery of the second device 15, and when the second device 15 operates as a transmitter in power transmitting mode, switch SW1 is open and switch SW2 is closed, wherein in power transmitting mode, circuit 16 acts as a DC-AC inverter powered by battery 18 to transmit power supplied by battery 18 to the first device 11. Controller 19 generates gate voltages G1-G4 to control bridge 16 to operate in the desired rectifier / inverter mode.

[0008] When the second device 15 operates as a receiver, the controlled switching bridge circuit 16 rectifies the AC current flowing in the transceiver coil Lxcvr to generate a DC current that charges the tank capacitor Ctank connected to node Nin, and a rectified voltage Vrect is formed across the tank capacitor Ctank. The voltage regulator 17 generates a regulated output voltage Vreg from this rectified voltage Vrect at its output node Nout, which is supplied to the battery 18 to charge it.

[0009] When the second device 15 operates as a transmitter, the voltage of the battery 18 is applied to node Nin via switch SW2 and becomes voltage Vrect. Then, the gate voltages G1-G4 are driven by controller 19 to generate a time-varying current flowing through the transceiver coil Lxcvr.

[0010] During wireless power transmission, a conductive external object 20 may inadvertently be physically present between the first device 11 and the second device 15 (such as...). Figure 2As shown, this could pose a danger. This is a problem because the transmitting device might induce eddy currents in a conductive external object, which would dissipate as heat and potentially damage the device. Therefore, a method is desired to detect the presence of a conductive external object, thereby halting wireless power transmission or mitigating the transmitted electrical force. In the context of a wireless power transmission system, the external object is a conductive material placed in the field, such as a coin, key, or paperclip, and is not part of the wireless charging system and is not protected by shielding in the transmitting or receiving devices. The alternating magnetic field between the transmitter and receiver can induce eddy currents in these conductive materials exposed to the magnetic field, causing them to heat up. Therefore, for efficient power delivery and operational safety, it is necessary to detect these objects and remove them from the wireless power transmission system.

[0011] The quality factor (Q factor) of the second device 15, an indication of the efficiency of the power transmitted to or from the second device 15, can be measured by simultaneously measuring the peak voltage generated at node AC1 and then measuring the next damped peak voltage generated at the same node AC1, after excitation with a time-varying electric field generated by transceiver 15. To accommodate this, a Q factor sensing block 9 is coupled to coil Lxcvr. The Q factor measurement period can be interleaved with the power transmission / reception period, but they will not occur simultaneously.

[0012] Since the mutual inductance between coils Ls and Lxcvr will vary depending on the conditions of system 10, the Q factor of Lxcvr will also vary depending on the conditions of system 10. Therefore, from the Q factor of Lxcvr, the second device 15 can infer the conditions of system 10. When the second device 15 is used as a transmitter, the possible relevant conditions of system 10 include: (i) both the first device 11 and the second device 15 are close to each other but not to the external object 20; (ii) the second device 15 is close to the external object 20 but not close to the first device 11; (iii) the second device 15 is neither close to the first device 11 nor close to the external object 20; and (iv) both the first device 11 and the second device 15 are close to each other and close to the external object 20.

[0013] By modeling the wireless power transmission system 10 as a transformer, the Q-factor curves for these different system cases can be derived. For example, see also... Figure 3In case (i), the resonant amplitude of coil Lxcvr will be higher than in other cases, and the resonant frequency of system 10 will be lower than in other cases, as shown by the Q factor curve labeled Fr_tx+rx. Similarly, in case (ii), the resonant amplitude of coil Lxcvr is lower than in other cases, and the resonant frequency of system 10 is higher than in other cases, as shown by the Q factor curve labeled Fr_tx+fo. For case (iii), the resonant amplitude of coil Lxcvr is less than that in case (i) but greater than that in case (iii), and the resonant frequency of coil Lxcvr is greater than that in case (i) but less than that in case (iii), as shown by the Q factor curve labeled Fr_tx. Case (iv) produces a resonant frequency similar to that in case (iii), but with a slightly smaller resonant amplitude, as shown by the Q factor curve labeled Fr_tx+rx+fo. Therefore, by measuring the Q factor of coil Lxcvr, the second device 15 can determine the current state of system 10 and can take appropriate actions (e.g., transmit at full power, transmit at lower power, stop transmitting, etc.).

[0014] Existing Q-factor measurement techniques have been shown to be inaccurate enough to correctly distinguish between cases (ii) and (iii), and also between cases (i) and (iv), because an external object exists in case (ii) but not in case (iii), and because an external object exists in case (iv) but not in case (i). Therefore, further development is needed. Summary of the Invention

[0015] This document discloses a wireless power circuit capable of operating in transceiver mode and Q-factor measurement mode. The wireless power circuit includes a coil, a bridge rectifier, a drive circuit, and a protection circuit. The coil has a first terminal and a second terminal. The bridge rectifier has a first input and a second input coupled to the first and second terminals of the coil, respectively, and an output coupled to a rectified voltage node. The drive circuit is coupled to the first terminal of the coil and configured to drive the coil using a pulse signal when in Q-factor measurement mode. The protection circuit couples the first terminal of the coil to a first node when in Q-factor measurement mode and decouples the first terminal of the coil from the first node when in transceiver mode. Furthermore, the wireless power circuit includes a Q-factor sensing circuit. The Q-factor sensing circuit has an amplifier, a comparator, a processing circuit, and an analog-to-digital converter. The amplifier has an input coupled to the first node and a common-mode voltage, and generates an output signal with an output voltage. The comparator has an input coupled to a second node and a common-mode voltage, and generates a comparison output indicating the VCM crossover of the voltage at the first terminal of the coil. The processing circuit is configured to receive the comparison output and generate an enable signal based on the comparison output. An analog-to-digital converter is configured to digitize the output voltage when enabled by an enable signal from the processing circuitry and to provide the digitized output voltage to the processing circuitry for calculating the Q factor of the coil.

[0016] The comparator can be configured to have a rising threshold equal to the common-mode voltage, a falling threshold equal to the common-mode voltage, and a hysteresis, such that when the voltage at the second node decreases, the effective rising threshold is equal to the rising threshold plus the hysteresis and the effective falling threshold is equal to the falling threshold, and when the voltage at the second node increases, the effective falling threshold is equal to the falling threshold minus the hysteresis and the effective rising threshold is equal to the rising threshold.

[0017] The processing circuit can calculate the Q factor of the coil based on the amplitude of a first sample of the output voltage obtained at a first peak of the output voltage and the amplitude of at least one other sample of the output voltage obtained at at least one other peak of the output voltage.

[0018] The processing circuit can calculate the Q factor as follows:

[0019]

[0020] Where A1 is the first sample of the output voltage obtained at the first peak of the output voltage, and AN is the Nth sample of the output voltage obtained at the Nth peak of the output voltage.

[0021] The processing circuit can calculate the Q factor of the coil based on the difference between the first sample of the output voltage obtained at the first peak of the output voltage and the second sample of the output voltage obtained at the first trough of the output voltage, and the difference between the third sample of the output voltage obtained at another peak of the output voltage and the fourth sample of the output voltage obtained at another trough of the output voltage.

[0022] The processing circuit can calculate the Q factor as follows:

[0023]

[0024] Where A1s is the first sample, A1b is the second sample, ANa is the third sample, and ANb is the fourth sample.

[0025] The excitation circuit may include a driver and a p-channel transistor. The driver is configured to receive a drive signal and generate an excitation signal based on the drive signal. The p-channel transistor has a source coupled to a supply voltage, a drain coupled to the anode of a diode via a resistor, and a gate coupled to receive the excitation signal. The diode has a cathode coupled to a first terminal of a coil.

[0026] The amplifier may have a non-inverting terminal coupled to a common-mode voltage, an inverting terminal coupled to a first node via a first capacitor, and an output coupled to the non-inverting terminal via a second capacitor, the output also being coupled to an analog-to-digital converter.

[0027] The comparator may have a non-inverting terminal coupled to a first node, an inverting terminal coupled to a common-mode voltage, and an output at which a comparator output is generated.

[0028] The first resistor can be coupled between the power supply voltage and the first node, and the second resistor can be coupled between the first node and ground.

[0029] The third resistor can be coupled between the power supply voltage and the second node, and the fourth resistor can be coupled between the second node and ground, generating a common-mode voltage at the second node.

[0030] The protection circuit may include a pair of series-coupled transistors coupled between the first node and the first terminal of the coil and having a gate coupled to a Q-factor sensing enable signal that is asserted when in Q-factor sensing mode and deasserted when not in Q-factor sensing mode.

[0031] In Q-factor measurement mode, the processing circuit can be configured to determine that a second wireless power circuit is close to a wireless power circuit but there is no external object between the two wireless power circuits by determining that the frequency of the output signal is less than the known frequency of the output signal minus a margin value in the absence of the second wireless power circuit and the external object. In response, the processing circuit can cause the wireless power circuit to wirelessly transmit power at full power level.

[0032] In Q-factor measurement mode, the processing circuit can be configured to determine that a second wireless power circuit is close to a wireless power circuit but an external object exists between the two wireless power circuits by: determining that the frequency of the output signal is greater than the known frequency of the output signal plus a margin value in the absence of the second wireless power circuit and the external object; determining that the frequency of the output signal is less than the known frequency of the output signal minus the margin value in the absence of the second wireless power circuit and the external object; determining whether the Q-factor is less than the Q-factor margin value; determining whether a first sample of the output voltage is less than the amplitude margin value; and determining whether another sample of the output voltage is less than the amplitude margin value. If the Q-factor is less than the Q-factor margin value, the first sample is less than the amplitude margin value, and the other sample is less than the amplitude margin value, the processing circuit causes the wireless power circuit not to wirelessly transmit power. If the Q-factor is not less than the Q-factor margin value, or if the first sample is not less than the amplitude margin value, or if the other sample is not less than the amplitude margin value, the processing circuit causes the wireless power circuit to wirelessly transmit a limited amount of power, which is less than the power that the wireless power circuit would otherwise transmit.

[0033] In Q-factor measurement mode, the processing circuit can be configured to determine that the second wireless power circuit is not close to the wireless power circuit and that an external object is close to the wireless power circuit by determining that the frequency of the output signal is greater than the known frequency of the output signal plus a margin value in the absence of the second wireless power circuit and the external object. In response, the processing circuit can cause the wireless power circuit to cease wireless power transmission.

[0034] In Q-factor measurement mode, the processing circuit can be configured to determine that the second wireless power circuit is not close to the wireless power circuit and that no external object is close to the wireless power circuit by determining that the frequency of the output signal is equal to the known frequency of the output signal in the absence of the second wireless power circuit and the external object. Attached Figure Description

[0035] Figure 1 This is a schematic block diagram of a wireless power transmission system based on existing technology;

[0036] Figure 2 yes Figure 1A schematic diagram of a wireless power transmission system, wherein an external object is located between the first device and the second device;

[0037] Figure 3 This is shown during Q-factor measurement mode at different positions of the second device relative to the first device and the external object. Figure 1 The amplitude versus frequency curve of the signal at node Nf;

[0038] Figure 4 This is a schematic block diagram of a wireless power transmitting device as described in this article, such as one that can be used as... Figure 1 The second device of the wireless power transmission system;

[0039] Figure 5 It is shown Figure 4 A graph showing the performance of a comparator in response to the voltage VLC input to the comparator;

[0040] Figure 6 This shows the period during both the excitation and sensing phases of the Q-factor measurement mode. Figure 4 The graph shows the excitation signal, voltage VLC, output voltage, and comparison output.

[0041] Figure 7 This illustrates the sensing period during the Q-factor measurement mode when the Q-factor is determined according to the first technique. Figure 4 The graph shows the voltage VLC changing over time.

[0042] Figure 8 This illustrates the sensing period during the Q-factor measurement mode when the Q-factor is determined according to the second technique. Figure 4 The graph shows the voltage VLC changing over time.

[0043] Figure 9 This is a flowchart illustrating the use of data collected during Q-factor mode to determine the presence or absence of an external object and the actions taken by the wireless power transmitting device in response.

[0044] Figure 10A This is a schematic block diagram of a transceiver device capable of wirelessly receiving power from a transmitter device using the hysteresis comparator described herein.

[0045] Figure 10B This is a diagram of the hysteresis comparator used in the bridge circuit of the transceiver device shown in Figure 10 during operation.

[0046] Figure 10C yes Figure 10B A diagram showing the operating characteristics of a hysteresis comparator;

[0047] Figure 11 yes Figures 10A-10C A schematic block diagram of a hysteresis comparator;

[0048] Figure 12 This is a schematic block diagram of a hysteresis comparator with an automatic zero-reset stage, such as one that can be used with... Figure 4 Used together with wireless power transmitting equipment; and

[0049] Figures 13A-13C It has or does not have an automatic zeroing function. Figure 12 A diagram showing the operating characteristics of a hysteresis comparator. Detailed Implementation

[0050] The following disclosure enables those skilled in the art to make and use the subject matter disclosed herein. The general principles described herein can be applied to other embodiments and applications besides those detailed above without departing from the spirit and scope of this disclosure. This disclosure is not intended to be limited to the embodiments shown, but is accorded the widest scope consistent with the principles and features disclosed or suggested herein.

[0051] References in this article Figure 4 Describe transceiver device 15', transceiver device 15' such as can be with Figure 1 It is used in conjunction with the wireless power transmission system 10, and the transceiver device 15' incorporates the Q-factor sensor 30 and excitation circuit 21 described herein.

[0052] The transceiver device 15' includes a controlled switching bridge circuit (operable as a bridge rectifier or a DC-AC inverter) 16 coupled to the transceiver coil Lxcvr at nodes Ac1 and Ac2, wherein capacitor Cxcvr represents a tuning capacitor for alignment impedance matching, and capacitor Cpar represents a parasitic capacitance intentionally added between nodes Ac1 and Ac2 to adjust the impedance of the system.

[0053] The controlled switching bridge circuit 16 includes transistors T1-T4 controlled by gate voltages G1-G4. More specifically: the drain of transistor T1 is coupled to node Nin, the source is coupled to node Ac1, and the gate is coupled to gate voltage G1; the drain of transistor T3 is coupled to node Ac1, the source is coupled to node N (which can be ground or other reference voltage), and the gate is coupled to gate voltage G3. The drain of transistor T2 is coupled to node Nin, the source is coupled to node Ac2, and the gate is coupled to gate voltage G2; the drain of transistor T4 is coupled to node Ac2, the source is coupled to node N, and the gate is coupled to gate voltage G4.

[0054] A tank capacitor Ctank is coupled between node Nin and ground. Voltage regulator 17 has an input coupled to node Nin and an output coupled to node Nout. Battery 18 is selectively coupled between node Nout and ground via switch SW1, and selectively coupled between node Nin and node Nout via switch SW2. Switches SW1 and SW2 operate out of phase; when transceiver device 15' operates as a receiver in power receive mode, switch SW1 is closed and switch SW2 is open, in which transmitter circuit 16 acts as an AC-DC rectifier and regulator is used to generate a regulated voltage Vreg to charge battery 18; and when device 15' operates as a transmitter in power transmit mode, switch SW1 is open and switch SW2 is closed, in which circuit 16 acts as a DC-AC inverter powered by battery 18.

[0055] Controller 19' generates gate voltages G1-G4 to control bridge 16 to operate in the desired rectifier / inverter mode. Controller 19' includes a logic core 23 that generates control signals Gate_G1, Gate_G2, Gate_G3, and Gate_G4, and a Q-factor measurement enable signal Q_en, which is inverted to generate signal Q_En_B. A first AND gate 31 performs a logical AND operation on signals Gate_G1 and Q_En_B to generate gate voltage G1. A second AND gate 32 performs a logical AND operation on signals Gate_G2 and Q_En_B to generate gate voltage G2. An OR gate 33 performs a logical OR operation on signals Gate_G3 and Q_E to generate gate voltage G3. An OR gate 34 performs a logical OR operation on signals Gate_G4 and Q_En to generate gate voltage G4.

[0056] When transceiver device 15' operates as a receiver, controlled switch bridge circuit 16 rectifies the AC current to generate a DC current that charges tank capacitor Ctank connected to node Nin, and a rectified voltage Vrect is formed across tank capacitor Ctank. Voltage regulator 17 generates a regulated output voltage Vreg at its output node Nout, which is supplied to battery 18 to charge battery 18.

[0057] When transceiver device 15' operates as a transmitter, the voltage of battery 18 is applied to node Nin via switch SW2 and becomes voltage Vrect. Gate voltages G1-G4 are then driven by controller 19 to generate a time-varying current flowing through transceiver coil Lxcvr. Details of this control scheme can be found in U.S. Patent Application No. 16 / 669,068, filed October 30, 2019, the contents of which are incorporated herein by reference in their entirety.

[0058] The excitation circuit 21 is coupled to the transceiver coil Lxcvr at node Ac1. The excitation circuit 21 includes a p-channel transistor MP1, the source of which is coupled to the power supply voltage Vdd, the drain of which is coupled to the first terminal of the drain resistor Re, and the gate of which is coupled to the pad Qe to receive the signal Vin_exc driven by driver 22. The excitation circuit 21 also includes a diode D1, the anode of which is coupled to the second terminal of the resistor Re, and the cathode of which is coupled to the transceiver coil Lxcvr at node Ac1. Note that, compared to other components of the transceiver device 15', the excitation circuit 21 and the capacitor Cq described below are off-chip.

[0059] Q-factor sensing circuit 30 includes capacitor Cq coupled between the cathode of diode D and pad Qs. The drain of n-channel transistor MN1 is coupled to pad Qs, the source is coupled to the source of n-channel transistor MN2, and the gate is coupled to the Q-factor measurement enable signal Q_en. The source of transistor MN2 is coupled to the source of transistor MN1, its drain is coupled to tap node N1 between resistors R1 and R2 (which are coupled in series between Vdd and ground), and its gate is coupled to receive the Q-factor measurement enable signal Q_En. Amplifier 26 has an inverting input terminal coupled to node N1 via capacitor Cg, an inverting input terminal further coupled to the output of the amplifier via capacitor Cf, and an inverting terminal coupled to receive the common-mode voltage Vcm. In some cases, capacitors Cg and Cf can be adjustable, thereby allowing adjustment of the gain of amplifier 26. An output voltage Vout is generated at the output of amplifier 26. The output voltage Vout is applied to the input of analog-to-digital converter (ADC) 24, which converts the analog output voltage into the digital signal ADCout.

[0060] The Q-factor sensing circuit 30 also includes a comparator 27. The non-inverting input terminal of comparator 27 is coupled to node N1, and the inverting input terminal is coupled to a tap node N2 between resistors R3 and R4, which are connected in series between the power supply voltage Vdd and ground, acting as a voltage divider circuit to generate a common-mode voltage Vcm at node N2. Comparator 27 also has an output at which a comparison output signal Comp_Out is generated. A finite state machine (FSM) 25 has inputs that receive the comparison output signal Comp_Out and the digital signal ADCout, and outputs the control signal Ctrl and the Vin_exc signal to ADC 24. Note that since the capacitances Cg and Cf are adjustable, the gain of amplifier 26 can be programmed, thus allowing adjustment of the resolution of the samples generated by ADC 24.

[0061] Also note that comparator 27 has rising and falling thresholds dynamically set by hysteresis, depending on whether the voltage at its input is rising or falling. The comparator sets both the comparator rising threshold Vtr and the comparator falling threshold Vtl to Vcm, but maintains hysteresis so that the actual threshold voltages Vtr and Vtl are dynamic, as... Figure 5 The diagram shows the voltage (which will be VLC) at pad Qs. Therefore, when the voltage VLC decreases, the rising threshold Vtr is set to Vcm + hysteresis (2V + 0.05V = 2.05V in this example), and the falling threshold Vtl is set to Vcm (2V in this example); conversely, when the voltage VLC increases, the falling threshold Vtr is set to Vcm - hysteresis (2V - 0.05V = 1.95V in this example), and the rising threshold Vtl is set to Vcm (2V in this example). Therefore, comparator 27 allows for accurate zero-crossing (Vcm crossover) detection without compromising its ability to suppress noise using hysteresis during zero-crossing detection.

[0062] The second device 15' can operate in transceiver mode (Rx or Tx) or Q-factor measurement mode.

[0063] During transceiver mode, controller 19 generates control signals G1-G4 to cause circuit 16 to function as a receiver or inverter, as described above. Furthermore, during transceiver mode, the Q-factor measurement enable signal Q_en is de-asserted to turn off transistors MN1 and MN2, effectively isolating node Qs from Vcm, while diode D effectively blocks transceiver signals from circuit 21, and the switching action of circuit 16 causes the voltage VLC across coil Lxcvr to switch between positive and negative maximum amplitudes (e.g., -50V and 50V).

[0064] In Q-factor measurement mode, the Q-factor measurement enable signal Q_en is asserted by controller 19 to turn on transistors MN1 and MN2, thereby establishing a connection from the Qs pad to the center tap of series resistors R1 and R2. Furthermore, transistors T3 and T4 are simultaneously turned on by controller 19 to assert gate voltages G3 and G4, thereby shorting nodes Ac1 and Ac2 to ground.

[0065] Then, during the excitation period, driver 22 drives p-channel transistor MP1 via pad Qe with a pulse wave Vin_exc to generate an excitation signal. The duty cycle, frequency, and number of cycles of the pulse wave Vin_exc are set by the firmware of FSM 25. Figure 6The graph shows the Vin_exc value at pad Qe during the excitation period. When Vin_exc is low during the excitation period, the p-channel transistor MP1 is turned on, and the coil Lp draws power from VDD; conversely, when Vin_exc is high during the excitation period, the p-channel transistor MP1 is turned off.

[0066] In this way, coil Lp is excited at a frequency and duty cycle set by Vin_exc. The pulse width and frequency of the excitation signal set the excitation amplitude of coil Lp. The excitation period continues until coil Lxcvr reaches a steady state. During the excitation phase, sensing circuit 30 is protected by diode D, resistor Re, and p-channel transistor MP1, which has a rated voltage sufficient to withstand the voltage VLC at node Nf.

[0067] Once the excitation period ends, the response of the voltage VLC at node Qs (which will be a decaying sine wave of the common-mode voltage Vcm oscillating at the tap between resistors R1 and R2) is as follows: Figure 6 As shown, the sensing circuit 23 senses the signal through capacitor Cq during the sensing period.

[0068] Specifically, comparator 27 asserts the Comp_Out signal when the voltage VLC experiences a rise-to-zero crossing (meaning VLC rises above the Vtr threshold, where "zero" is the hysteresis-modified Vcm, as described above), and cancels the assertion of the Comp_Out signal when the voltage VLC experiences a fall-to-zero crossing (meaning VLC falls below the Vtl threshold, where "zero" is the hysteresis-modified Vcm, as described above). When the Comp_Out signal is asserted, FSM 25 then asserts the control signal Ctrl, thereby enabling or triggering ADC 24 to perform a single sample, which is the digitized amplitude of the output voltage Vout output by amplifier 26 after a time delay td following the assertion of the control signal Ctrl to generate the ADC output signal ADCout, which is received by FSM 25.

[0069] The first way that processing circuit 31 can calculate the Q factor from the samples is by calculating it from two peak samples, for example, by referencing... Figure 7 ,as follows:

[0070]

[0071] Where A1 is the amplitude of the first measured peak value of Vout during the sensing period, and AN is the amplitude of the Nth measured peak value during the sensing period.

[0072] When calculating the Q factor using the first method, FSM 25 stores the value of magnitude A1 and continues to compare the value of magnitude A1 with the current value of magnitude AN. When the value of magnitude AN is less than half of magnitude A1, FSM 25 saves the value of magnitude AN, thereby reducing the number of magnitude AN values ​​stored for calculating the Q factor and reducing the size of the lookup table used for the natural logarithm function.

[0073] The above calculation is also valid if the amplitude A1 is measured not only at the peak, but also at any point within the time delay td of the zero-crossing point on the curve during the sensing period. For example, refer to Figure 8 The amplitude A1 can be measured at any point between t1a and t1b, provided that the amplitude AN is also measured within the same time delay td from the zero-crossing point on the curve within the Nth oscillation period, except for td = 0, td = half the period of the first oscillation, or td = the period of the first oscillation.

[0074] To eliminate errors introduced by the DC offset and / or flicker noise of amplifier 26, the peak and trough values ​​of the oscillation period can be utilized. For example, reference Figure 8 We can obtain amplitude samples A1a and A1b, and amplitude samples ANa and ANb. The Q factor can be calculated as follows:

[0075]

[0076] When calculating the Q-factor using the second method, FSM 25 stores the values ​​of A1a-A1b and continues to compare these values ​​with the current values ​​of ANa-ANb. When the value of ANa-ANb is less than half the value of A1a-A1b, FSM 25 saves these values ​​of magnitude ANa and magnitude ANb, thereby reducing the number of ANa-ANb values ​​stored for calculating the Q-factor and reducing the size of the lookup table used for the natural algorithm function.

[0077] The Q-factor calculation using the second device 15' has now been described; see also [reference needed]. Figure 9 Flowchart 50 describes an operational technique for external object detection using a calculated Q-factor. This technique begins with calibration. During calibration, it is known that the first device 11 and the external object are not close to the second device 15', and the second device 15' is set to Q-factor measurement mode. Then, an excitation period as described above occurs (e.g., the second device 15' is excited in the absence of the second device 11), and its output voltage Vout is sampled during the sensing period. Based on the sampled Vout, the frequency of Vout during the sensing period, i.e., the resonant frequency of the second device 15', is determined and saved as Fr_tx to complete the steps in block 51.

[0078] Now, the operation of the second device 15' and its FSM 25 for performing external object detection is described. Starting from the steps of box 52, when it is unknown whether the first device 11 and / or an external object are near the second device 15', the Q-factor measurement mode is enabled, the excitation period as described above occurs, and the output voltage Vout is sampled during the sensing period. Based on the sample of Vout, the frequency of Vout during the sensing period is determined by the FSM 25, i.e., the resonant frequency of the system (second device 15', first device 11 (if present), and external object (if present)), and it is saved as Fr_sys. The FSM 25 also saves a first sample of Vout (amplitude A1), and an amplitude AN sample used with the amplitude A1 sample to determine the Q-factor, thus completing the steps of box 52.

[0079] If, in step 53, the difference between Fr_tx and the margin Fr_margin is greater than Fr_sys, then FSM 25 can infer in step 54 that the first device 11 exists but the external object does not. Therefore, the second device 15' can continue wireless transmission at full power in step 55, and this is achieved by FSM 25 accordingly instructing logic core 23. Regarding the margin Fr_margin, this is a set tolerance threshold obtained through estimation or analysis.

[0080] If, in step 56, Fr_sys is less than Fr_tx plus Fr_margin but greater than Fr_tx minus Fr_margin, then FSM 25 can infer in step 57 that both the first device 11 and the external object are present. To provide higher accuracy at this step, the Q-factor (shown here as Qsys) calculated during the Q-factor measurement mode is compared with the Q-factor margin value (shown here as Qmargin), and the amplitude A1 or AN sample is compared with the amplitude margin value (shown here as Amargin). Specifically, if, in step 58, Qsys is less than Qmargin, amplitude A1 is less than Amargin, or amplitude AN is less than Amargin, then FSM 25 can infer in step 59 that the external object is located between the first device 11 and the second device 15' or is sufficiently conductive, so the second device 15' should preferably not be making wireless power transmissions at this time, and FSM 25 accordingly instructs logic core 23. On the other hand, if Qsys is greater than Qmargin, or if amplitude A1 is greater than Amargin, or if amplitude AN is greater than Amargin, then FSM 25 can infer in step 60 that the external object is not sufficiently positioned between the first device 11 and the second device 15', or is not sufficiently conductive, so the second device 15' can wirelessly transmit limited power, and FSM 25 accordingly instructs logic core 23.

[0081] If Fr_sys equals Fr_tx in step 64, then FSM 25 can infer in step 65 that neither the first device 11 nor the external object exists, and therefore can perform periodic pings (e.g., every few seconds to check for the presence of the first device 11), and FSM 25 accordingly instructs logic core 23.

[0082] Note here that sufficiently non-conductive objects (such as the plastic casing of a smartphone) may not have a significant effect on the output voltage Vout.

[0083] As described above, the comparator 27 used by transceiver device 15' has a rising threshold and a falling threshold dynamically set by hysteresis, depending on whether the voltage at its input is rising or falling. The comparator sets both the comparator rising threshold Vtr and the comparator falling threshold Vtl to Vcm, but maintains hysteresis so that the actual threshold voltages Vtr and Vtl are dynamic.

[0084] The advantages provided by this comparator 27 may best be described first by referring to a more general example of an electronic device 90 that includes transmitter hardware 91 and receiver or transceiver hardware 92, such as Figure 10AAs shown. Transmitter hardware 91 has a transmitter coil Lxmit coupled thereto, and capacitor Cxmit is a tuning capacitor. Receiver hardware 92 includes a receiver coil Lxcvr, and capacitor Cxcvr is a tuning capacitor. Bridge rectifier 99 has a first input node Ac1 coupled to a first terminal of receiver coil Lxcvr and a second input node Ac2 coupled to a second terminal of receiver coil Lxcvr. Bridge rectifier 99 has an output node Nin coupled to voltage regulator 97, and tank capacitor Ctank is coupled between output node Nin and ground. A rectified voltage Vrect is formed across tank capacitor Ctank. Voltage regulator 97 receives the rectified voltage Vrect at its input and outputs a regulated voltage Vreg to load 98 at its output.

[0085] The bridge rectifier 99 includes a first n-channel transistor T1, a second n-channel transistor T2, a third n-channel transistor T3, and a fourth n-channel transistor T4. The drain of the first n-channel transistor T1 is coupled to the output node Nin, the source is coupled to the input node Ac1, and the gate is coupled to receive the high-side turn-on signal HS1_ON generated by the driver 93 based on the low-side turn-on signal LS2_ON. The drain of the second n-channel transistor T2 is coupled to the output node Nin, the source is coupled to the input node Ac2, and the gate is coupled to receive the high-side turn-on signal HS2_ON generated by the driver 95 based on the low-side turn-on signal LS1_ON. The drain of the third n-channel transistor T3 is coupled to the input node Ac1, the source is coupled to ground, and the gate is coupled to receive the low-side turn-on signal LS1_ON generated by the comparator 94. The inverting terminal of the comparator 94 is coupled to the input node Ac1, and the non-inverting terminal is grounded. The drain of the fourth n-channel transistor T4 is coupled to the input node Ac2, the source is coupled to ground, and the gate is coupled to receive the low-side turn-on signal LS2_ON generated by comparator 96. The inverting terminal of comparator 96 is coupled to the input node Ac2, and the non-inverting terminal is grounded.

[0086] In operation, transmitter 91 drives transmitter coil Lxmit with a time-varying current, causing a time-varying current to be induced in receiver coil Lxcvr, which is then rectified by rectifier 99. The operation of rectifier 99 is as follows, and further reference is also available. Figure 10B .

[0087] When the voltage at node Ac1 crosses zero and the voltage at node Ac2 goes high, comparator 94 outputs a logic high LS1_ON signal to turn on transistors T2 and T3. This has the following effect: current flows from node Ac2 through transistor T2 to output node Nin, current flows from node Ac2 through receiver coil Lxcvr to node Ac1, and current flows from ground through transistor T3 to node Ac1.

[0088] When the voltage at node Ac2 crosses zero and the voltage at node Ac1 goes high, comparator 96 outputs a logic high LS2_ON signal to turn on transistors T1 and T4. This has the following effect: current flows from node Ac1 through transistor T1 to output node Nin, from node Ac1 through receiver coil Lxcvr to node Ac2, and from ground through transistor T4 to node Ac2.

[0089] Comparators 94 and 96 are hysteresis comparators, for example, with a rising threshold Vtr at 0V and a falling threshold Vtl at, for example, -80mV. This response characteristic can be... Figure 10C As seen in the image, the lower threshold Vtl is used to help ensure that the current direction in the receiver coil Lxcvr is completely reversed before the comparator changes state, in order to avoid an incorrect direction that could cause the comparator output to oscillate.

[0090] The novel designs of comparators 94 and 96, such as Figure 11 As shown, each comparator 94, 96 consists of the following: a first p-channel transistor MH1 and a second p-channel transistor MH2. The source of the first p-channel transistor MH1 is coupled to the tail current source 101, the drain is coupled to ground through transistor Rh1, and the gate forms the first comparator input (shown as IN1). The source of the second p-channel transistor MH2 is coupled to the tail current source 101, the drain is coupled to ground through transistor Rh2, and the gate forms the second comparator input (shown as IN2). Resistor Rh3 is selectively connected in parallel with resistor Rh2 via switch SW. The input of gain stage 102 (shown as an amplifier) ​​is coupled to the drains of p-channel transistors MH1 and MH2 at nodes No1 and No2, respectively, and the output OUT of gain stage 102 forms the output of comparators 94, 96. Switch SW operates according to the output OUT of comparators 94, 96.

[0091] Figure 11 The comparators 94 and 96 shown are designed to operate as follows. When OUT is logic low, switch SW is open, and the output load on each side of the comparator is equal because the resistances of Rh1 and Rh2 are equal. The trigger point (to logic high) of the comparator output OUT is located at the point where the voltage Vo1 across Rh1 equals the voltage Vo2 across Rh2. Therefore, at the comparator's trigger point, the output current I1 from the drain of transistor MH1 is equal to the current I2 from the drain of transistor MH2 because Von = In * Rhn, where n is 1 or 2, depending on which side of the comparator structure is being referenced. Since the output current is proportional to the square of the input voltage, the comparator output OUT is asserted when IN1 equals IN2.

[0092] Now, when the output OUT is logic high, the switch SW is closed. This causes an output load imbalance because resistors Rh2 and Rh3 are connected in parallel, so voltage Vo2 becomes less than voltage Vo1. As a result, current I2 increases to ensure that voltage Vo1 remains equal to Vo2 to reach the trigger point. Therefore, the comparator output will not trigger when IN1 = IN2, and the trigger point (according to the transition of output OUT from high to low) is shifted according to the value of resistor Rh3.

[0093] This type of hysteresis comparator is very useful when the comparator (as shown in the figure) has a resistive load, and it works well in the aforementioned electronic device 90.

[0094] However, PVT variations can cause offsets, leading to inaccurate zero-crossing detection performed by comparators 94 and 96, thus making this comparator design suboptimal for some applications. For example, this comparator design could be used as comparator 27 in the aforementioned transceiver device 15', although functionality could be improved if comparator 27 included an auto-zero offset cancellation component. However, auto-zero offset cancellation components cannot work with resistive loads, therefore they would have an active load.

[0095] This design is in Figure 12 As shown, comparator 27 can also be used in the transceiver device 15' described above. Comparator 27 consists of the following components: hysteresis stage 27a, auto-zero stage 27b, and gain stage 27c.

[0096] Hysteresis stage 27a consists of p-channel transistors MH1 and MH2. The sources of MH1 and MH2 are coupled to current source 101, and the drains of MH1 and MH2 are coupled to nodes No1 and No2, respectively. Resistor Rh1 is coupled between node No1 and ground, and resistor Rh2 is coupled between node No2 and ground. The resistances of resistors Rh2 and Rh3 can be equal. Switch S5 selectively couples resistors Rh2 and Rh3 in parallel in response to the output OUT of comparator 27.

[0097] The gate of p-channel transistor MH1 is selectively coupled to input IN1 via switch S1, and switch S1 operates in response to the cancellation assertion of the auto-zero signal AZ. The gate of p-channel transistor MH1 is also selectively coupled to ground via switch S3 in response to the auto-zero signal assertion. The gate of p-channel transistor MH2 is selectively coupled to input IN2 via switch S2, and switch S2 operates in response to the cancellation assertion of the auto-zero signal AZ. The gate of p-channel transistor MH2 is also selectively coupled to ground via switch S4 in response to the auto-zero signal assertion.

[0098] The auto-zero stage 27b consists of p-channel transistors MH3 and MH4. The sources of p-channel transistors MH3 and MH4 are coupled to tail current source 103, and the drains of MH3 and MH4 are coupled to nodes No3 and No4, respectively. The gate of p-channel transistor MH3 is coupled to node No1, and the gate of p-channel transistor MH4 is coupled to node No2. The drain of n-channel transistor MH5 is coupled to node No3, and its source is coupled to ground. The drain of n-channel transistor MH6 is coupled to node No4, and its source is coupled to ground. Switch S6, in response to the assertion of the auto-zero signal AZ, couples the gate of n-channel transistor MH5 to the drain of n-channel transistor MH5 and to the top plate of capacitor Ch1. The bottom plate of capacitor Ch1 is coupled to ground. Switch S7, in response to the assertion of the auto-zero signal AZ, couples the gate of n-channel transistor MH6 to the drain of n-channel transistor MH6 and to the top plate of capacitor Ch2. The bottom plate of capacitor Ch2 is coupled to ground.

[0099] Gain stage 27c consists of amplifiers with inputs coupled to nodes No3 and No4, and provides comparator output OUT.

[0100] Figure 12 The operation of comparator 27 is as follows. In auto-zero mode, the auto-zero signal AZ is asserted to open switches S1 and S2 while closing switches S3, S4, S6, and S7. Any offset caused by the resistance change between resistors Rh1 and Rh2 is amplified by transistors MH3 and MH4, and samples are taken across capacitors Ch1 and Ch2.

[0101] When the auto-zero mode is complete, the auto-zero signal AZ is canceled to open switches S3, S4, S6, and S7. Note that the offset is still stored across capacitors Ch1 and Ch2. The auto-zero signal cancellation assertion is also used to close switches S1 and S2 to receive input.

[0102] When OUT is logic low, switch S5 is open and the output load on each side of hysteresis stage 27a is equal because the resistances of Rh1 and Rh2 are equal. The trigger point (to logic high) of the comparator output OUT is located at the point where the voltage Vo1 across Rh1 is equal to the voltage Vo2 across Rh2. Therefore, at the comparator's trigger point, the output current I1 from the drain of transistor MH1 is equal to the current I2 from the drain of transistor MH2, because Von = In * Rhn, where n is 1 or 2, depending on which side of hysteresis stage 27a is referenced. Since the output current is proportional to the square of the input voltage, the comparator output OUT is asserted when IN1 equals IN2. Note that any resistance imbalance between resistors Rh1 and Rh2 is compensated by n-channel transistors MH5 and MH6, which are biased by the offset stored across capacitors Ch1 and Ch2 during auto-zero mode.

[0103] Now, when the output OUT is logic high, switch S5 is closed. This causes an output load imbalance because resistors Rh2 and Rh3 are connected in parallel, so voltage Vo2 becomes less than voltage Vo1. As a result, current I2 increases to ensure that voltage Vo1 remains equal to Vo2 to reach the trigger point. Therefore, the comparator output does not trigger when IN1 = IN2, and the trigger point (according to the transition from high to low of output OUT) is shifted according to the value of resistor Rh3. Again, as mentioned above, any resistance imbalance between resistors Rh1 and Rh2 is compensated by n-channel transistors MH5 and MH6, which are biased by the offset stored across capacitors Ch1 and Ch2 during auto-zero mode.

[0104] Figures 13A-13C The diagram shows the operating characteristics of comparator 27 with and without auto-zeroing. Note that hysteresis sets Vtr to 0V and Vtl to -75mV. The offset at Vtr without auto-zeroing can be 15.3mV, and the offset at Vtl without auto-zeroing can be 13.1mV; with auto-zeroing, the offset at Vtr is reduced to 0.3mV, and the offset at Vtl is reduced to 5.7mV.

[0105] While this disclosure has been described with respect to a limited number of embodiments, those skilled in the art who benefit from this disclosure will understand that other embodiments may be contemplated without departing from the scope of this disclosure disclosed herein. Therefore, the scope of this disclosure should be limited only by the appended claims.

Claims

1. A wireless power circuit capable of operating in a transceiver mode and a Q-factor measurement mode, the wireless power circuit comprising: a coil having a first terminal and a second terminal; a bridge rectifier having a first input and a second input coupled to the first terminal and the second terminal of the coil, respectively, and having an output coupled to a rectified voltage node; a drive circuit coupled to the first terminal of the coil and configured to drive the coil with a pulsed signal when in the Q-factor measurement mode; a protection circuit coupling the first terminal of the coil to a first node when in the Q-factor measurement mode and decoupling the first terminal of the coil from the first node when in the transceiver mode; and a Q-factor sensing circuit comprising: an amplifier having inputs coupled to the first node and a common mode voltage, and the amplifier generating an output signal having an output voltage; a comparator having inputs coupled to a second node and the common mode voltage, and the comparator generating a comparison output signal of a voltage at the first terminal of the coil to the common mode voltage; a processing circuit configured to receive the comparison output signal and generate an enable signal based on the comparison output signal; and an analog-to-digital converter configured to digitize the output voltage and provide the digitized output voltage to the processing circuit for calculating a Q-factor of the coil when enabled by the enable signal from the processing circuit.

2. The wireless power circuit of claim 1, wherein the comparator is configured to have a rising threshold equal to a common mode voltage, a falling threshold equal to the common mode voltage, and a hysteresis, such that when a voltage at the second node falls, an effective rising threshold is equal to the rising threshold plus the hysteresis and an effective falling threshold is equal to the falling threshold, and such that when the voltage at the second node rises, the effective falling threshold is equal to the falling threshold minus the hysteresis and the effective rising threshold is equal to the rising threshold.

3. The wireless power circuit of claim 1, wherein the processing circuit calculates the Q-factor of the coil based on a magnitude of a first sample of the output voltage taken at a first peak of the output voltage, and a magnitude of at least one other sample of the output voltage taken at at least one other peak of the output voltage.

4. The wireless power circuit of claim 3, wherein the processing circuit calculates the Q-factor as: where Ai is the first sample of the output voltage taken at the first peak of the output voltage, AN is an Nth sample of the output voltage taken at an Nth peak of the output voltage. ​ ​ 5. The wireless power circuit of claim 1, wherein the processing circuit calculates the Q factor of the coil based on a difference between a first sample of the output voltage taken at a first peak of the output voltage and a second sample of the output voltage taken at a first trough of the output voltage, and a difference between a third sample of the output voltage taken at another peak of the output voltage and a fourth sample of the output voltage taken at another trough of the output voltage.

6. The wireless power circuit of claim 5, wherein the processing circuit calculates the Q factor as: where A la is the first sample, A lb is the second sample, ANa is the third sample, and ANb is the fourth sample, and N is a sequence number of an oscillation period of the output voltage.

7. The wireless power circuit of claim 1, wherein the excitation circuit comprises: a driver configured to receive a drive signal and generate an excitation signal based on the drive signal; and a p-channel transistor having a source coupled to a supply voltage, a drain coupled to an anode of a diode through a resistance, and a gate coupled to receive the excitation signal; wherein the diode has a cathode coupled to the first terminal of the coil.

8. The wireless power circuit of claim 1, wherein the amplifier has a non- inverting terminal coupled to the common mode voltage, an inverting terminal capacitively coupled to the first node through a first capacitor, and an output coupled to the non- inverting terminal through a second capacitor, the output also coupled to the analog-to-digital converter.

9. The wireless power circuit of claim 1, wherein the comparator has a non- inverting terminal coupled to the first node, an inverting terminal coupled to the common mode voltage, and an output at which the comparison output signal is generated.

10. The wireless power circuit of claim 1, further comprising a first resistance coupled between a supply voltage and the first node, and a second resistance coupled between the first node and ground.

11. The wireless power circuit of claim 1, further comprising a third resistance coupled between a supply voltage and a second node, and a fourth resistance coupled between the second node and ground, the common mode voltage being generated at the second node.

12. The wireless power circuit of claim 1, wherein the protection circuit comprises a pair of series coupled transistors coupled between a first node and the first terminal of the coil and having gates coupled to a Q factor sense enable signal, the Q factor sense enable signal being asserted when in a Q factor sense mode and de-asserted when not in a Q factor sense mode.

13. The wireless power circuit of claim 1, ​ ​ wherein in the Q-factor measurement mode, the processing circuit is configured to determine that a second wireless power circuit is proximate to the wireless power circuit but that no external object is present between the second wireless power circuit and the wireless power circuit by: determining that a frequency of the output signal is less than a known frequency of the output signal in the absence of the second wireless power circuit and the external object minus a margin value; and determining that the frequency of the output signal is greater than the known frequency of the output signal in the absence of the second wireless power circuit and the external object plus a margin value; determining that the frequency of the output signal is less than the known frequency of the output signal in the absence of the second wireless power circuit and the external object minus the margin value; determining whether the Q-factor is less than a Q-factor margin value; determining whether a first sample of the output voltage is less than an amplitude margin value; and determining whether another sample of the output voltage is less than the amplitude margin value; if the Q-factor is less than the Q-factor margin value, the first sample is less than the amplitude margin value, and the other sample is less than the amplitude margin value, causing the wireless power circuit to not wirelessly transfer power; and if the Q-factor is not less than the Q-factor margin value, or if the first sample is not less than the amplitude margin value, or if the other sample is not less than the amplitude margin value, causing the wireless power circuit to wirelessly transfer a limited amount of power, the limited amount of power being less than an amount of power that the wireless power circuit would otherwise transfer.

15. The wireless power circuit of claim 1, wherein in the Q-factor measurement mode, the processing circuit is configured to determine that a second wireless power circuit is not proximate to the wireless power circuit and that an external object is proximate to the wireless power circuit by: determining that a frequency of the output signal is greater than a known frequency of the output signal in the absence of the second wireless power circuit and the external object plus a margin value; and causing the wireless power circuit to not wirelessly transfer power.

16. The wireless power circuit of claim 1, wherein in the Q-factor measurement mode, the processing circuit is configured to determine that a second wireless power circuit is not proximate to the wireless power circuit and that no external object is proximate to the wireless power circuit by determining that a frequency of the output signal is equal to a known frequency of the output signal in the absence of the second wireless power circuit and the external object.

17. A method of operating a wireless power circuit, comprising the steps of: ​ ​ 1) energize a coil of the wireless power circuit in the absence of a second wireless power circuit; 2) measure a first resonant frequency at a sense node of the wireless power circuit once energization is released; 3) energize the coil of the wireless power circuit; 4) measure a second resonant frequency at the sense node once energization is released; 5) determine a Q factor by the Q factor sense circuit as defined in claim 1; and 6) determine, based at least on the first resonant frequency, the second resonant frequency, and a frequency margin value, whether: a) the second wireless power circuit is proximate to the wireless power circuit but no external object is present between the second wireless power circuit and the wireless power circuit; b) the second wireless power circuit is proximate to the wireless power circuit but an external object is present between the second wireless power circuit and the wireless power circuit; c) the second wireless power circuit is not proximate to the wireless power circuit and an external object is proximate to the wireless power circuit; or d) the second wireless power circuit is not proximate to the wireless power circuit and no external object is proximate to the wireless power circuit. cause the wireless power circuit to wirelessly transfer power at a full power level in response to determining that the second wireless power circuit is proximate to the wireless power circuit but no external object is present between the second wireless power circuit and the wireless power circuit.

18. The method of claim 17, wherein determining that the second wireless power circuit is proximate to the wireless power circuit but that no external object exists between the second wireless power circuit and the wireless power circuit is performed by determining that the second resonant frequency is less than the first resonant frequency minus the frequency margin value; and the method further comprises:

19. The method of claim 17, wherein determining the Q factor comprises taking a first sample and a second sample of an output voltage at the sense node.

20. The method of claim 19, wherein determining that the second wireless power circuit is proximate to the wireless power circuit but an external object is present between the second wireless power circuit and the wireless power circuit is performed by: determining that the second resonant frequency is greater than the first resonant frequency plus the frequency margin value; determining that the second resonant frequency is less than the first resonant frequency minus the frequency margin value; determining whether the Q factor is less than a Q factor margin value; determining whether the first sample is less than an amplitude margin value; and determining whether the second sample is less than the amplitude margin value; the method further comprising causing the wireless power circuit to not make wireless power emissions if the Q factor is less than the Q factor margin value, the first sample is less than the amplitude margin value, and the second sample is less than the amplitude margin value; and the method further comprising causing the wireless power circuit to wirelessly transfer a limited amount of power that is less than an amount of power that the wireless power circuit would otherwise transfer if the Q factor is not less than the Q factor margin value, or if the first sample is not less than the amplitude margin value, or if the second sample is not less than the amplitude margin value. cause the wireless power circuit to not make wireless power emissions in response to determining that the second wireless power circuit is not proximate to the wireless power circuit and that the external object is proximate to the wireless power circuit.

21. The method of claim 17, wherein determining that the second wireless power circuit is not proximate to the wireless power circuit and that the external object is proximate to the wireless power circuit is performed by determining that the second resonant frequency is greater than the first resonant frequency plus the frequency margin value; and the method further comprises: ​ 22. The method of claim 17, wherein determining that the second wireless power circuit is not proximate to the wireless power circuit and that the external object is also not proximate to the wireless power circuit is performed by determining that the second resonant frequency is equal to the first resonant frequency.

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