Single-input wideband load-modulated balanced amplifier and design method thereof

Abstract

This invention discloses a single-input broadband load-modulated balanced amplifier and its design method. By employing a single-input configuration, it achieves fully automatic modulation of the load impedance of the load-modulated balanced amplifier, eliminating the need for manual adjustment and testing compared to traditional load-modulated balanced amplifiers. The addition of a dual-impedance pre-matching network brings the transistor load impedance closer to its optimal value, eliminating the need for manual adjustment to the optimal impedance and improving amplifier back-off efficiency. This invention offers advantages over traditional load-modulated balanced amplifiers, including superior performance, ease of application, and convenient measurement.

Description

Technical Field

[0001] This invention belongs to the field of radio frequency microwave communication and relates to a single-input broadband load modulation balanced amplifier and its design method. Specifically, it is a high-efficiency single-input reconfigurable load modulation balanced amplifier that can operate in a wide frequency range. Background Technology

[0002] Power amplifiers (PAs) are increasingly used in the 5G era, such as in carrier aggregation and other high-data-rate communication applications, imaging, and radar. Furthermore, modern communication systems require high peak-to-average power ratio (PAPR) signals to operate over a wide power dynamic range. Bandwidth and linearity requirements significantly exceed the specifications offered by traditional amplifier designs. Therefore, PA design must simultaneously consider the three crucial parameters of bandwidth, linearity, and efficiency, which has been a long-standing challenge for designers.

[0003] Load-modulated power amplifiers (DPPAs) are favored by researchers among various power amplifier types due to their high efficiency, wide power back-off range, and good linearity. Typically, power amplifier efficiency reaches its optimal level only at saturation. However, DPPAs can achieve high efficiency within the power back-off range (low power) by dynamically changing the load impedance. Two representative architectures are the Doherty amplifier and the Outphasing amplifier. The Doherty amplifier dynamically adjusts the load through the current relationship between the sub-amplifiers, increasing the load impedance at the power back-off point to cause the transistors to saturate earlier, thus achieving optimal efficiency. The Outphasing amplifier uses angle modulation to saturate both transistors and then uses power combining networks to offset the reactive virtual part, also achieving high efficiency within the power back-off range. However, both architectures are limited by insufficient operating bandwidth. In recent years, maintaining bandwidth while ensuring the efficiency of DPPAs has been a key research focus. Based on this, a new DPPA architecture has been proposed.

[0004] Load-modulated balanced amplifiers (LMBAs), employing wideband devices and featuring load modulation capabilities, have garnered significant attention since their inception as a novel load-modulated amplifier architecture. A LMBA circuit comprises two paths: a control path and a balanced path. The control path consists of a single-transistor amplifier, while the balanced path comprises two perfectly symmetrical amplifiers. These two paths are connected and power-combined via couplers. During operation, the coupler's port impedance, acting as the load impedance of the balanced amplifier, is controlled by the amplitude and phase of the control path amplifier's output signal. Theoretically, the output power of each path can be fully output after entering the coupler. Therefore, by manually adjusting the magnitude and phase of the control path signal source power, load modulation can be achieved. By manually adjusting the load impedance to its optimal state at the power saturation and power back-off points, high efficiency and a large back-off range can ultimately be achieved in a wideband configuration.

[0005] However, this architecture also has the following drawbacks: First, it requires two signal sources as inputs, which is inconsistent with traditional power amplifiers. This not only increases structural load but also makes the concept of gain somewhat vague, thus making definition and measurement difficult. Second, unlike typical load-modulated power amplifiers, this amplifier needs to dynamically adjust the phase shifter and input power of the control circuit according to changes in the balanced circuit input power. This adjustment can only be performed manually during testing, and it cannot achieve the high efficiency within the fully automatic power back-off range like traditional load-modulated power amplifiers, making testing and implementation more difficult.

[0006] Therefore, given the shortcomings of current technology, it is necessary to conduct research to provide a solution for a fully automatic single-input broadband load modulation balanced amplifier. Summary of the Invention

[0007] The purpose of this invention is to address the shortcomings of existing technologies by providing a single-input fully automatic load modulation balanced amplifier with broadband characteristics, based on the coupler port impedance trajectory under single-input conditions and by designing the order of transistor saturation in the balanced and control circuits.

[0008] To overcome the shortcomings of existing technologies, this invention employs a dual impedance pre-matching network matrix.

[0009] A single-input broadband load-modulated balanced amplifier includes a power distribution circuit, a phase-compensated microstrip line, and two branches. The two branches include a balanced path and a control path. The balanced path includes a first 3-dB directional coupler circuit, a second 3-dB directional coupler circuit, and upper and lower branches with identical structures. Each branch includes a broadband input matching circuit, a first RC stabilization circuit, a transistor, and a dual-impedance pre-matching circuit. The control path includes a control path broadband input matching circuit, a second RC stabilization circuit, a transistor, and a control path broadband output matching circuit.

[0010] The power distribution circuit is used to distribute the power of a single input signal source to the balanced circuit and the control circuit, and can be implemented using a Wilkinson power divider.

[0011] Preferably, the power distribution circuit includes parallel transmission lines L1 and L2, and a resistor R1; one end of parallel transmission line L1 is connected to one end of parallel transmission line L2 and serves as the input of a single-input broadband load modulation balanced amplifier; the other end of parallel transmission line L1 is connected to one end of resistor R1 and serves as one output of the power distribution circuit; the other end of parallel transmission line L2 is connected to the other end of resistor R1 and serves as the other output of the power distribution circuit.

[0012] The phase-compensated microstrip line L5 adjusts the load impedance trajectory to the optimal impedance position according to design requirements; one end of the phase-compensated microstrip line L5 is connected to the other output of the power distribution circuit, and the other end is connected to the input of the first 3-dB directional coupler.

[0013] The first and second 3-dB directional couplers are located after the circuit input and before the circuit output, respectively, to ensure that the phase of the upper and lower paths in the balanced circuit is constant. The first and second 3-dB directional couplers adopt a bridge structure. The bridge structure has the advantages of simple structure, stable performance and wide bandwidth, and is suitable as the core power combining device of the amplifier.

[0014] Preferably, the first 3-dB directional coupler Coupler1 includes a first parallel transmission line L15-1, a second parallel transmission line L16-1, a third parallel transmission line L15-2, and a fourth parallel transmission line L16-2. One end of the first parallel transmission line L15-1 is connected to one end of the second parallel transmission line L16-1 and serves as the input terminal of the first 3-dB directional coupler, connected to the phase compensation microstrip line L5. The other end of the first parallel transmission line L15-1 is connected to the second parallel transmission line L16-2. One end of line -2 is connected and serves as the through end of the first 3-dB directional coupler, which is connected to the input end of the balanced path up branch; one end of the second parallel transmission line L15-2 is connected to the other end of the second parallel transmission line L16-2 and serves as the coupling end of the first 3-dB directional coupler, which is connected to the input end of the balanced path down branch; the other end of the first parallel transmission line L16-1 is connected to the other end of the second parallel transmission line L15-2 and serves as the isolation end of the first 3-dB directional coupler, which is connected to a standard 50Ω resistor and grounded.

[0015] Preferably, the second 3-dB directional coupler Coupler2 includes a fifth parallel transmission line L17-1, a sixth parallel transmission line L18-1, a seventh parallel transmission line L17-2, and an eighth parallel transmission line L18-2. One end of the fifth parallel transmission line L17-1 is connected to one end of the sixth parallel transmission line L18-1, serving as the coupling end of the second 3-dB directional coupler and connected to the output end of the balanced path up branch. The other end of the sixth parallel transmission line L18-1 is connected to one end of the seventh parallel transmission line L17-2, serving as the through end of the second 3-dB directional coupler and connected to the output end of the balanced path down branch. The other end of the fifth parallel transmission line L17-1 is connected to one end of the eighth parallel transmission line L18-2, serving as the isolation end of the second 3-dB directional coupler and connected to the control path output end. The other end of the seventh parallel transmission line L17-2 is connected to the other end of the eighth parallel transmission line L18-2, serving as the input end of the second 3-dB directional coupler and connected to the circuit output end.

[0016] The broadband input matching circuit is designed with a broadband topology based on the optimal input impedance of the transistor, which can maximize the signal power input to the transistor.

[0017] Preferably, the broadband input matching circuit includes a DC blocking capacitor C1, a series transmission line L3, and a series transmission line L4 connected in sequence; one end of the DC blocking capacitor C1 serves as the input terminal of the broadband input matching circuit, and the other end is connected to one end of the series transmission line L3; the other end of the series transmission line L3 is connected to one end of the series transmission line L4; the other end of the series transmission line L4 serves as the output terminal of the broadband input matching circuit and is connected to the input terminal of the RC stabilization circuit.

[0018] The RC stabilization circuit uses capacitors and resistors to form a negative feedback loop to improve stability. It is generally placed at the gate to prevent amplifier self-oscillation.

[0019] The three-way RC stabilization circuit consists of parallel RC circuits, including a parallel capacitor C2 and a parallel resistor R2. Preferably, the three RC stabilization circuits have identical structures; one end of each RC stabilization circuit is connected to the output of the wideband input matching circuit, and the other end is connected to the gate V of the transistor. gs It is connected to the gate bias.

[0020] The dual impedance pre-matching circuit can make the load impedance trajectory in the power back-off interval coincide with the transistor's optimal efficiency region and maximum output power region, thereby improving amplifier efficiency.

[0021] Preferably, the dual impedance pre-matching circuit includes a parallel transmission line L6, a series transmission line L7, a parallel transmission line L8, a series transmission line L9, and a DC blocking capacitor C3; one end of the parallel transmission line L6 is connected to one end of the series transmission line L7 as the input terminal of the dual impedance pre-matching circuit, and is connected to the drain of the transistor; the other end of the parallel transmission line L6 is biased to the drain by V. ds Connected; the other end of the series transmission line L7 is connected to one end of the parallel transmission line L8 and one end of the series transmission line L9; the other end of the parallel transmission line L8 is in an open circuit state; the other end of the series transmission line L9 is connected to one end of the DC blocking capacitor C3; the other end of the DC blocking capacitor C3 is connected to the port of the 3dB directional coupler.

[0022] Another object of the present invention is to provide a design method for the above-described single-input load modulated balanced amplifier.

[0023] Step 1: Design an RC stabilization circuit and continuously adjust the values ​​of resistors and capacitors to ensure that the stabilization parameter is greater than 1 across the entire frequency band;

[0024] Step 2: Determine the input and output impedances of the transistor for subsequent matching;

[0025] Step 3: Using the optimal input impedance obtained in Step 2, construct a broadband input matching circuit and a broadband control circuit output matching circuit.

[0026] Step 4: Debug the first and second 3-dB directional couplers to optimize circuit bandwidth and performance.

[0027] Step 5: Debug the Wilkinson power divider circuit to achieve equal power distribution and meet broadband requirements.

[0028] Step Six: Design the circuit according to the above content. After the connection is completed, adjust the bias and phase compensation microstrip lines of the Wilkinson power divider stub length control circuit and balance circuit transistors to make the control circuit transistors saturate in advance. During the debugging process, ensure that the load impedance at the back point in the load impedance trajectory is greater than the load impedance at the saturation point and that the curve is as close as possible to the inductive region of the Smith chart.

[0029] Preferably, the debugging process that causes the control circuit transistor to saturate prematurely is as follows:

[0030] To achieve the desired effect, the control circuit transistor needs to saturate prematurely so that the ratio of control circuit output power to balanced circuit output power decreases as input power increases. This can be achieved by keeping the control circuit output power constant while increasing the balanced circuit output power with increasing input power. Adjusting the Wilkinson power divider stub length can either increase the control circuit input power or decrease the gate bias voltage of the balanced circuit transistor to operate the control circuit transistor in Class B mode and the balanced circuit transistor in Class C mode.

[0031] Preferably, the adjustment process for ensuring that the load impedance at the pullback point in the load impedance trajectory is greater than the load impedance at the saturation point, and that the curve is as close as possible to the inductive region of the Smith chart, is as follows:

[0032] Based on the load pull results, it is known that the phase of the optimal load impedance will lag when the frequency increases. The phase difference between the two sides of the power divider can be adjusted by using a phase compensation microstrip line to achieve a broadband effect. The phase compensation microstrip line should be adjusted so that the load impedance trajectory curve is located to the left of the inductive region of the Smith chart.

[0033] Step 7: Design a dual-impedance pre-matching network that can match the port impedance of the second 3-dB directional coupler to the optimal impedance at the saturation point and the optimal impedance at the backoff point of the balanced circuit transistor. Based on the current-voltage-impedance relationship, list the impedance matrix of the dual-impedance pre-matching network and then synthesize the dual-impedance pre-matching network.

[0034] The dual-impedance pre-matching circuit achieves port impedance matching of the second 3-dB directional coupler to the optimal impedance at the saturation point and the optimal impedance at the backoff point of the balanced circuit transistor; specifically as follows:

[0035] The lossless reciprocal impedance matrix Z of the dual-impedance pre-matched circuit:

[0036]

[0037] Where V b V′ is the output voltage of the balanced circuit transistor. b To determine the output voltage after adding a dual impedance pre-matching circuit, I b I′ is the output current of the balanced circuit transistor. bZ represents the output current after adding the dual impedance pre-matching circuit. 11 Z 12 Z 21 These are all elements in the Z-matrix of the dual impedance pre-matched circuit.

[0038] According to the Z matrix in formula (1), we can obtain:

[0039]

[0040] Z b This is the optimal load impedance for the balanced circuit transistor.

[0041] Since the dual-impedance pre-matched circuit is lossless and reciprocal, therefore:

[0042]

[0043] Where P1 is the output power of the balanced transistor when the dual impedance pre-matching circuit is not applied, Re(Z) b ) is Z b The real part of P2 is the saturated output power of the balanced circuit transistor, which can be found in the datasheet.

[0044] The impedance matrix of the dual impedance pre-matching network is listed based on the current-voltage-impedance relationship, and then the dual impedance pre-matching network is synthesized, as follows:

[0045] Based on formula (3) and the transistor saturated output power and back-off output power obtained from the transistor datasheet, determine the Z in the dual impedance pre-matching matrix. 11 Z 12 Z 21 Then, the Z matrix of the dual impedance pre-matching circuit is transformed into an ABCD matrix, and then the topology and transmission line values ​​of the dual impedance pre-matching network are synthesized.

[0046] Step 8: Connect the above dual impedance pre-matching network to the circuit in Step 6, and repeatedly adjust the calculated microstrip line values ​​to optimize the overall performance of the amplifier.

[0047] The beneficial effects of this invention are: by adopting a single-input form, the load impedance of the load-modulated balanced power amplifier is fully automatically modulated, which eliminates the need for manual adjustment and testing compared to traditional load-modulated power amplifiers; the addition of a dual impedance pre-matching network makes the transistor load impedance closer to the optimal value, eliminating the need for the traditional manual adjustment of the load impedance to the optimal impedance, and improving the amplifier back-off efficiency.

[0048] This invention offers advantages over traditional load-modulated balanced amplifiers, including superior performance, ease of application, and convenient measurement. Attached Figure Description

[0049] Figure 1 This is a schematic diagram of the structure of a single-input load modulation balanced amplifier according to the present invention;

[0050] Figure 2 This is a structural block diagram of a conventional load-modulated balanced amplifier in this invention;

[0051] Figure 3 This is a simplified block diagram of the coupler network in this invention;

[0052] Figure 4 This is a block diagram of the dual impedance pre-matching network in this invention;

[0053] Figure 5 The results are obtained by simulating the invention in a wide frequency band (3.4GHz-3.7GHz) using simulation software. Detailed Implementation

[0054] The following are specific embodiments of the present invention, which are described in conjunction with the accompanying drawings. However, the present invention is not limited to these embodiments.

[0055] Figure 1 The diagram shows a single-input load modulation balanced amplifier structure according to the present invention. The power amplifier includes a power distribution circuit, a broadband input matching circuit, a phase compensation microstrip line, a three-way RC stabilization circuit, a dual impedance pre-matching circuit, a control-path broadband input matching circuit, a control-path broadband output matching circuit, and two 3dB directional coupler circuits.

[0056] Figure 2 The diagram shown is a basic block diagram of a traditional LMBA. The following is a brief description of the basic principle of LMBA load modulation. In traditional LMBA, the coupler port impedance Z is changed by altering the values ​​of RFcontrol and RFbalance. b1 and Z b2 Size, Z b1 and Z b2 The value can be calculated from the Z matrix of the coupler:

[0057]

[0058] Due to the characteristics of balanced amplifiers, Z b1 and Z b2 In ideal conditions, they are completely equal, Z b1 and Z b2 In the design, this refers to the load impedance to be modulated. In the above formula, φ represents I. c with I b2Given the relative phase of the two phases, let Γ be the reflection coefficient of the coupler port, which is also the load impedance of the balanced amplifier, and τ be Pcon / Pbal. Γ satisfies:

[0059]

[0060] This formula shows that the reflection coefficient curve is a circle centered at the origin on the Smith chart, with a radius proportional to τ. Therefore, within the selected backoff interval, manually adjusting the value of RFcontrol and the phase shift value of the phase shifter can control the amplitude and phase of the reflection coefficient, i.e., changing the load impedance to the optimal value. However, the current theory is not entirely applicable to single-input LMBA because when RFbalance and RFcontrol are combined into one input, RFcontrol cannot be manually adjusted because it is the same input as RFbalance; it can only change with the input signal. Furthermore, since the transistor is a voltage-controlled current source, α is defined as I... c with I b The ratio of I to RF control changes when the input signal changes, resulting in load modulation at the coupler port. b This inevitably leads to changes, making the value of α uncontrollable. Correspondingly, the phase and amplitude of the reflection coefficient will also change with power, and this change currently appears uncontrollable. Therefore, it is necessary to further determine the trend of the value of τ as the input power changes. Only then can the variation law of the port reflection coefficient amplitude be obtained based on the proportional relationship between the reflection coefficient amplitude and τ, and the required load modulation trajectory be designed based on this law. Finally, based on the change of the reflection coefficient phase under single-input conditions, combined with the relationship between phase and amplitude changes, the trajectory of the reflection coefficient as a function of input power is finally plotted. Further details are as follows:

[0061] First, let's examine the phase. Let the phase of the reflection coefficient Γ at the coupler port be θ. Since θ only depends on the control amplifier and the balanced amplifier at the coupling end, and the balanced amplifier is perfectly symmetrical, for ease of analysis, we only need to study the relationship between the signal and the phase of the reflection coefficient at these two ports. Ideally, assume that the input and through terminals of the coupler are connected to matched loads, and only the coupling and control terminals are connected to 50Ω signal sources. Since the other ports are connected to matched loads, the characteristics of these two ports can be directly obtained from the coupler's S-parameter matrix. A detailed schematic diagram can be seen... Figure 3 .in addition, Figure 3 The two signal sources on the left and right are equivalent to the signals entering the coupling terminal and the isolation terminal, respectively. The Γ mentioned earlier as needing to be studied in detail is... Figure 3 Г in in Analyzing the characteristics of a two-port network easily yields the following:

[0062]

[0063] Under ideal conditions, the termination impedances of Port1 and Port2 should be 50 ohms, matching the characteristic impedance of the coupler. Therefore, the port reflection coefficient is zero. 11 =S 22 =0, then we can get Г in Phase:

[0064] Γ in (θ)=S 12 (θ)+S 21 (θ)+Γ L (θ)

[0065] In summary, Г in The phase is equal to Γ under ideal conditions. L The phase. Г L The phase needs to be determined by finding the incident and reflected waves of Port2. For Port2, the signal emitted as a signal source is the reflected wave, so the phase of the reflected wave is θ2. The incident wave should be the signal entering from Port1. Combining the S-parameter matrix of the coupler, we know that there is no phase difference between the through end and the isolation end, so the phase of the incident wave is θ1. Therefore, under ideal conditions, the phase relationship is obtained as follows:

[0066] Γ in (θ)=θ2-θ1

[0067] Extending this to LMBA, it can be deduced that when terminating a matched load, changes in input power will not affect the phase of the reflection coefficient. The phase value of the reflection coefficient is always equal to the phase difference between the control signal and the balance signal, and can be directly controlled by a phase shifter.

[0068] Obviously, in actual circuit design, the coupler port is not connected to a matched load, and the amplifier's load impedance changes with power. Therefore, when designing a single-input LMBA, the effect of input power changes on the phase needs to be considered. Since the load impedance is constantly changing, port reflection exists. Therefore, the phase of the reflection coefficient is not solely controlled by the phase shifter; the phase is affected by multiple variables and requires qualitative analysis. According to well-known theory, we have:

[0069]

[0070] Substitute it into the previous Z text b1 From the calculation formula, the phase θ of Г is obtained:

[0071]

[0072] Clearly, θ is determined by both φ and α, where α is I. c with I bThe ratio of φ to θ. In traditional LMBA designs, due to the dual-input architecture, φ is a variable during LMBA operation, and analyzing the change of θ under two variables is obviously cumbersome. However, in a single-input LMBA architecture, since the control circuit and the balancing circuit are from the same signal source, the change of their relative phase difference φ is almost negligible.

[0073] Therefore, treating φ as a constant and combining it with the formula for calculating the phase θ of Γ, we can see that under single-input LMBA conditions, the phase of the reflection coefficient is inversely proportional to α. In conclusion, under single-input conditions, the phase of the load impedance can be controlled by appropriately varying α.

[0074] In summary, after obtaining the relationship between the reflection coefficient at the coupler port and the amplitude and phase of the load impedance, a single-input load modulation balanced amplifier can be designed based on this theory.

[0075] Step 1: Design an RC stabilization circuit. Continuously adjust the values ​​of C2 and R2 during single-transistor testing until no self-oscillation occurs within a bandwidth of three harmonics of the center frequency under single-transistor conditions.

[0076] Step Two: Optimize the performance of a broadband Class AB single-transistor power amplifier as the control circuit amplifier. Then, design a broadband input matching circuit based on the optimal input impedance of a Class C transistor as the input matching circuit for the balanced power amplifier, and repeatedly debug it to achieve optimal performance. Finally, design a 3dB directional coupler and a power divider, and optimize their performance across the entire frequency band.

[0077] Step 3: Assemble the above circuit according to... Figure 1 The connection shown illustrates the measurement of the port impedance of the second 3dB directional coupler of the coupler to improve power back-off efficiency under reduced input power. To achieve high back-off efficiency under single-input conditions, the load impedance at the back-off point needs to be increased to induce early transistor saturation. Therefore, a load trajectory curve needs to be fitted so that the load impedance at the back-off point is greater than the load impedance at the saturation point. Furthermore, to facilitate the design of the output matching circuit while achieving the target, a curve should be obtained to the left of the inductive region of the Smith chart, where the back-off point impedance is above the saturation point impedance, ensuring that the back-off point impedance is greater than the saturation point impedance. Therefore, as the power increases, the phase of the reflection coefficient should increase and the amplitude should decrease. To achieve this effect, based on the reflection coefficient amplitude formula mentioned earlier, if the amplitude of the reflection coefficient is to decrease, the ratio of the power of the control amplifier to the power of the balanced amplifier should be reduced. This can be achieved by saturating the control amplifier earlier. Thus, after the control amplifier is saturated, as long as the input power increases, the output power of the balanced amplifier increases while the output power of the control amplifier remains unchanged, and their ratio will decrease accordingly. If the phase of the reflection coefficient is to increase, α should decrease. This can also be achieved by saturating the control amplifier earlier.

[0078] Obviously, to achieve early saturation of the control amplifier, an unequal power divider and altered transistor bias are typically employed. As the theory above states, after the control amplifier saturates, the load impedance trajectory curve meets the high-efficiency requirement of the power back-off point. Therefore, the saturation point of the control amplifier is defined as the back-off point. In the back-off state, the gate bias and the divider stub length are repeatedly adjusted until the load impedance trajectory curve approximates the theoretical curve.

[0079] In addition, a phase-compensated microstrip line should be designed for two main purposes. Firstly, it can shift the load impedance trajectory curve to the left of the inductive region on the Smith chart. Secondly, it can achieve broadband matching. Based on the load pull results, it is known that the phase of the optimal load impedance lags as the frequency increases. Adding a phase-compensated microstrip line can adjust the phase difference between the two sides of the power divider and achieve a broadband effect. This is because the microstrip line's phase leads as the frequency increases, which can compensate for this mismatch caused by frequency offset. Here, the phase-compensated microstrip line should first be adjusted so that the load impedance trajectory curve is located to the left of the inductive region on the Smith chart.

[0080] Step 4: As mentioned above, the overall circuit output power should be the power input to the three ports of coupler2. However, due to power isolation at the coupler's isolation terminals, which is mainly caused by port reflections, the key to ensuring the coupler's input terminals can output the complete input signals from all three ports is to reduce port reflections. In practical design, this means matching the transistor's output impedance with the coupler's port impedances, which can be achieved by adding a pre-matching network. Therefore, after obtaining a relatively ideal load impedance trajectory curve, the back-off point impedance and saturation point impedance should be matched to their optimal values. Figure 4 This is a block diagram of the pre-matching network. The computational design process is given below:

[0081] Depend on Figure 4 Assume the lossless reciprocal impedance matrix of the pre-matched network:

[0082]

[0083] V b V is the output voltage of the balanced circuit transistor. b 'This refers to the output voltage of the balanced transistor after adding a dual-impedance pre-matching circuit.' b V is the output current of the balanced circuit transistor. b 'This refers to the output current of the balanced transistor after adding a dual-impedance pre-matching circuit.' 11 Z 12 Z 21 These are elements in the dual impedance pre-matched circuit matrix.

[0084] Obviously, Figure 4The saturation power of P2 as a transistor can be found in the datasheet. b This should be the optimal load impedance of the transistor. Based on the Z matrix in the above equation, we can obtain:

[0085]

[0086] Since the pre-matching network is costless and reciprocal, therefore:

[0087]

[0088] When the dual impedance pre-matching circuit is not applied, the output power of the balanced transistor is P1. Re(Z) b ) is Z b The real part.

[0089] Combining the above formulas, we get:

[0090]

[0091]

[0092] Among them, P sat P represents the saturated output power in the transistor datasheet. back This refers to the back-off output power from the transistor datasheet. The optimal impedances at the saturation point and back-off point are Z0 and Z0, respectively. sat and Z back ; α is I c with I b The ratio, with the added subscripts 'sat' and 'back' indicating its values ​​under saturation and back-off states. b To control the output current of the transistor, the added subscripts `sat` and `back` represent its values ​​in saturation and back-off states, respectively. As mentioned earlier, the power amplifier remains in saturation during the back-off interval, which can be approximated as I... csat and I cback If they are equal, solve Z using simultaneous equations. 11 Value:

[0093]

[0094] The optimal impedance Z at the saturation point and the retreat point sat and Z back The values ​​of saturation point and backoff point α can be obtained based on the load pull. Since a load impedance trajectory that is easy to match and conforms to the power backoff principle has already been fitted, the values ​​can be obtained from the current relationship explained in detail above. The saturation output power is obtained from the transistor datasheet. After determining the backoff interval, the backoff point output power can be obtained. Substituting all the values ​​into the above formula, Z can be finally determined. 11 The value of .

[0095] According to the theory mentioned above, I csat and I cback Equal, and the matching network does not affect I. c The value of I can be obtained through simulation without a matching network. c The value of Z, then... 11 and I c Substituting into the power calculation formula, Z can be determined. 12 The value of is thus determined, thus identifying three unknowns in the Z matrix. The remaining unknown can be freely determined based on design and computational simplicity. After obtaining the Z matrix of the network, it is then transformed into an ABCD matrix using the following formula:

[0096] A = Z 11 / Z 21

[0097] B = |Z| / Z 21

[0098] C = 1 / Z 21

[0099] D = Z 11 / Z 21

[0100] After obtaining the ABCD matrix of the dual impedance pre-matching network, the specific dimensions of each microstrip line in the matching network are synthesized using Richard transform, and then connected to the circuit.

[0101] Step 5: In the saturation state of the single-input broadband load modulated balanced amplifier, due to the premature saturation of the control power amplifier and the small conduction angle of the balanced power amplifier, the current waveform is severely distorted, hence the drain current I... d The fundamental component I dm The smaller the gain, the lower the power output to the load, resulting in low gain. To change this, a reconfigurable approach can be considered. In the saturation region, the conduction angle of the balanced power amplifier can be increased to improve the amplitude of the fundamental component in the drain current and increase the gain at the saturation point. Therefore, the gate bias should be repeatedly adjusted to optimize efficiency and gain. Since both transistors are located in the saturation region, the overall efficiency is still considerable.

[0102] Finally, the dimensions of the phase compensation microstrip line were repeatedly adjusted to achieve good performance of the circuit in the 3.4GHz-3.7GHz range.

[0103] Figure 5The figure shown is a simulation result of the design of this invention in ADS. The simulation results show that in the 3.4GHz-3.7GHz frequency band, the saturated output power is greater than 46dBm, the saturated output drain efficiency is greater than 75%, the drain efficiency is greater than 68% in the 8dB power back-off interval, and the power gain is in the range of 8-10dB. The results show that the function of a broadband single-input load modulated power amplifier has been realized.

[0104] The above description of the embodiments is merely for the purpose of helping to understand the method and core ideas of the present invention. It should be noted that those skilled in the art can make various improvements and modifications to the present invention without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of the present invention. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined in this application can be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention will not be limited to the embodiments shown in this application, but is to be accorded the widest scope consistent with the principles and novel features disclosed in this application.

Claims

1. A single input wideband load-modulated balanced amplifier characterized by The power distribution circuit, the phase compensation microstrip line and the two-way branch; the two-way branch includes a balance way and a control way, wherein the balance way includes a first 3-dB directional coupler circuit, a second 3-dB directional coupler circuit, an upper and lower two-way branch, the upper and lower two-way branch are the same in structure, each of which includes a wideband input matching circuit, a first RC stabilizing circuit, a transistor, a double impedance pre-matching circuit, the control way includes a control way wideband input matching circuit, a second RC stabilizing circuit, a transistor, a control way wideband output matching circuit; The power distribution circuit is used for distributing single input signal source power to the balance way and the control way; The phase compensation microstrip line L5 converts the load impedance locus to the optimal impedance position according to the design requirement; The first and second 3-dB directional couplers are respectively located behind the circuit input end and in front of the circuit output end to ensure the phase constancy of the upper and lower two-way branches in the balance way; The wideband input matching circuit is designed according to the optimal input impedance of the transistor in a wideband topology to maximize the signal power input to the transistor; The double impedance pre-matching circuit makes the load impedance trajectory in the power backoff interval coincide with the transistor optimal efficiency region and the maximum output power region; the double impedance pre-matching circuit comprises a parallel transmission line L6, a series transmission line L7, a parallel transmission line L8, a series transmission line L9 and a DC blocking capacitor C3; one end of the parallel transmission line L6 is connected with one end of the series transmission line L7 as an input end of the double impedance pre-matching circuit and connected with a drain of a transistor; the other end of the parallel transmission line L6 is connected with a drain bias V ds ; the other end of the series transmission line L7 is connected with one end of the parallel transmission line L8 and one end of the series transmission line L9; the other end of the parallel transmission line L8 is in an open circuit state; the other end of the series transmission line L9 is connected with one end of the DC blocking capacitor C3; the other end of the DC blocking capacitor C3 is connected with a port of a 3dB directional coupler.

2. A single input wideband load-modulated balanced amplifier as recited in claim 1, further characterized by The power distribution circuit includes parallel transmission lines L1, L2 and a resistor R1; one end of the parallel transmission line L1 is connected to one end of the parallel transmission line L2 to serve as the input of the single input wideband load modulation balance amplifier, the other end of the parallel transmission line L1 is connected to one end of the resistor R1 to serve as one output of the power distribution circuit; the other end of the parallel transmission line L2 is connected to the other end of the resistor R1 to serve as the other output of the power distribution circuit.

3. A single input wideband load-modulated balanced amplifier as recited in claim 1, wherein The first 3-dB directional coupler Coupler1 includes first, second, third and fourth parallel transmission lines L15-1, L16-1, L15-2 and L16-2; one end of the first parallel transmission line L15-1 is connected to one end of the first parallel transmission line L16-1 to serve as the input end of the first 3-dB directional coupler and is connected to the phase compensation microstrip line L5; the other end of the first parallel transmission line L15-1 is connected to one end of the second parallel transmission line L16-2 to serve as the through end of the first 3-dB directional coupler and is connected to the input end of the upper branch of the balance way; one end of the second parallel transmission line L15-2 is connected to the other end of the second parallel transmission line L16-2 to serve as the coupling end of the first 3-dB directional coupler and is connected to the input end of the lower branch of the balance way; the other end of the first parallel transmission line L16-1 is connected to the other end of the second parallel transmission line L15-2 to serve as the isolation end of the first 3-dB directional coupler and is connected to a standard 50Ω resistor for grounding.

4. A single input wideband load-modulated balanced amplifier as recited in claim 1, further characterized by The second 3-dB directional coupler Coupler2 includes fifth, sixth, seventh and eighth parallel transmission lines L17-1, L18-1, L17-2 and L18-2; one end of the fifth parallel transmission line L17-1 is connected to one end of the sixth parallel transmission line L18-1 to serve as the coupling end of the second 3-dB directional coupler and is connected to the output end of the upper branch of the balance way; The other end of the sixth parallel transmission line L18-1 is connected to one end of the seventh parallel transmission line L17-2 as a through end of the second 3-dB directional coupler, and is connected to the output end of the branch of the balanced path; The other end of the fifth parallel transmission line L17-1 is connected to one end of the eighth parallel transmission line L18-2 as an isolation end of the second 3-dB directional coupler, and is connected to the output end of the control path; the other end of the seventh parallel transmission line L17-2 is connected to the other end of the eighth parallel transmission line L18-2 as an input end of the second 3-dB directional coupler, and is connected to the circuit output end.

5. A single input wideband load-modulated balanced amplifier as recited in claim 1, further characterized by The wideband input matching circuit comprises a direct-current blocking capacitor C1, a series transmission line L3 and a series transmission line L4 connected in sequence; one end of the direct-current blocking capacitor C1 is an input end of the wideband input matching circuit, and the other end is connected to one end of the series transmission line L3; the other end of the series transmission line L3 is connected to one end of the series transmission line L4; and the other end of the series transmission line L4 is an output end of the wideband input matching circuit and is connected to an input end of the RC stabilizing circuit.

6. A method of designing a single-input wideband load-modulated balanced amplifier, characterized by The method comprises the following steps: Step one: design the first and second RC stabilizing circuits, and continuously adjust the values of the resistors and capacitors so that the stability parameters are greater than 1 in the full frequency band; Step two: determine the input and output impedances of the transistor; Step three: design the balanced path wideband input matching circuit, the control path wideband input matching circuit and the control path wideband output matching circuit according to the optimal input impedance of the transistor; Step four: debug the first and second 3-dB directional couplers so that the circuit bandwidth and performance are optimal; Step five: debug the power distribution circuit so that the circuit achieves power equalization and meets the wideband requirements; Step six: according to any one of claims 1-5, assemble the power distribution circuit, the first 3-dB directional coupler circuit, the second 3-dB directional coupler circuit, the balanced path wideband input matching circuit, the first RC stabilizing circuit, the balanced path transistor, the control path wideband input matching circuit, the second RC stabilizing circuit, the control path transistor, the control path wideband output matching circuit and the phase compensation microstrip line according to the single-input wideband load modulation balanced amplifier, and after the connection is completed, debug the power distribution circuit branch length, the bias of the control path and the balanced path transistor and the phase compensation microstrip line so that the control path transistor is saturated in advance, and in the debugging process, it should be ensured that the load impedance at the back-off point in the load impedance trajectory is greater than the load impedance at the saturation point and the load impedance trajectory curve is close to the inductive region of the Smith chart; Step seven: design a double-impedance pre-matching network that can match the port impedance of the second 3-dB directional coupler to the optimal impedances at the saturation point and the back-off point of the balanced path transistor; according to the current-voltage and impedance relationship, the impedance matrix of the double-impedance pre-matching network is derived, and then the double-impedance pre-matching network is synthesized; The port impedance of the second 3-dB directional coupler is matched to the optimal impedances at the saturation point and the back-off point of the balanced path transistor through the double-impedance pre-matching circuit; specifically as follows: The lossless reciprocal impedance matrix Z of the double-impedance pre-matching circuit: where V b is the output voltage of the balanced transistor, V b ′ is the output voltage of the balanced transistor with the double impedance pre-match circuit, I b is the output current of the balanced transistor, I b ′ is the output current of the balanced transistor with the double impedance pre-match circuit, Z 11 , Z 12 , Z 21 are elements in the Z matrix of the double impedance pre-match circuit. According to the Z matrix in formula (1), we can get: wherein Z b is the optimal load impedance of the balancing transistor; Since the double-impedance pre-matching circuit is lossless and reciprocal, we have: Where P1 is the output power of the balanced transistor when the dual impedance pre-matching circuit is not applied, Re(Z) b ) is Z b The real part of P2 is the saturated output power of the balanced circuit transistor, which can be found in the datasheet. Step eight, the above-mentioned double impedance pre-matching network is connected to the circuit in step six, and the adjustment is repeated until the overall performance of the amplifier is optimal.

7. The method of claim 6, wherein The adjustment process for making the control path transistor saturated in advance in step six is as follows: Keeping the output power of the control path unchanged, the output power of the balance path is increased with the increase of the input power; at the same time, the length of the power distribution circuit branch is adjusted, so that the input power of the control path is slightly high or the gate bias voltage of the balance path transistor is reduced, thereby making the control path transistor work in class B working state and the balance path transistor work in class C working state.

8. The method of claim 6, wherein The adjustment process for making the load impedance trajectory curve close to the inductive region of the Smith chart in the load impedance trajectory in step six is as follows: According to the load traction result, it is found that the phase of the optimal load impedance will lag when the frequency is increased. The phase compensation microstrip line is adjusted to adjust the phase difference on both sides of the power distribution circuit and achieve a wideband effect, and the phase compensation microstrip line is adjusted to the left side of the load impedance trajectory curve in the inductive region of the Smith chart.

9. The method of claim 6, wherein The impedance matrix of the double impedance pre-matching network is derived according to the current-voltage and impedance series in step seven, and the double impedance pre-matching network is synthesized as follows: According to formula (3), the transistor saturation output power and the backoff output power determine the Z 11 , Z 12 , Z 21 , and then the double-impedance pre-matching circuit Z matrix is converted into an ABCD matrix, and then the topology and transmission line specific values of the double-impedance pre-matching network are synthesized.

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