Ultra-low power por circuit and integrated circuit device

Abstract

The application provides a kind of ultra-low power consumption POR circuit and integrated circuit equipment, comprising: power-on detection circuit, pulse expansion circuit, pulse latching circuit, power-down detection circuit and output buffer circuit;The power-on detection circuit is connected with pulse expansion circuit, the pulse expansion circuit is connected with pulse latching circuit, and the pulse latching circuit is connected with power-on detection circuit and buffer circuit respectively, and the power-down detection circuit is connected with pulse latching circuit.The POR circuit of the application completes power-on detection, generates POR signal, and turns off the power-on detection module to reduce the static power consumption of the circuit, and realizes extremely low power consumption.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of POR circuit, in particular, to an ultra-low power POR circuit and integrated circuit device. BACKGROUND

[0002] Power on reset circuit (POR circuit) is mostly used in digital and mixed signal integrated circuits. When the power is on in analog and digital circuits, the voltage and logic level of each functional module and circuit node in the chip are in an unknown state. Running the chip from this uncertain unknown state may cause the system to run incorrectly, and even affect the entire chip. In order to understand the power-on and power-off of the power supply in the circuit and make the circuit work in a certain expected state, a signal that can detect the power supply in time is needed. Generally, when the power voltage rises to a certain trigger voltage, the POR circuit will generate a digital reset signal. This signal is used to initialize each node in the analog and digital circuits, so that the circuit works in a preset state.

[0003] Many POR circuits use a scheme with reference and hysteresis comparator to generate a reset signal, which can avoid the interference of temperature and power supply voltage on the signal. However, due to the introduction of reference and comparator modules, the power consumption and chip area also increase. For low-power application scenarios, this scheme is obviously not desirable.

[0004] After the power supply is powered on, the POR circuit will give a reset signal to the digital and analog circuits, so that the circuit works in a preset state. However, the power supply after power-on will still be disturbed by the outside world, and there will be a situation of unstable power supply voltage. The jitter of the power supply voltage within a certain range has little effect on the system, so the POR circuit is not enabled. However, once the power supply voltage drops by more than the normal working range of the circuit, the POR circuit needs to have a power-off detection function in addition to the power-on reset function. The design difficulty of the power-off detection circuit lies in how to detect the time when the power supply voltage starts to drop.

[0005] In low-power applications, the low-power design of the POR circuit is very important. The POR circuit using the reference and comparator scheme has a circuit complexity, and the power consumption is basically in the uA level, which is not suitable for low-power application scenarios. SUMMARY

[0006] In view of the defects in the prior art, the purpose of the present application is to provide an ultra-low power POR circuit and integrated circuit device.

[0007] According to the ultra-low power POR circuit provided by the present application, the power-on detection circuit, the pulse expansion circuit, the pulse latching circuit, the power-off detection circuit and the output buffer circuit are included.

[0008] The power-on detection circuit is connected with a pulse stretching circuit, the pulse stretching circuit is connected with a pulse latching circuit, the pulse latching circuit is connected with the power-on detection circuit and the buffer circuit respectively, and the power-off detection circuit is connected with the pulse latching circuit.

[0009] Preferably, the power-on detection circuit comprises a PMOS tube P1, a resistor R1, a resistor R2, an inverter U1 and an inverter U2; the source of the PMOS tube P1 is connected with VDD, the drain of the PMOS tube P1 is connected with one end of the resistor R1, the other end of the resistor R1 is connected with one end of the resistor R2 and the input end of the inverter U1 respectively, and the other end of the resistor R2 is grounded; the output end of the inverter U1 is connected with the input end of the inverter U2, and the output end of the inverter U2 is connected with the pulse stretching circuit.

[0010] Preferably, the pulse stretching circuit comprises an inverter U3 and an inverter U4; the input end of the inverter U3 is connected with the output end of the inverter U2, the output end of the inverter U3 is connected with the input end of the inverter U4, and the output end of the inverter U4 is connected with the pulse latching circuit.

[0011] Preferably, the pulse latching circuit comprises a MOS tube Q1, a MOS tube Q2, an inverter U5, an inverter U6, an inverter U7, an inverter U8, an inverter U9, an inverter U10 and an NMOS tube N1; the drain of the MOS tube Q1 and the drain of the MOS tube Q2 are connected with the output end of the inverter U4, the gate of the MOS tube Q1 is connected with the output end of the inverter U5, the source of the MOS tube Q1 and the source of the MOS tube Q2 are connected with the source of the NMOS tube N1 and the input end of the inverter U7 respectively, the gate of the MOS tube Q2 is connected with the input end of the inverter U5 and the output end of the inverter U6 respectively, the output end of the inverter U7 is connected with the input end of the inverter U10, the output end of the inverter U9 and the input end of the inverter U8 respectively, the output end of the inverter U8 is connected with the input end of the inverter U6, the output end of the inverter U10 is connected with the input end of the inverter U9, the gate of the NMOS tube N1 and the gate of the PMOS tube P1, and the drain of the NMOS tube N1 is connected with VDD.

[0012] Preferably, the output buffer circuit comprises a buffer, and the input end of the buffer is connected with the output end of the inverter U10.

[0013] Preferably, the power-off detection circuit comprises: a PMOS tube P2, an NMOS tube N2, a MOS tube Q3, a MOS tube Q4, a PMOS tube P3, an NMOS tube N3 and an NMOS tube N4; the source of the PMOS tube P2 is connected with VDD; the drain of the PMOS tube P2 is connected with the gate of the PMOS tube P2, the gate of the NMOS tube N2, the source of the MOS tube Q3 and the source of the PMOS tube P3 respectively; the source of the NMOS tube N2 and the drain of the NMOS tube N2 and the source of the MOS tube Q4 are connected and grounded; the gate of the MOS tube Q3 is connected with the gate of the MOS tube Q4 and then connected with VDD; the drain of the MOS tube Q3 and the drain of the MOS tube Q4 are connected and then connected with the gate of the NMOS tube N3 and the gate of the NMOS tube N4 respectively; the source of the NMOS tube N3 and the source of the NMOS tube N4 are connected and grounded; the drain of the NMOS tube N3 is connected with the input end of an inverter U7; the drain of the NMOS tube N4 is connected with the output end of an inverter U10; the gate of the PMOS tube P3 is connected with VDD; and the drain of the PMOS tube P3 is connected with the input end of the inverter U10.

[0014] The application provides an integrated circuit device comprising the super-low-power POR circuit.

[0015] Compared with the prior art, the application has the following beneficial effects:

[0016] 1. In the application, the power-off detection circuit adopts the structure of MOS capacitor and diode connection to realize charge storage. The diode-connected transistor ensures unidirectionality and prevents charge leakage. When the power voltage starts to drop, the voltage on the MOS capacitor remains unchanged. The voltage and the power voltage serve as the gate-source voltage to drive the P-type transistor. When the power voltage drops, the pressure difference generated turns on the transistor, thereby generating a step signal. The power-off detection function can ensure that the system receives the power-off signal in time when the power supply is accidentally powered off, and shuts down the related modules to ensure the safe operation of the system.

[0017] 2. When the POR circuit completes the power-on detection and generates the POR signal, the power-on detection module is shut down to reduce the static power consumption of the circuit and achieve extremely low power consumption. BRIEF DESCRIPTION OF DRAWINGS

[0018] Other features, objects and advantages of the application will become more apparent from the following detailed description of non-limiting embodiments with reference to the attached drawings:

[0019] Figure 1 The application provides a super-low-power POR circuit composition framework diagram;

[0020] Figure 2 The application provides a super-low-power POR circuit connection schematic diagram. DETAILED DESCRIPTION

[0021] The application will be described in detail below with specific examples. The following examples will help those skilled in the art to further understand the application, but do not limit the application in any form. It should be noted that those skilled in the art can make several changes and improvements without departing from the concept of the application. These are within the scope of protection of the application.

[0022] The application discloses a kind of ultra-low power POR circuit, refer to Figure 1 And Figure 2 Including: power-on detection circuit, pulse expansion circuit, pulse latching circuit, power-down detection circuit and output buffer circuit.

[0023] The power-on detection circuit is connected with pulse expansion circuit, the pulse expansion circuit is connected with pulse latching circuit, and the pulse latching circuit is connected with power-on detection circuit and buffer circuit respectively, and the power-down detection circuit is connected with pulse latching circuit.

[0024] The circuits will be described in detail below.

[0025] The power-on detection circuit includes PMOS tube P1, resistance R1, resistance R2, inverter U1 and inverter U2;The source of PMOS tube P1 is connected with VDD, the drain of PMOS tube P1 is connected with one end of resistance R1, the other end of resistance R1 is connected with one end of resistance R2 and the input end of inverter U1 respectively, and the other end of resistance R2 is grounded;The output end of inverter U1 is connected with the input end of inverter U2, and the output end of inverter U2 is connected with pulse expansion circuit.

[0026] Figure 2 The block 1 in the figure is power-on detection circuit. In initial state, the voltage of each node in the circuit is zero. Therefore, when the power supply voltage starts to power on, the gate voltage of PMOS tube P1 is zero. When the power supply voltage rises to the threshold voltage of PMOS tube P1, PMOS tube P1 is turned on, and the current generated on the resistance produces a voltage drop. When the voltage at point A reaches the flip threshold of the inverter, the output voltage of the first stage inverter, i.e. inverter U1 and inverter U2, changes from following the power supply voltage to low voltage.

[0027] The pulse expansion circuit includes inverter U3 and inverter U4;The input end of inverter U3 is connected with the output end of inverter U2, the output end of inverter U3 is connected with the input end of inverter U4, and the output end of inverter U4 is connected with pulse latching circuit.

[0028] Figure 2The block 2 in the figure is a pulse stretching circuit. The delay time of the circuit can be designed according to the application scene requirement to meet the width requirement of the POR reset signal of the system.

[0029] The pulse latching circuit comprises MOS Q1, MOS Q2, inverter U5, inverter U6, inverter U7, inverter U8, inverter U9, inverter U10 and NMOS N1. The drain of the MOS Q1 and the drain of the MOS Q2 are connected and connected to the output of the inverter U4. The gate of the MOS Q1 is connected to the output of the inverter U5. The source of the MOS Q1 and the source of the MOS Q2 are connected and connected to the source of the NMOS N1 and the input of the inverter U7 respectively. The gate of the MOS Q2 is connected to the input of the inverter U5 and the output of the inverter U6 respectively. The output of the inverter U7 is connected to the input of the inverter U10, the output of the inverter U9 and the input of the inverter U8 respectively. The output of the inverter U8 is connected to the input of the inverter U6. The output of the inverter U10 is connected to the input of the inverter U9, the gate of the NMOS N1 and the gate of the PMOS P1. The drain of the NMOS N1 is connected to VDD.

[0030] Figure 2 The block 3 in the figure is a pulse latching circuit. The circuit not only contains the pulse latching function, but also the voltage at D and E controls the switch of the PMOS P1 of the power-on detection circuit and the switch of the transmission gate between B and C respectively. When the power-on detection circuit detects the preset trigger voltage, the PMOS P1 and the transmission gate are turned off, and the power-on detection function is disabled to reduce the static power consumption.

[0031] The output buffer circuit comprises a buffer, and the input of the buffer is connected to the output of the inverter U10. Figure 2 The block 4 in the figure is an output buffer circuit.

[0032] The power-off detection circuit comprises: PMOS tube P2, NMOS tube N2, MOS tube Q3, MOS tube Q4, PMOS tube P3, NMOS tube N3 and NMOS tube N4; the source of the PMOS tube P2 is connected with VDD, the drain of the PMOS tube P2 is connected with the gate of the PMOS tube P2, the gate of the NMOS tube N2, the source of the MOS tube Q3 and the source of the PMOS tube P3 respectively, the source of the NMOS tube N2 and the drain of the NMOS tube N2 and the source of the MOS tube Q4 are connected and grounded, the gate of the MOS tube Q3 is connected with the gate of the MOS tube Q4 and then connected with VDD, the drain of the MOS tube Q3 is connected with the drain of the MOS tube Q4 and then connected with the gate of the NMOS tube N3 and the gate of the NMOS tube N4 respectively, the source of the NMOS tube N3 is connected with the source of the NMOS tube N4 and then grounded, the drain of the NMOS tube N3 is connected with the input end of the inverter U7, the drain of the NMOS tube N4 is connected with the output end of the inverter U10, the gate of the PMOS tube P3 is connected with VDD, and the drain of the PMOS tube P3 is connected with the input end of the inverter U10.

[0033] In Figure 2 the block 5 is a power-off detection circuit. The NMOS tube N2 is connected as a capacitor, and the PMOS tube P2 is a diode-connected MOS tube. When the power supply voltage is powered on, the capacitor is charged through the PMOS tube P2, so that the voltage at point F reaches the maximum value of the power supply voltage. Since the PMOS tube P2 has unidirectionality, the charge on the NMOS tube N2 capacitor will not leak. When the power supply voltage is powered off, the voltage at point F continues to maintain around the maximum value of the power supply voltage, and the power supply voltage connected to the gate of the PMOS tube P3 is continuously decreasing. When the voltage decreases to a threshold voltage different from the voltage at point E, the PMOS tube P3 is turned on. A high voltage appears at the drain of the PMOS tube P3, i.e. at point D. Therefore, the output of the POR circuit changes from high to low due to the power-off of the power supply voltage.

[0034] The working principle of the ultra-low power consumption POR circuit disclosed by the application is as follows: when the circuit is powered on, the power-on detection circuit works, and when it is detected that the power supply voltage reaches the trigger voltage, the power-on detection circuit outputs a step signal from low to high. The signal passes through a delay circuit and a transmission gate, and is kept at a high level at E. The level turns off the PMOS tube P1 in the power-on monitoring circuit, and then the output of the power-on detection circuit is from high to low, forming a positive pulse. After passing through a pulse widening circuit, a POR pulse width meeting the system requirements is generated. When the power supply voltage is powered off due to external interference, the power-off detection circuit starts to work and generates a step signal from low to high at point D. Through subsequent inverters and buffers, a step signal from high to low is generated at the output of the POR circuit.

[0035] The application further discloses an integrated circuit device comprising the super low power POR circuit.

[0036] In the description of the present application, it should be understood that the terms "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship shown in the drawings based on the orientation or positional relationship shown in the drawings, and are only for the purpose of facilitating the description of the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application.

[0037] The specific embodiments of the present application are described above. It should be understood that the present application is not limited to the specific embodiments described above, and various changes or modifications can be made by those skilled in the art within the scope of the claims, which does not affect the essential content of the present application. The embodiments of the present application and the features in the embodiments can be arbitrarily combined with each other without conflict.

Claims

1. An ultra-low power consumption POR circuit, characterized in that: include: Power-on detection circuit, pulse stretching circuit, pulse latch circuit, power-off detection circuit and output buffer circuit; The power-on detection circuit is connected to the pulse stretching circuit, the pulse stretching circuit is connected to the pulse latch circuit, the pulse latch circuit is connected to the power-on detection circuit and the buffer circuit respectively, and the power-off detection circuit is connected to the pulse latch circuit; The power-on detection circuit includes: a PMOS tube P1, a resistor R1, a resistor R2, an inverter U1 and an inverter U2; The source of the PMOS transistor P1 is connected to VDD, the drain of the PMOS transistor P1 is connected to one end of the resistor R1, the other end of the resistor R1 is respectively connected to one end of the resistor R2 and the input end of the inverter U1, and the other end of the resistor R2 is grounded; the output end of the inverter U1 is connected to the input end of the inverter U2, and the output end of the inverter U2 is connected to the pulse stretching circuit; The pulse stretching circuit includes an inverter U3 and an inverter U4; the input end of the inverter U3 is connected to the output end of the inverter U2, the output end of the inverter U3 is connected to the input end of the inverter U4, and the output end of the inverter U4 is connected to the pulse latch circuit; The pulse latch circuit includes a MOS transistor Q1, a MOS transistor Q2, an inverter U5, an inverter U6, an inverter U7, an inverter U8, an inverter U9, an inverter U10 and an NMOS transistor N1; the drain of the MOS transistor Q1 is connected to the drain of the MOS transistor Q2 and then connected to the output end of the inverter U4; the gate of the MOS transistor Q1 is connected to the output end of the inverter U5; the source of the MOS transistor Q1 is connected to the source of the MOS transistor Q2 and then connected to the source of the NMOS transistor N1 and the gate of the inverter U7. The gate of the MOS tube Q2 is connected to the input end of the inverter U5 and the output end of the inverter U6 respectively. The output end of the inverter U7 is connected to the input end of the inverter U10, the output end of the inverter U9 and the input end of the inverter U8 respectively. The output end of the inverter U8 is connected to the input end of the inverter U6. The output end of the inverter U10 is connected to the input end of the inverter U9, the gate of the NMOS tube N1 and the gate of the PMOS tube P1. The drain of the NMOS tube N1 is connected to VDD.

2. The ultra-low power consumption POR circuit according to claim 1, wherein: The output buffer circuit includes a buffer, and an input end of the buffer is connected to the output end of the inverter U10.

3. The ultra-low power consumption POR circuit according to claim 1, wherein: The power-off detection circuit includes: a PMOS transistor P2, an NMOS transistor N2, a MOS transistor Q3, a MOS transistor Q4, a PMOS transistor P3, an NMOS transistor N3 and an NMOS transistor N4; the source of the PMOS transistor P2 is connected to VDD, the drain of the PMOS transistor P2 is respectively connected to the gate of the PMOS transistor P2, the gate of the NMOS transistor N2, the source of the MOS transistor Q3 and the source of the PMOS transistor P3, the source of the NMOS transistor N2, the drain of the NMOS transistor N2 and the source of the MOS transistor Q4 are connected and then grounded, and the MOS transistor Q3 is connected. The gate of the MOS transistor Q3 is connected to the gate of the MOS transistor Q4 and then connected to VDD. The drain of the MOS transistor Q3 is connected to the drain of the MOS transistor Q4 and then connected to the gate of the NMOS transistor N3 and the gate of the NMOS transistor N4 respectively. The source of the NMOS transistor N3 is connected to the source of the NMOS transistor N4 and then grounded. The drain of the NMOS transistor N3 is connected to the input end of the inverter U7. The drain of the NMOS transistor N4 is connected to the output end of the inverter U10. The gate of the PMOS transistor P3 is connected to VDD. The drain of the PMOS transistor P3 is connected to the input end of the inverter U10.

4. An integrated circuit device, characterized in that: The invention comprises the ultra-low power consumption POR circuit according to any one of claims 1 to 3.

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