A power supply timing control circuit

Abstract

The application belongs to the technical field of power timing control, and particularly relates to a power timing control circuit. The power of the current stage is connected to a window detector, and the high and low levels of the window detector are set as the maximum and minimum values of the normal range of the power of the current stage. When the window detector detects that the power of the current stage is within the high and low levels, i.e. the normal value, a high level is output, the power of the next stage is enabled by the power chip of the next stage, and the load power supply switch circuit of the current stage is closed, so that the power of the current stage is supplied to the load. When the window detector detects that the power of the current stage is outside the high and low levels, i.e. the abnormal value, a low level is output, the power of the next stage is not enabled by the power chip of the next stage, the power of the next stage is not generated, the load power supply switch circuit of the current stage is disconnected, and the load is not supplied with power.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of power supply timing control, and particularly relates to a power supply timing control circuit. BACKGROUND

[0002] At present, in the design of electronic products, the functions and design of products are more and more complex, the circuit integration is higher and higher, and the power consumption is increased. In most cases, the main control controller needs to provide multiple different power supplies and needs to follow a certain timing. For example, the power supply types required by a ZYNQ chip are 1V, 1.8V, 1.5V and 3.3V, and the power-on sequence must also be 1V-1.8V-1.5V-3.3V, and the delay between them also has certain requirements. At present, the power-on sequence control of the power supply mainly has the following three methods:

[0003] 1) The output of the programmable logic device drives the enable end of the power supply chip. This method can realize controllable delay between power supplies and has high freedom, but the programmable logic device belongs to the main controller, and the power supply of the programmable logic device has not been controlled in sequence, so it cannot be started and cannot output the enable signal of the power supply.

[0004] 2) Most of the power supply chips used at present have a power output indication pin (PG) and an enable pin (EN). The PG of the previous stage power supply chip is connected with the EN of the next stage power supply chip. The PG is generally an open drain output. When the output of the power supply chip reaches 90% or more of the nominal output voltage, the PG outputs a high impedance state, and in other cases, it outputs a low level. When the output of the current stage power supply chip reaches 95%, the PG is high level through an external pull-up resistor, so as to drive the EN of the next stage power supply chip, so that the next stage power supply chip starts to work. If the output of the previous stage power supply does not reach 95%, the PG outputs a low level, and the next stage power supply chip does not work. This control method is not suitable for the case where the output voltage is low, because the output voltage of the power supply is relatively low, and a slight fluctuation will trigger the threshold of the PG, so the quality requirement of the power supply is high.

[0005] 3) Directly use the output of the previous stage to connect the enable end of the next stage power supply chip, as shown in the attached Figure 1 : The previous stage power supply 1 is connected with the enable end of the next stage power supply 2 through the attached Figure 1The resistance voltage division in the window detection sub-circuit makes the transistor conduct, thereby driving the enable end of the next-stage power supply chip, but two problems exist: a. When V1 is small, the voltage drop of the transistor also makes the output of the transistor, i.e. the voltage of the enable end of the power supply chip, small, which is likely to be less than the enable threshold, resulting in that the next-stage power V2 is not generated; b. Since V1 and V2 are generated by the power supply chip, the voltage output of the power supply chip is divided by two resistors and compared with the internal reference to form a feedback loop, if the resistors are damaged, the output voltage of the power supply chip will directly rise to a large value, which will damage the subsequent power supply chip and the main control chip supplied by V1. SUMMARY

[0006] The present application aims at:

[0007] The present application proposes a power sequence control circuit, which realizes that the subsequent power supply chip only functions when the voltage of the previous stage is within a reasonable range, and generates the subsequent power supply, while the current power supply functions on the load; when in an abnormal value range, the subsequent power supply chip does not start, and the subsequent power supply is not generated, while the current abnormal power supply does not function on the load, which ensures safety and reliability.

[0008] The technical scheme adopted by the present application to solve the technical problems is:

[0009] A power sequence control circuit, which is arranged between two-stage power supplies; the circuit comprises: a window detection sub-circuit and a load power supply switch sub-circuit.

[0010] The input end of the window detection sub-circuit is connected to the output end of the previous-stage power supply, the output end of the window detection sub-circuit is connected to the input end of the load power supply switch sub-circuit, and the output end of the load power supply switch sub-circuit is connected to the previous-stage load.

[0011] The output end of the window detection sub-circuit is also connected to the enable end of the subsequent power supply.

[0012] Further, the window detection sub-circuit comprises: a first comparator U1, a second comparator U2, a resistor R1, an upper limit constant voltage source VIH, and a lower limit constant voltage source VIL.

[0013] The output voltage of the upper limit constant voltage source VIH is the upper limit value of the fluctuation of the output end of the previous-stage power supply, and the output voltage of the lower limit constant voltage source VIL is the lower limit value of the fluctuation of the output end of the previous-stage power supply.

[0014] The positive input end of the first comparator U1 is connected to the upper limit constant voltage source VIH, and the negative input end of the first comparator is connected to the output end of the previous-stage power supply.

[0015] The positive input end of the second comparator U2 is connected to the negative input end of the first comparator, and the negative input end of the second comparator is connected to the lower limit constant voltage source VIL.

[0016] The output ends of the first comparator U1 and the second comparator U2 are interconnected as the output end of the window detection sub-circuit; the output end of the window detection sub-circuit is further pulled up to the upper limit constant voltage source VIH through the resistor R1.

[0017] Further, the load power supply switch sub-circuit comprises a transistor Q1 and a resistor R2.

[0018] The base of the transistor Q1 is connected to the output end of the window detection sub-circuit, the collector is connected to the output end of the front-stage power supply, the emitter is grounded through the resistor R2, and the emitter is further connected to the front-stage load as the output end of the load power supply switch sub-circuit.

[0019] Further, the enable sub-circuit comprises a voltage monitoring chip, a capacitor C1 and a resistor R3.

[0020] The threshold comparison end of the voltage monitoring chip is connected to the output end of the window detection sub-circuit, the power supply end is connected to a primary power supply, the ground end is grounded, and the output end is connected to the enable end of the rear-stage power supply after being pulled up to the upper limit constant voltage source VIH through the resistor R3.

[0021] The delay end of the voltage monitoring chip is grounded through the capacitor C1, and the delay of the output end of the voltage monitoring chip is adjusted by adjusting the capacitance of the capacitor C1.

[0022] Further, the enable sub-circuit further comprises a capacitor C2, and the power supply end of the voltage monitoring chip is grounded through the capacitor C2.

[0023] Further, the upper limit constant voltage source VIH is composed of a primary power supply, a resistor R4 and a stabilizing diode D1.

[0024] One end of the resistor R4 is connected to the primary power supply, the other end is connected to the cathode of the stabilizing diode D1, the anode of the stabilizing diode D1 is grounded, and the cathode of the stabilizing diode D1 is the output end of the upper limit constant voltage source VIH.

[0025] The lower limit constant voltage source VIL is composed of a primary power supply, a resistor R5 and a stabilizing diode D2.

[0026] One end of the resistor R5 is connected to the primary power supply, the other end is connected to the cathode of the stabilizing diode D2, the anode of the stabilizing diode D2 is grounded, and the cathode of the stabilizing diode D2 is the output end of the lower limit constant voltage source VIL.

[0027] Beneficial effects:

[0028] This invention has two major advantages: when the nominal value of the power supply is very small, the actual value of the power supply is within the normal range and can drive the subsequent power supply, while controlling the load power supply switch of this stage to close and supply power to the load; when the power supply of this stage is particularly large or particularly small and is within the abnormal range, it cannot drive the subsequent power supply chip to turn on and output the subsequent power supply, while controlling the load power supply switch of this stage to disconnect and supply power to the load. Attached Figure Description

[0029] Figure 1 This is a schematic diagram of a power supply timing control circuit;

[0030] Figure 2 This is a schematic diagram of the power supply timing control circuit of the present invention;

[0031] Figure 3 This is a schematic diagram of Example 1;

[0032] Figure 4 This is a schematic diagram of Example 2. Detailed Implementation

[0033] A power supply timing control circuit connects the current power supply to a window detector, and sets the high and low levels of the window detector to represent the maximum and minimum values ​​within the normal range of the current power supply. When the voltage range of the current power supply is within the high and low levels of the window detector, the window detector outputs an open-drain output; when the voltage range is outside the high and low levels, it outputs a low level. The output of the window detector is connected to three points: 1. pulled up to the detector high level through a pull-up resistor; 2. connected to the enable terminal of the subsequent power supply chip; 3. connected to the input of the load power supply switching circuit of the current power supply. When the window detector detects that the current power supply is within the high and low levels (normal value), it outputs a high level, the subsequent power supply chip is enabled, and the load power supply switching circuit of the current power supply closes, supplying power to the load. When the window detector detects that the current power supply is outside the high and low levels (abnormal value), it outputs a low level, the subsequent power supply chip is disabled, the subsequent power supply is not generated, the load power supply switching circuit of the current power supply opens, and the load is not supplied with power.

[0034] like Figure 2 The diagram shows a power supply timing control circuit framework of the present invention, specifically including a window detector, a local load power supply switch circuit, and a subsequent power supply enable circuit. The window detector mainly detects the local input power supply VI, and its output is connected to the subsequent enable circuit to control the power supply of the subsequent stage; at the same time, it is connected to the input of the local load power supply switch circuit to control the power supply of the local load.

[0035] Example 1

[0036] like Figure 3As shown, the window detector includes comparators U1 and U2. U1 and U2 each have four pins: a non-inverting input, an inverting input, a positive power supply pin, and a negative power supply pin. The non-inverting input of U1 is connected to VIH, which is the maximum value of the normal voltage of VI, the inverting input of U1 is connected to VI and the non-inverting input of U2, the inverting input of U2 is connected to VIL, which is the minimum value of the normal voltage of VI, and the output of U1 is pulled up to VIH through R1.

[0037] The post-stage power supply enabling circuit is U3, the enabling end of U3 is connected to the output of the window detector, and the output of U3 is connected to the input of the post-stage power supply.

[0038] The current-stage load power supply switching circuit includes a transistor Q1 and R2. The base of Q1 is connected to the output of the window detector and the enabling end of the power supply enabling circuit, the collector of Q1 is connected to the current-stage input power supply VI, and the emitter of Q1 is pulled down to ground through R2 and is connected to the current-stage load.

[0039] Working principle:

[0040] The maximum value VIH and the minimum value VIL of the normal range of the current-stage power supply are generated by the voltage stabilizing circuit, VI is input to the window detector, when VI < VIL or VI > VIH, the window detector outputs a low level, the low level does not enable the enabling end of the post-stage power supply chip, the post-stage power supply cannot be generated, and at the same time, since Ube of the transistor is less than 0.7V, the transistor is not turned on, the current-stage VI power supply cannot output power to the current-stage load, i.e., the main controller; when VIL < VI < VIH, the window detector outputs an open drain, which is connected to VIH through a pull-up resistor, the output high level is VIH, VIH can enable the enabling end of the power supply chip to generate the next-stage power supply, and at the same time, VIH > VI, which can make the transistor Q1 saturated and turned on, the voltage drop of UCE will be very small, and VI outputs power to the current-stage load, i.e., the main controller.

[0041] Embodiment two

[0042] Attachment Figure 4 Embodiment two is an extension of embodiment one, and uses an optocoupler to replace the operational amplifier to make the window detector. Since the input impedance of the operational amplifier is nearly infinite, the current flowing into the operational amplifier is very small, and only voltage is needed, which belongs to a voltage-controlled device. As long as VI is between VIL and VIH, the rear-end circuit will be turned on. Even if VI is only the coupling voltage, not the real voltage output by the front-stage power supply. By using the optocoupler, VI must meet two conditions of voltage and current, the coupling interference voltage, and no current driving capability. The window detector does not work, and the mis-opening of the lower voltage due to the mis-coupling voltage is avoided.

[0043] When the window detector detects that the voltage is between the maximum VIH and VIL, the open-drain output is pulled up to VIH by the external pull-up resistor R1, VIH > the threshold value of the voltage monitoring chip U5, and the CT end capacitor C1 is fully charged, then the output will be open-drain output, pulled up to 5V under the action of pull-up resistor R3, and the output is connected to the enable end of the lower power supply chip at the same time, so that the lower power supply chip outputs power. When the capacitor C1 is not fully charged, even if VIL

Claims

1. A power supply timing control circuit, characterized by: The circuit is arranged between two-pole power supply; the circuit comprises: window detection sub-circuit and load power supply switch sub-circuit; The window detection sub-circuit input end is connected with the output end of the former stage power supply, the window detection sub-circuit output end is connected with the input end of the load power supply switch sub-circuit, and the load power supply switch sub-circuit output end is connected with the former stage load; The window detection sub-circuit output end is also connected with the latter stage power supply enable end; The window detection sub-circuit comprises: first photoelectric coupler U3, second photoelectric coupler U4, resistance R1, upper limit constant voltage source VIH and lower limit constant voltage source VIL; The output voltage of the upper limit constant voltage source VIH is the upper limit value of the fluctuation of the output end of the former stage power supply, and the output voltage of the lower limit constant voltage source VIL is the lower limit value of the fluctuation of the output end of the former stage power supply; The anode of the input end of the first photoelectric coupler U3 is connected with the upper limit constant voltage source VIH, the cathode of the input end of the second photoelectric coupler U4 is connected with the lower limit constant voltage source VIL, the cathode of the input end of the first photoelectric coupler U3 is connected with the anode of the input end of the second photoelectric coupler and the output end of the former stage power supply; The emitter of the output end of the first photoelectric coupler U3 is interconnected with the emitter of the output end of the second photoelectric coupler U4 and grounded after being pulled up to the upper limit constant voltage source VIH through the resistance R1, and the collector of the output end of the first photoelectric coupler U3 is interconnected with the collector of the output end of the second photoelectric coupler U4 and pulled up to the upper limit constant voltage source VIH through the resistance R1; The load power supply switch sub-circuit comprises: triode Q1 and resistance R2; the base of the triode Q1 is connected with the output end of the window detection sub-circuit, the collector is connected with the output end of the former stage power supply, the emitter is grounded through the resistance R2, and the emitter is also connected with the former stage load as the output end of the load power supply switch sub-circuit.

2. The power timing control circuit of claim 1, wherein: The circuit further comprises: an enable sub-circuit arranged between the output end of the window detection sub-circuit and the latter stage power supply enable end.

3. The power timing control circuit of claim 2, wherein: The enable sub-circuit comprises: voltage monitoring chip, capacitor C1 and resistance R3; The threshold comparison end of the voltage monitoring chip is connected with the output end of the window detection sub-circuit, the power supply end is connected with the primary power supply, the grounding end is grounded, and the output end is connected with the latter stage power supply enable end after being pulled up to the upper limit constant voltage source VIH through the resistance R3; The delay end of the voltage monitoring chip is grounded through the capacitor C1, and the capacitor C1 value is adjusted to adjust the delay of the output end of the voltage monitoring chip.

4. The power timing control circuit of claim 3, wherein: The enable sub-circuit further comprises: capacitor C2, and the power supply end of the voltage monitoring chip is grounded through the capacitor C2.

5. The power timing control circuit of claim 4, wherein: The upper limit constant voltage source VIH is composed of the primary power supply, resistance R4 and stabilizing diode D1; One end of the resistance R4 is connected with the primary power supply, the other end is connected with the cathode of the stabilizing diode D1, the anode of the stabilizing diode D1 is grounded, and the cathode of the stabilizing diode D1 is the output end of the upper limit constant voltage source VIH; The lower limit constant voltage source VIL is composed of the primary power supply, resistance R5 and stabilizing diode D2; One end of the resistance R5 is connected with the primary power supply, the other end is connected with the cathode of the stabilizing diode D2, the anode of the stabilizing diode D2 is grounded, and the cathode of the stabilizing diode D2 is the output end of the lower limit constant voltage source VIL.

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