Buffer circuits and delay circuits

Abstract

The present invention discloses a buffer circuit and a delay circuit. The buffer circuit comprises: an input terminal, an output terminal and a power supply terminal, wherein the input terminal is used to access an input differential signal, the output terminal is used to connect a functional circuit, and the power supply terminal is used to access a power supply; a driving unit is used to respond to an input differential signal at the input terminal and generate an output differential signal to the output terminal; a load unit is coupled between the output terminal and the power supply terminal; and a negative capacitance unit is coupled between the power supply terminal and the output terminal to reduce the capacitance of the functional circuit. The present invention can increase the operating frequency of the buffer circuit.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of circuit technology, and in particular to a buffer circuit and a delay circuit. Background Art

[0002] Buffer circuits can buffer input signals and then output them. They have the advantages of increasing circuit driving capability and optimizing waveforms, and are widely used in various circuits.

[0003] However, the existing buffer circuit has speed limitations and a low operating frequency, and is not very effective in higher frequency applications. Summary of the invention

[0004] The invention provides a buffer circuit and a delay circuit to improve the operating frequency of the buffer circuit.

[0005] In a first aspect, an embodiment of the present invention provides a buffer circuit, the buffer circuit comprising:

[0006] An input terminal, an output terminal and a power supply terminal, wherein the input terminal is used to receive an input differential signal, the output terminal is used to connect a functional circuit, and the power supply terminal is used to receive a power supply;

[0007] a driving unit, for responding to an input differential signal at the input terminal and generating an output differential signal to the output terminal;

[0008] A load unit, coupled between the output terminal and the power supply terminal;

[0009] A negative capacitance unit is coupled between the power supply terminal and the output terminal, and is used to reduce the capacitance of the functional circuit.

[0010] Optionally, the output terminal includes a first output terminal and a second output terminal; the load unit includes a first load and a second load; the negative capacitance unit includes a first triode, a second triode, a first diode structure and a second diode structure;

[0011] The first load, the first triode and the first diode structure are connected in series between the power supply terminal and the first output terminal; the second load, the second triode and the second diode structure are connected in series between the power supply terminal and the second output terminal;

[0012] The base of the first transistor is electrically connected to the collector of the second transistor, and the base of the second transistor is electrically connected to the collector of the first transistor.

[0013] Optionally, the first end of the first load is electrically connected to the power supply terminal, and the second end of the first load is electrically connected to the collector of the first transistor; the emitter of the first transistor is electrically connected to the first electrode of the first diode structure, and the second electrode of the first diode structure is electrically connected to the first output terminal;

[0014] The first end of the second load is electrically connected to the power supply terminal, and the second end of the second load is electrically connected to the collector of the second transistor; the emitter of the second transistor is electrically connected to the first pole of the second diode structure, and the second pole of the second diode structure is electrically connected to the second output terminal.

[0015] Optionally, a first electrode of the first diode structure is electrically connected to the power supply terminal, and a second electrode of the first diode structure is electrically connected to the collector of the first transistor; an emitter of the first transistor is electrically connected to a first end of the first load, and a second end of the first load is electrically connected to the first output terminal;

[0016] The first electrode of the second diode structure is electrically connected to the power supply terminal, and the second electrode of the second diode structure is electrically connected to the collector of the second transistor; the emitter of the second transistor is electrically connected to the first end of the second load, and the second end of the second load is electrically connected to the second output terminal.

[0017] Optionally, the first diode structure includes a third triode, the base of the third triode is electrically connected to the collector of the third triode to serve as the first electrode of the first diode structure, and the emitter of the third triode serves as the second electrode of the first diode structure;

[0018] The second diode structure includes a fourth triode, the base of the fourth triode is electrically connected to the collector of the fourth triode and serves as the first electrode of the second diode structure, and the emitter of the fourth triode serves as the second electrode of the second diode structure.

[0019] Optionally, the driving unit includes a fifth transistor and a sixth transistor; the input terminal includes a first input terminal and a second input terminal; the output terminal includes a first output terminal and a second output terminal;

[0020] The collector of the fifth transistor is electrically connected to the first output terminal, the emitter of the fifth transistor is electrically connected to the emitter of the sixth transistor, and the base of the fifth transistor is electrically connected to the first input terminal;

[0021] The collector of the sixth transistor is electrically connected to the second output terminal, and the base of the sixth transistor is electrically connected to the second input terminal.

[0022] Optionally, the buffer circuit further includes a first current source, a first end of the first current source is electrically connected to the emitter of the fifth transistor and the emitter of the sixth transistor, and a second end of the first current source is grounded.

[0023] Optionally, the buffer circuit further includes:

[0024] A first emitter follower and a second emitter follower;

[0025] The first output terminal is electrically connected to the input end of the first emitter follower, and the output end of the first emitter follower serves as the first follower output end of the buffer circuit;

[0026] The second output terminal is electrically connected to the input end of the second emitter follower, and the output end of the second emitter follower serves as the second follower output end of the buffer circuit.

[0027] Optionally, the first emitter follower includes a seventh transistor and a second current source; the base of the seventh transistor is electrically connected to the first output terminal, the collector of the seventh transistor is electrically connected to the power supply terminal, the emitter of the seventh transistor is electrically connected to the first end of the second current source and the first follower output terminal, and the second end of the second current source is grounded;

[0028] The second emitter follower includes an eighth transistor and a third current source; the base of the eighth transistor is electrically connected to the second output terminal, the collector of the eighth transistor is electrically connected to the power supply terminal, the emitter of the eighth transistor is electrically connected to the first end of the third current source and the second follower output terminal, and the second end of the third current source is grounded.

[0029] In the second aspect, an embodiment of the present invention further provides a delay circuit, which includes the buffer circuit and the functional circuit described in the first aspect, wherein the output terminal of the buffer circuit is used to connect the functional circuit; the functional circuit is a voltage-controlled delay unit, and the voltage-controlled delay unit is used to delay the input signal and then output it.

[0030] The technical solution of the embodiment of the present invention adopts a buffer circuit including: an input terminal, an output terminal and a power supply terminal, wherein the input terminal is used to access an input differential signal, the output terminal is used to connect a functional circuit, and the power supply terminal is used to access a power supply; a driving unit is used to respond to an input differential signal at the input terminal and generate an output differential signal to the output terminal; a load unit is coupled between the output terminal and the power supply terminal; and a negative capacitance unit is coupled between the power supply terminal and the output terminal to reduce the capacitance of the functional circuit. By coupling the negative capacitance unit between the power supply terminal and the output terminal of the buffer circuit, the capacitance of the functional circuit can be greatly reduced, thereby increasing the speed of signal transmission, and further increasing the operating frequency of the buffer circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 A schematic diagram of a circuit structure of a buffer circuit provided by an embodiment of the present invention;

[0032] Figure 2 A schematic diagram of a circuit structure of another buffer circuit provided in an embodiment of the present invention;

[0033] Figure 3 A schematic diagram of the circuit structure of another buffer circuit provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0034] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0035] Figure 1 A schematic diagram of a circuit structure of a buffer circuit provided by an embodiment of the present invention, referring to Figure 1 The buffer circuit includes: an input terminal, an output terminal and a power supply terminal VCC, the input terminal is used to input a differential signal, the output terminal is used to connect a functional circuit, and the power supply terminal VCC is used to access a power supply; a driving unit 11, used to respond to an input differential signal at the input terminal and generate an output differential signal to the output terminal; a load unit 13, coupled between the output terminal and the power supply terminal; a negative capacitance unit 12, coupled between the power supply terminal and the output terminal, used to reduce the capacitance of the functional circuit.

[0036] Specifically, the input terminals of the buffer circuit include a first input terminal VIN and a second input terminal VIP, and the input terminals are used to access the input differential signal; the output terminals include a first output terminal VON and a second output terminal VOP, and the output terminals are used to provide the output differential signal to the functional circuit, so that the functional circuit can work normally; the driving unit 11 can generate an output differential signal according to the input differential signal. For example, when the first input terminal VIN inputs a high level and the second input terminal VIP inputs a low level, the driving unit 11 can control the first output terminal VOP to output a low level and the second output terminal VON to output a high level; and when the first input terminal VIN inputs a low level and the second input terminal VIP inputs a low level, the driving unit 11 can control the first output terminal VOP to output a low level and the second output terminal VON to output a high level. When the sub-VIP inputs a high level, the driving unit 11 can control the first output terminal VOP to output a high level, and the second output terminal VON to output a low level; the load unit 13 is used to generate a voltage drop, so that the corresponding output terminal can output a high level and a low level; at high frequencies, the functional circuit will have a larger equivalent capacitance than the buffer circuit, which affects the speed of signal transmission, thereby making the operating frequency of the buffer circuit also lower. This embodiment can greatly reduce the capacitance of the functional circuit by coupling the negative capacitance unit 12 between the power supply terminal VCC and the output terminal of the buffer circuit, thereby increasing the speed of signal transmission, thereby increasing the load capacity, and increasing the operating frequency of the buffer circuit.

[0037] The technical solution of this embodiment adopts a buffer circuit including: an input terminal, an output terminal and a power supply terminal, wherein the input terminal is used to access an input differential signal, the output terminal is used to connect a functional circuit, and the power supply terminal is used to access a power supply; a driving unit is used to respond to an input differential signal at the input terminal and generate an output differential signal to the output terminal; a load unit is coupled between the output terminal and the power supply terminal; and a negative capacitance unit is coupled between the power supply terminal and the output terminal to reduce the capacitance of the functional circuit. By coupling the negative capacitance unit between the power supply terminal and the output terminal of the buffer circuit, the capacitance of the functional circuit can be greatly reduced, thereby increasing the speed of signal transmission, thereby increasing the load carrying capacity, and increasing the operating frequency of the buffer circuit.

[0038] Optionally, continue to refer to Figure 1, the output terminal includes a first output terminal VOP and a second output terminal VON; the load unit 13 includes a first load R1 and a second load R2; the negative capacitance unit 12 includes a first transistor Q5, a second transistor Q6, a first diode structure Q3 and a second diode structure Q4; the first load R1, the first transistor Q5 and the first diode structure Q3 are connected in series between the power supply terminal VCC and the first output terminal VOP; the second load R2, the second transistor Q6 and the second diode structure Q4 are connected in series between the power supply terminal VCC and the second output terminal VON; wherein the base of the first transistor Q5 is electrically connected to the collector of the second transistor Q6, and the base of the second transistor Q6 is electrically connected to the collector of the first transistor Q5.

[0039] Specifically, the first transistor Q5 and the second transistor Q6 form a cross-pair transistor structure, and the first diode structure Q3 and the second diode structure Q4 are coupled to form a negative feedback capacitor, and the negative feedback capacitor and the cross-pair transistor structure form a negative capacitance effect, thereby enabling the negative capacitance unit 12 to reduce the capacitance of the functional circuit and increase the operating frequency of the buffer circuit. In addition, in this embodiment, the diode structure is coupled to form a negative feedback capacitor, and the diode structure can also provide a voltage drop for the output branch, thereby reducing the power consumption of the buffer circuit.

[0040] For example, Figure 1 As shown in, a first end of the first load R1 is electrically connected to the power supply terminal VCC, and a second end of the first load R1 is electrically connected to the collector of the first transistor Q5; an emitter of the first transistor Q5 is electrically connected to a first electrode of the first diode structure Q3, and a second electrode of the first diode structure Q3 is electrically connected to a first output terminal VOP; a first end of the second load R2 is electrically connected to the power supply terminal VCC, and a second end of the second load R2 is electrically connected to a collector of a second transistor Q6; an emitter of the second transistor Q6 is electrically connected to a first electrode of a second diode structure Q4, and a second electrode of the second diode structure Q4 is electrically connected to a second output terminal VON.

[0041] Specifically, in this embodiment, the first load R1, the first transistor Q5 and the first diode structure Q3 are connected in series between the power supply terminal VCC and the first output terminal VOP, and the second load R2, the second transistor Q6 and the second diode structure Q4 are connected in series between the power supply terminal VCC and the second output terminal VON; the resistance values ​​of the first load R1 and the second load R2 can both be 50 ohms; the first transistor Q5 and the second transistor Q6 can both be NPN transistors, and the models of the two can be the same.

[0042] Or, in some other embodiments, such as Figure 2 As shown, Figure 2A circuit structure schematic diagram of another buffer circuit provided by an embodiment of the present invention. In this embodiment, a first electrode of the first two-section tube structure Q3 is electrically connected to the power supply terminal VCC, and a second electrode of the first diode structure Q3 is electrically connected to a collector of a first triode Q5; an emitter of the first triode Q5 is electrically connected to a first end of a first load R1, and a second end of the first load R1 is electrically connected to a first output terminal VOP; a first electrode of the second diode structure Q4 is electrically connected to the power supply terminal VCC, and a second electrode of the second diode structure Q4 is electrically connected to a collector of a second triode Q6; an emitter of the second triode Q6 is electrically connected to a first end of a second load R2, and a second end of the second load R2 is electrically connected to a second output terminal VON. In this embodiment, the first diode structure Q3, the first transistor Q5 and the first load R1 are connected in series between the power supply terminal VCC and the first output terminal VOP, and the second diode structure Q4, the second transistor Q6 and the second load R2 are connected in series between the power supply terminal VCC and the second output terminal VON; of course, in some other implementations, other connection methods are also possible, as long as the negative capacitor unit can be used to reduce the capacitance of the functional circuit, and the first diode structure and the second diode structure can be used to form a negative feedback capacitor and reduce power consumption.

[0043] Optionally, continue to refer to Figure 1 and Figure 2 The first diode structure Q3 includes a third triode, the base of the third triode is electrically connected to the collector of the third triode as the first pole of the first diode structure Q3, and the emitter of the third triode is the second pole of the first diode structure Q3; the second diode structure Q4 includes a fourth triode, the base of the fourth triode is electrically connected to the collector of the fourth triode as the first pole of the second diode structure Q4, and the emitter of the fourth triode is the second pole of the second diode structure Q4. The third triode and the fourth triode are used to form the first diode structure and the second diode structure respectively. In addition to being used as diodes, they can also play a role in temperature compensation due to their close temperature coefficients to the first triode Q5 and the second triode Q6.

[0044] Optionally, continue to refer to Figure 1 and Figure 2 The driving unit 11 includes a fifth transistor Q1 and a sixth transistor Q2; the input terminal includes a first input terminal VIN and a second input terminal VIP; the collector of the fifth transistor Q1 is electrically connected to the first output terminal VOP, the emitter of the fifth transistor Q1 is electrically connected to the emitter of the sixth transistor Q2, and the base of the fifth transistor Q1 is electrically connected to the first input terminal VIN; the collector of the sixth transistor Q2 is electrically connected to the second output terminal VON, and the base of the sixth transistor is electrically connected to the second input terminal VIP.

[0045] Specifically, the fifth transistor Q1 and the sixth transistor Q2 are both current driven. When the first input terminal VIN is at a high level and the second input terminal VIP is at a low level, the fifth transistor Q1 is turned on and the sixth transistor Q2 is turned off. Current flows through the first load R1, so that a voltage drop is generated on the first load R1, that is, the voltage output by the first output terminal VOP is less than the voltage at the power supply terminal VCC. Since the sixth transistor Q2 is turned off, there is no current on the second load R2, and the voltage output by the second output terminal VON is equal to the voltage at the power supply terminal VCC, that is, the first output terminal VOP outputs a low level. The second output terminal VON outputs a high level; when the first input terminal VIN is at a low level and the second input terminal VIP is at a high level, the fifth transistor Q1 is turned off, the sixth transistor Q2 is turned on, and current flows through the second load R2, causing a voltage drop on the second load R2, that is, the voltage output by the second output terminal VON is less than the voltage at the power supply terminal VCC, and since the fifth transistor Q1 is turned off, there is no current on the first load R1, and the voltage output by the first output terminal VOP is equal to the voltage at the power supply terminal VCC, that is, the first output terminal VOP outputs a high level, and the second output terminal VON outputs a low level.

[0046] Optionally, continue to refer to Figure 1 and Figure 2 The buffer circuit further includes a first current source I1, a first end of the first current source I1 is electrically connected to the emitter of the fifth transistor Q1 and the emitter of the sixth transistor Q2, and a second end of the first current source I1 is grounded.

[0047] Specifically, the first current source I1 is used to provide a bias for the fifth transistor Q1 and the sixth transistor Q2, and can provide a stable static operating point; the magnitude of the current of the first current source I1 affects the swing of the output voltage of the output terminal, and the magnitude of the swing affects the transmission rate, distance and power consumption of the circuit, etc. The output current of the first current source I1 can be 16 mA.

[0048] Optionally, Figure 3 A circuit structure diagram of another buffer circuit provided in an embodiment of the present invention, the buffer circuit also includes a first emitter follower 14 and a second emitter follower 15; the first output terminal VOP is electrically connected to the input end of the first emitter follower 14, and the output end of the first emitter follower 14 serves as a first follower output terminal VOP1 of the buffer circuit; the second output terminal VON is electrically connected to the input end of the second emitter follower 15, and the output end of the second emitter follower 15 serves as a second follower output terminal VON2 of the buffer circuit.

[0049] Specifically, in this embodiment, the output differential signal can be set to be output from the follower output end of the buffer circuit after passing through the first emitter follower 14 and the second emitter follower 15 respectively. By adding an emitter follower, the load capacity of the buffer circuit can be greatly improved, and the application range of the buffer circuit can be further expanded. It should be noted that when the buffer circuit is added with an emitter follower, the functional circuit can be connected to the follower output end of the buffer circuit.

[0050] For example, Figure 3 As shown, the first emitter follower 14 includes a seventh transistor Q7 and a second current source I2; the base of the seventh transistor Q7 is electrically connected to the first output terminal, the collector of the seventh transistor Q7 is electrically connected to the power supply terminal VCC, the emitter of the seventh transistor Q7 is electrically connected to the first end of the second current source I2 and the first follower output terminal VOP1, and the second end of the second current source I2 is grounded; the second emitter follower 15 includes an eighth transistor Q8 and a third current source I3; the base of the eighth transistor Q8 is electrically connected to the second output terminal VON, the collector of the eighth transistor Q8 is electrically connected to the power supply terminal VCC, the emitter of the eighth transistor Q8 is electrically connected to the first end of the third current source I3 and the second follower output terminal VON1, and the second end of the third current source I3 is grounded.

[0051] Specifically, in this embodiment, the function of the emitter follower can be realized by using a transistor and a current source, the circuit structure is simple, easy to implement, and the cost of the buffer circuit can be greatly reduced. The buffer circuit of this embodiment can be applied to a clock link to improve the driving capability of the clock link and can also perform waveform shaping.

[0052] The embodiment of the present invention further provides a delay circuit, which includes the buffer circuit and the functional circuit provided by any embodiment of the present invention, wherein the output terminal of the buffer circuit is used to connect the functional circuit; the functional circuit is a voltage-controlled delay unit, and the voltage-controlled delay unit is used to output the input signal after delay. Because it includes the delay circuit provided by any embodiment of the present invention, it also has the same beneficial effects, which will not be described in detail here.

[0053] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A buffer circuit, characterized in that: The buffer circuit comprises: An input terminal, an output terminal and a power supply terminal, wherein the input terminal is used to receive an input differential signal, the output terminal is used to connect a functional circuit, and the power supply terminal is used to receive a power supply; a driving unit, for responding to an input differential signal at the input terminal and generating an output differential signal to the output terminal; A load unit, coupled between the output terminal and the power supply terminal; a negative capacitance unit, coupled between the power supply terminal and the output terminal, for reducing the capacitance of the functional circuit; The output terminal includes a first output terminal and a second output terminal; the load unit includes a first load and a second load; the negative capacitance unit includes a first triode, a second triode, a first diode structure and a second diode structure; the first load, the first triode and the first diode structure are connected in series between the power supply terminal and the first output terminal, wherein the first diode structure includes a third triode, the base of the third triode is electrically connected to the collector of the third triode and serves as the first pole of the first diode structure, and the emitter of the third triode serves as the second pole of the first diode structure; the second load, the second triode and the second diode structure are connected in series between the power supply terminal and the second output terminal; the base of the first triode is electrically connected to the collector of the second triode, and the base of the second triode is electrically connected to the collector of the first triode, wherein the second diode structure includes a fourth triode, the base of the fourth triode is electrically connected to the collector of the fourth triode and serves as the first pole of the second diode structure, and the emitter of the fourth triode serves as the second pole of the second diode structure.

2. The buffer circuit according to claim 1, characterized in that: The first end of the first load is electrically connected to the power supply terminal, and the second end of the first load is electrically connected to the collector of the first transistor; the emitter of the first transistor is electrically connected to the first electrode of the first diode structure, and the second electrode of the first diode structure is electrically connected to the first output terminal; The first end of the second load is electrically connected to the power supply terminal, and the second end of the second load is electrically connected to the collector of the second transistor; the emitter of the second transistor is electrically connected to the first pole of the second diode structure, and the second pole of the second diode structure is electrically connected to the second output terminal.

3. The buffer circuit according to claim 1, wherein: The first electrode of the first diode structure is electrically connected to the power supply terminal, and the second electrode of the first diode structure is electrically connected to the collector of the first transistor; the emitter of the first transistor is electrically connected to the first end of the first load, and the second end of the first load is electrically connected to the first output terminal; The first electrode of the second diode structure is electrically connected to the power supply terminal, and the second electrode of the second diode structure is electrically connected to the collector of the second transistor; the emitter of the second transistor is electrically connected to the first end of the second load, and the second end of the second load is electrically connected to the second output terminal.

4. The buffer circuit according to claim 1, wherein: The driving unit includes a fifth transistor and a sixth transistor; the input terminal includes a first input terminal and a second input terminal; the output terminal includes a first output terminal and a second output terminal; The collector of the fifth transistor is electrically connected to the first output terminal, the emitter of the fifth transistor is electrically connected to the emitter of the sixth transistor, and the base of the fifth transistor is electrically connected to the first input terminal; The collector of the sixth transistor is electrically connected to the second output terminal, and the base of the sixth transistor is electrically connected to the second input terminal.

5. The buffer circuit according to claim 4, characterized in that: The buffer circuit further includes a first current source, a first end of which is electrically connected to the emitter of the fifth transistor and the emitter of the sixth transistor, and a second end of the first current source is grounded.

6. The buffer circuit according to claim 1, characterized in that: The buffer circuit further includes: A first emitter follower and a second emitter follower; The first output terminal is electrically connected to the input end of the first emitter follower, and the output end of the first emitter follower serves as the first follower output end of the buffer circuit; The second output terminal is electrically connected to the input end of the second emitter follower, and the output end of the second emitter follower serves as the second follower output end of the buffer circuit.

7. The buffer circuit according to claim 6, characterized in that: The first emitter follower includes a seventh transistor and a second current source; the base of the seventh transistor is electrically connected to the first output terminal, the collector of the seventh transistor is electrically connected to the power supply terminal, the emitter of the seventh transistor is electrically connected to the first end of the second current source and the first follower output end, and the second end of the second current source is grounded; The second emitter follower includes an eighth transistor and a third current source; the base of the eighth transistor is electrically connected to the second output terminal, the collector of the eighth transistor is electrically connected to the power supply terminal, the emitter of the eighth transistor is electrically connected to the first end of the third current source and the second follower output terminal, and the second end of the third current source is grounded.

8. A delay circuit, characterized in that: The delay circuit comprises the buffer circuit and the functional circuit according to any one of claims 1 to 7, wherein the output terminal of the buffer circuit is used to connect the functional circuit; the functional circuit is a voltage-controlled delay unit, and the voltage-controlled delay unit is used to output the input signal after delaying it.

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