Clock distribution network and method thereof

Abstract

A clock distribution network and method thereof. The method comprises: receiving a remote voltage signal; converting the remote voltage signal into a local voltage signal using a current mode transmission scheme, the current mode transmission scheme comprising a voltage-to-current driver, a transmission line, a current buffer and an inductor-capacitor slot connected in series; transmitting the local voltage signal into a first destination voltage signal using a voltage mode transmission scheme, the voltage mode transmission scheme comprising a first capacitor drive line and a first inverter buffer connected in series; and transmitting the local voltage signal into a second destination voltage signal using a voltage mode transmission scheme, the voltage mode transmission scheme comprising a second capacitor drive line and a second inverter buffer connected in series.

Description

Technical Field

[0001] The present disclosure relates to clock distribution, and more particularly to a clock distribution network and method for transmitting a high-speed clock in a relatively long transmission line. Background Art

[0002] A clock signal is a voltage signal that oscillates between a low level and a high level. Clock signals are widely used in synchronous digital circuits and can be used to coordinate the actions between synchronous digital circuits. In an integrated circuit including a plurality of synchronous digital circuits, there is usually a clock generation circuit, such as a phase-locked loop, for generating a clock signal, and the clock signal generated by the clock generation circuit is usually transmitted to each synchronous digital circuit via a transmission line to coordinate the actions of these synchronous digital circuits. In one example, the synchronous digital circuit that needs to receive the clock signal generated by the clock generation circuit may be far away from the clock generation circuit, making the transmission of the clock signal extremely challenging. If the length of the transmission line is considerable relative to the wavelength of the clock signal, the transmission line is considered to be relatively long. For example, for a 15 GHz clock with a wavelength of 10 millimeters (mm), a 2 mm transmission line can be considered relatively long when considering clock transmission. Long-distance transmission of clock signals often encounters a large amount of transmission loss, resulting in weak signal strength at the receiving end. In particular, when the clock signal is a high-speed clock signal, the transmission loss of the transmission line increases with the frequency of the transmitted signal, making the problem particularly serious. For a 2 mm transmission line fabricated on a substrate using a CMOS process, a 15 GHz clock typically has an insertion loss of 3 dB, which is considered to be a significant insertion loss. In some instances, there are multiple local circuits at the receiving end that require a clock signal, but the local separation distances between these local circuits are small.

[0003] Therefore, it is desired to have a clock distribution method that can be used for long-distance transmission of high-speed clock signals and distribute the high-speed clock signals to multiple locally separated local circuits without incurring significant insertion loss. Summary of the invention

[0004] According to some embodiments, the clock distribution network includes a voltage-to-current driver, a transmission line, a current buffer, an inductor-capacitor slot, a first capacitor driving line, a first inverter buffer, a second capacitor driving line, and a second inverter buffer. The voltage-to-current driver is used to receive a first voltage signal and output a first current signal. The transmission line is used to receive a first current signal and output a second current signal. The current buffer is used to receive a second current signal and output a third current signal.

[0005] The inductor capacitor slot is used to receive a third current signal and establish a second voltage signal. The first capacitor driving line is used to receive the second voltage signal and output a third voltage signal. The first inverter buffer is used to receive the third voltage signal and output a fourth voltage signal. The second capacitor driving line is used to receive the second voltage signal and output a fifth voltage signal. The second inverter buffer is used to receive the fifth voltage signal and output a sixth voltage signal.

[0006] According to some embodiments, the clock distribution method includes: receiving a first voltage signal; converting the first voltage signal into a first current signal using a voltage-to-current driver; transmitting the first current signal into a second current signal using a transmission line; relaying the second current signal into a third current signal using a current buffer; using an inductor capacitor slot as a load to convert the third current signal into a second voltage signal; converting the second voltage signal into a third voltage signal using a first capacitor drive line; amplifying the third voltage signal into a fourth voltage signal using a first inverter buffer; transmitting the second voltage signal into a fifth voltage signal using a second capacitor drive line; and amplifying the fifth voltage signal into a sixth voltage signal using a second inverter buffer.

[0007] According to some embodiments, a clock distribution method includes: receiving a remote voltage signal; converting the remote voltage signal into a local voltage signal using a current mode transmission scheme, the current mode transmission scheme includes a voltage-to-current driver, a transmission line, a current buffer and an inductor capacitor slot, wherein the voltage-to-current driver, the transmission line, the current buffer and the inductor capacitor slot are connected in series; transmitting the local voltage signal into a first destination voltage signal using a voltage mode transmission scheme, the voltage mode transmission scheme includes a first capacitor drive line and a first inverter buffer, wherein the first capacitor drive line and the first inverter buffer are connected in series; and transmitting the local voltage signal into a second destination voltage signal using a voltage mode transmission scheme, the voltage mode transmission scheme includes a second capacitor drive line and a second inverter buffer, wherein the second capacitor drive line and the second inverter buffer are connected in series. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 It is a schematic diagram of a clock distribution network according to some embodiments of the present disclosure.

[0009] Figure 2 Schematic diagram of a voltage-to-current driver according to some embodiments of the present disclosure.

[0010] Figure 3 is a schematic diagram of a current buffer according to some embodiments of the present disclosure.

[0011] Figure 4 Schematic diagram of an inductor and capacitor slot according to some embodiments of the present disclosure.

[0012] Figure 5 is a schematic diagram of an inverter buffer according to some embodiments of the present disclosure.

[0013] Figure 6 is a schematic diagram of a transmission line according to some embodiments of the present disclosure.

[0014] Figure 7 The present invention is a flowchart of a clock distribution method according to some embodiments of the present disclosure.

[0015] Explanation of symbols

[0016] 100: Clock Distribution Network

[0017] 110: Voltage to Current Driver

[0018] 120: Transmission line

[0019] 130: Current buffer

[0020] 140: Inductor and capacitor slots

[0021] 150: First capacitor driving line

[0022] 151: Capacitor

[0023] 152: Capacitor

[0024] 153: Transmission Line

[0025] 160: First inverter buffer

[0026] 165: First local circuit

[0027] 170: Second capacitor driving line

[0028] 171: Capacitor

[0029] 172: Capacitor

[0030] 173: Transmission Line

[0031] 180: Second inverter buffer

[0032] 185: Second local circuit

[0033] V1: first voltage signal

[0034] V2: Second voltage signal

[0035] V3: The third voltage signal

[0036] V4: fourth voltage signal

[0037] V5: Fifth voltage signal

[0038] V6: Sixth voltage signal

[0039] I1: First current signal

[0040] I2: Second current signal

[0041] I3: The third current signal

[0042] 200: Voltage to Current Driver

[0043] 201: N-type transistor

[0044] 202: N-type transistor

[0045] 203: N-type transistor

[0046] 209: Common source node

[0047] V B1 : First bias voltage

[0048] V 1+ : The first voltage signal

[0049] V 1- : The first voltage signal

[0050] I 1+ : The first current signal

[0051] I 1- : The first current signal

[0052] 300: Current buffer

[0053] 311: N-type transistor

[0054] 312: N-type transistor

[0055] 321: Capacitor

[0056] 322: Capacitor

[0057] 331: Resistor

[0058] 332: Resistor

[0059] V B2 : Second bias voltage

[0060] I 2+ : The second current signal

[0061] I 2- : The second current signal

[0062] I 3+ : The third current signal

[0063] I 3-: The third current signal

[0064] 400: Inductor and capacitor slots

[0065] 410: Inductor

[0066] 420: Capacitor

[0067] V DD : Power Node

[0068] V DD : Supply voltage

[0069] V 2+ : The second voltage signal

[0070] V 2- : The second voltage signal

[0071] 500: Inverter Buffer

[0072] 510: First inverter

[0073] 511: N-type transistor

[0074] 512: P-type transistor

[0075] 513: Feedback resistor

[0076] 520: Second inverter

[0077] 521: N-type transistor

[0078] 522: P-type transistor

[0079] 523: Feedback resistor

[0080] V 3+ : The third voltage signal

[0081] V 3- : The third voltage signal

[0082] V 4+ : The fourth voltage signal

[0083] V 4- : The fourth voltage signal

[0084] 600: Transmission Line

[0085] 631: Metal routing

[0086] 632: Metal routing

[0087] 633: Metal routing

[0088] 634: Metal routing

[0089] 635: Ground Plane

[0090] 639: Box

[0091] 710-790: Steps DETAILED DESCRIPTION

[0092] The present disclosure relates to clock distribution networks and methods thereof. Although several preferred modes of implementing the present disclosure are described in the specification, it should be understood that the present disclosure can still be implemented in many ways and should not be limited to the specific embodiments described below or the specific methods of implementing the features described below. In the embodiments, well-known details will not be repeated or discussed again to avoid blurring the key points of the present disclosure.

[0093] Those skilled in the art should be able to understand the terms and basic concepts related to microelectronics used in the present disclosure, such as "circuit node", "power supply node (power node)", "ground node", "differential signal", "differential pair", "voltage", "current", "complementary metal oxide semiconductor (CMOS)", "P-type transistor (PMOS)", "N-type transistor (NMOS)", "resistor", "inductor", "capacitor", "inverter", "buffer", "inductor-capacitor tank (LC tank)", "clock", "signal", "amplifier", "common source", "common gate", "impedance", "transmission line", and "load". Since the above terms and basic concepts are well known to those skilled in the art, they will not be explained in detail here.

[0094] A person skilled in the art can recognize a circuit schematic diagram including components such as capacitors, inductors, resistors, N-type transistors, and P-type transistors, and there is no need to describe in detail how one component is connected to another component in the schematic diagram. For ease of representation, the "source terminal" of a transistor is hereinafter referred to as the "source", the "gate terminal" is referred to as the "gate", and the "drain terminal" is referred to as the "drain". A person skilled in the art can also understand the symbols of P-type transistors and N-type transistors, and distinguish the "source", "gate" and "drain" of P-type transistors and N-type transistors. A person skilled in the art can also understand units such as volts (V), gigahertz (GHz), millimeters (mm), micrometers (μm), nanometers (nm), kiloohms (KOhm), nanohenries (nH) and femtofarads (fF).

[0095] The present disclosure is expressed from an engineering perspective (i.e., from the perspective of a person skilled in the art), rather than from a strictly mathematical perspective. For example, "A equals B" means "the difference between A and B is less than the engineering tolerance."

[0096] In the present disclosure, the ground node is used as a reference node for zero voltage (0 volt) electromotive force. The power supply node is represented by "VDD". For convenience, "VDD" can also represent the power supply voltage provided at the power supply node, hereinafter referred to as "power supply voltage".

[0097] In this disclosure, a circuit is a collection of transistors, capacitors, resistors, and / or other electronic devices that are interconnected in a specific way to achieve a specific function. A network is a circuit or a collection of multiple circuits.

[0098] In the present disclosure, a signal is a variable voltage level or current level, and the level is used to represent certain information.

[0099] In the present disclosure, the clock signal is a voltage signal oscillating between a low level and a high level.

[0100] In the present disclosure, the transmission of a signal includes transmitting the signal using a transmitter, transmitting the signal using a transmission line, and receiving the signal using a receiver. The current mode transmission scheme utilizes a receiver with a low input impedance; in this example, the input impedance of the receiver is less than the output impedance of the transmitter. The voltage mode transmission scheme utilizes a receiver with a high input impedance; in this example, the input impedance of the receiver is greater than the output impedance of the transmitter.

[0101] In the present disclosure, a current buffer is a circuit that receives an input current from an input terminal and outputs an output current at an output terminal, so that the input impedance is low at the input terminal and the output impedance is high at the output terminal, and the input impedance is substantially independent of the load condition at the output terminal.

[0102] Figure 1 FIG. 1 is a schematic diagram of a clock distribution network 100 according to some embodiments of the present disclosure. Figure 1 In some embodiments, the purpose of the clock distribution network 100 is to transmit a clock signal from a remote location to a local location and then distribute the clock signal to multiple local circuits. By way of example and not limitation, Figure 1Two local circuits (a first local circuit 165 and a second local circuit 185) are shown. The clock distribution network 100 includes a voltage-to-current driver 110, a transmission line 120, a current buffer 130, an inductor capacitor tank (LC tank) 140, a first capacitively driven wire (CDW) 150, a first inverter buffer 160, a first local circuit 165, a second capacitor driving line 170, a second inverter buffer 180 and a second local circuit 185. The voltage-to-current driver 110 is used to receive a first voltage signal V1 and output a first current signal I1. The transmission line 120 is used to transmit the first current signal I1 to a second current signal I2. The current buffer 130 is used to receive the second current signal I2 and output a third current signal I3. The inductor capacitor tank 140 is used to receive the third current signal I3 and output a second voltage signal V2. The first capacitor driving line 150 is used to receive the second voltage signal V2 and output the third voltage signal V3. The first inverter buffer 160 is used to receive the third voltage signal V3 and output the fourth voltage signal V4. The first local circuit 165 is used to receive the fourth voltage signal V4. The second capacitor driving line 170 is used to receive the second voltage signal V2 and output the fifth voltage signal V5. The second inverter buffer 180 is used to receive the fifth voltage signal V5 and output the sixth voltage signal V6. The second local circuit 185 is used to receive the sixth voltage signal V6. The voltage-to-current driver 110 is located at a remote position, and the current buffer 130, the inductor capacitor slot 140, the first capacitor driving line 150, the second capacitor driving line 170, the first inverter buffer 160, the second inverter buffer 180, the first local circuit 165 and the second local circuit 185 are all located at a local position.

[0103] In some embodiments, the first voltage signal V1 is a remote voltage signal, the second voltage signal V2 is a local voltage signal, the fourth voltage signal V4 is a first destination voltage signal, and the sixth voltage signal V6 is a second destination voltage signal.

[0104] In some embodiments, the first voltage signal V1 is a high-speed clock signal. The voltage-to-current driver 110 converts the first voltage signal V1 into a first current signal I1, and the first current signal I1 is transmitted along the transmission line 120 as a second current signal I2. The purpose of the current buffer 130 and the inductor capacitor slot 140 is to convert the second current signal I2 into a second voltage signal V2, so that the second voltage signal V2 can have a larger swing. A current mode transmission scheme is adopted here, and the current buffer 130 is used to provide low impedance, so that the second current signal I2 flows into, passes through and becomes the third current signal I3. The current mode transmission scheme has the advantage of low insertion loss, because the insertion loss from the transmission line 120 is mainly presented in the form of voltage drop, which is not a problem for the current mode transmission. The current buffer 130 has a high output impedance, and the inductor capacitor slot 140 is used to realize the load. The resonant frequency of the inductor capacitor slot 140 is tuned to the frequency of the high-speed clock signal. Thus, the LC tank 140 may have a high impedance to the third current signal I3 , and the second voltage signal V2 may have a larger swing.

[0105] In some embodiments, the second voltage signal V2 needs to be transmitted to the first local circuit 165 and the second local circuit 185, wherein the first local circuit 165 and the second local circuit 185 are both local, but are still partially isolated from the inductor capacitor slot 140. The first capacitor drive line 150 and the second capacitor drive line 170 are used for local transmission. Voltage mode transmission is adopted here, and since the current transmission distance is short, the disadvantage of higher insertion loss of voltage mode transmission compared with current mode transmission is not very important. On the other hand, voltage mode transmission has the advantage of being easy to receive, and since a receiver circuit with a high impedance input is generally easier to implement than a receiver circuit with a low input impedance, an inverter buffer such as the first inverter buffer 160 and the second inverter buffer 180 can be used. The use of capacitor drive lines such as the first capacitor drive line 150 and the second capacitor drive line 170 has the advantage of high input impedance, thereby reducing the load effect on the inductor capacitor slot 140. The first capacitor driving line 150 and the second capacitor driving line 170 can both cause insertion loss, so the swing of the third voltage signal V3 and the fifth voltage signal V5 is smaller than the swing of the second voltage signal V2. The first inverter buffer 160 and the second inverter buffer 180 are used to amplify and restore the voltage swing, so that the fourth voltage signal V4 and the sixth voltage signal V6 can have a large swing.

[0106] In some embodiments, a differential signal is used, such as a voltage signal or a current signal, wherein the differential signal includes a first portion with a subscript “+” and a second portion with a subscript “-”. Specifically, the first voltage signal V1 includes the first voltage signal V 1+ and the first voltage signal V 1-, the second voltage signal V2 includes the second voltage signal V 2+ and the second voltage signal V 2- , the third voltage signal V3 includes a third voltage signal V 3+ and the third voltage signal V 3- , the fourth voltage signal V4 includes a fourth voltage signal V 4+ and the fourth voltage signal V 4- , the fifth voltage signal V5 includes the fifth voltage signal V 5+ and the fifth voltage signal V 5- , the sixth voltage signal V6 includes the sixth voltage signal V 6+ and the sixth voltage signal V 6- The first current signal I1 includes the first current signal I 1+ and the first current signal I 1- The second current signal I2 includes the second current signal I 2+ and the second current signal I 2- The third current signal I3 includes the third current signal I 3+ and the third current signal I 3- Differential signals are well known to those skilled in the art and will not be explained in detail here.

[0107] Figure 2 FIG. 2 is a schematic diagram of a voltage-to-current driver 200 according to some embodiments of the present disclosure. Figure 1 and Figure 2 In some embodiments, the voltage-to-current driver 110 is used to implement the function of converting voltage into current, and a schematic diagram of a voltage-to-current driver 200 for implementing the voltage-to-current driver 110 is shown in FIG. Figure 2 As mentioned earlier, Figure 2 A differential signal is used: the first voltage signal V 1+ and the first voltage signal V 1- The first voltage signal V1 and the first current signal I 1+ and the first current signal I 1- The voltage-to-current driver 200 includes an N-type transistor 201 and an N-type transistor 202. The N-type transistor 201 and the N-type transistor 202 are used to receive the first voltage signal V 1+ and the first voltage signal V 1- , and outputs a first current signal I 1+ and the first current signal I 1-The N-type transistor 201 and the N-type transistor 202 are used as a differential pair of common-source amplifiers. The voltage-to-current driver 200 further includes another N-type transistor 203. The N-type transistor 203 is used to generate a voltage according to the first bias voltage V B1 A bias current is provided to the common source node 209 of the common-source amplifier differential pair. The voltage-to-current driver 200 is well known to those skilled in the art and will not be explained in detail herein. In an alternative embodiment not shown in the figure but well known to those skilled in the art, the N-type transistor 203 is replaced with a resistor. This alternative embodiment is also known to the public and will not be explained further. In another alternative embodiment not shown in the figure but obvious to those skilled in the art, the N-type transistor 203 is replaced with a short circuit. In this example, the N-type transistor 201 and the N-type transistor 202 form a pseudo-differential pair of common-source amplifiers. This alternative embodiment is also known to the public and will not be explained further.

[0108] Figure 3 FIG. 3 is a schematic diagram of a current buffer 300 according to some embodiments of the present disclosure. Figure 1 and Figure 3 , in some embodiments, a schematic diagram of a current buffer 300 for implementing the current buffer 130 is shown as Figure 3 As mentioned earlier, Figure 3 A differential signal is used: the second current signal I 2+ and the second current signal I 2- The second current signal I2 is realized together, and the third current signal I 3+ and the third current signal I 3- The current buffer 300 includes an N-type transistor 311, an N-type transistor 312, a capacitor 321, a capacitor 322, a resistor 331, and a resistor 332. The N-type transistor 311 and the N-type transistor 312 are respectively used to receive the second current signal I 2+ and the second current signal I 2- , and outputs a third current signal I 3+ and the third current signal I 3-. Resistors 331 and 332 are used to establish gate biases for N-type transistors 311 and 312, respectively. Capacitors 321 and 322 are used to provide cross-coupling between N-type transistors 311 and 312, respectively, that is, the gate of N-type transistor 311 is coupled to the source of N-type transistor 312 via capacitor 322, and the gate of N-type transistor 312 is coupled to the source of N-type transistor 311 via capacitor 321. N-type transistors 311 and N-type transistors 312 are configured in a common-gate amplifier topology, and the cross-coupling between N-type transistors 311 and 312 can effectively increase the gain. Here, “V B2 ” represents the second bias voltage. The current buffer 300 is known in the prior art and will not be explained in detail here.

[0109] Figure 4 FIG. 4 is a schematic diagram of an inductor and capacitor tank 400 according to some embodiments of the present disclosure. Figure 1 and Figure 4 In some embodiments, a schematic diagram of an inductor and capacitor slot 400 for implementing the inductor and capacitor slot 140 is shown as follows. Figure 4 As mentioned earlier, Figure 4 A differential signal is used: the third current signal I 3+ and the third current signal I 3- The third current signal I3 is realized together, and the second voltage signal V 2+ and the second voltage signal V 2- The LC tank 400 includes an inductor 410 and a capacitor 420, which are configured in a parallel connection topology. The inductor 410 has a center tap, which is connected to the power node V DD In the case of resonance, the imaginary part of the impedance of the inductor 410 and the imaginary part of the impedance of the capacitor 420 are approximately the same but have opposite polarities. The LC tank 400 has a high input impedance and can make the second voltage signal V2 have a large swing.

[0110] Continue to refer to Figure 1In some embodiments, the first capacitance driving line 150 includes a capacitor 151, a capacitor 152 and a transmission line 153, wherein the capacitor 151, the capacitor 152 and the transmission line 153 are configured in a series connection topology. Similarly, the second capacitance driving line 170 includes a capacitor 171, a capacitor 172 and a transmission line 173, wherein the capacitor 171, the capacitor 172 and the transmission line 173 are configured in a series connection topology. Transmission lines 153 and 173 are local transmission lines shorter than transmission line 120. Compared with the case where transmission line 153 is directly connected to the inductor capacitor slot 140, due to the series connection of capacitor 151 and capacitor 152, the first capacitance driving line 150 has a higher impedance to the inductor capacitor slot 140. This is because capacitor 151 and capacitor 152 provide high impedance in advance and prevent the inductor capacitor slot 140 from seeing the transmission line 153, which is equivalent to a large capacitance load. Similarly, corresponding to capacitor 171, capacitor 172 and second capacitance driving line 170.

[0111] In some embodiments, it is noted that the transmission line is essentially a distributed network. In a lumped circuit, "the first element in front is connected in series to the second element in the back" is equivalent to "the second element in front is connected in series to the first element in the back". However, in a distributed network, swapping the order of elements in the series connection will lead to different results. Therefore, swapping the order of transmission line 153 and capacitors 151 and 152 will lead to different effects and deviate from the purpose of the capacitive drive line.

[0112] Figure 5 FIG. 5 is a schematic diagram of an inverter buffer 500 according to some embodiments of the present disclosure. Figure 1 and Figure 5 , in some embodiments, a schematic diagram of an inverter buffer 500 for implementing the first inverter buffer 160 is shown as Figure 5 As mentioned earlier, Figure 5 A differential signal is used: the third voltage signal V 3+ and the third voltage signal V 3- The third voltage signal V3 is realized together, and the fourth voltage signal V 4+ and the fourth voltage signal V 4- The inverter buffer 500 includes a first inverter 510 and a second inverter 520. The first inverter 510 is used to receive the third voltage signal V 3+ , and outputs a fourth voltage signal V 4- The second inverter 520 is used to receive the third voltage signal V 3- , and outputs a fourth voltage signal V 4+The first inverter 510 includes an N-type transistor 511, a P-type transistor 512, and a feedback resistor 513. The second inverter 520 includes an N-type transistor 521, a P-type transistor 522, and a feedback resistor 523. The inverter buffer 500 is known in the prior art, and thus will not be explained in detail herein.

[0113] In some embodiments, the inverter buffer 500 can be configured to output the third voltage signal V 3+ , the third voltage signal V 3- , the fourth voltage signal V 4+ and the fourth voltage signal V 4- is the fifth voltage signal V 5+ , the fifth voltage signal V 5- , the sixth voltage signal V 6+ and the sixth voltage signal V 6- , to realize the second inverter buffer 180.

[0114] In some embodiments, the first local circuit 165 and the second local circuit 185 use the fourth voltage signal V4 and the sixth voltage signal V6 respectively to implement circuits of certain functions, such as clock multiplication, frequency conversion, logical operation, etc.

[0115] In some embodiments, transmission lines 120 , 153 , and 173 may be implemented in any embodiment known in the art at the discretion of a circuit designer.

[0116] Figure 6 FIG. 6 is a schematic diagram of a transmission line 600 according to some embodiments of the present disclosure. Figure 6 In some embodiments, by way of example and not limitation, the clock distribution network 100 is fabricated on a substrate using a 28 nanometer CMOS process. The 28 nanometer CMOS process includes a plurality of metal layers, including a top metal layer (e.g., an RDL layer), a thick metal layer (not shown), and a thin metal layer (e.g., an ME6 layer). The top metal layer is an aluminum metal layer that may be referred to as a redistribution layer and is often referred to as an "RDL layer." The thick metal layer is located below the top metal layer (RDL layer), and the thin metal layer is located below the thick metal layer. The power supply voltage V DDis 1.1 volts. The first voltage signal is 14 GHz. The channel width and channel length (W / L) of N-type transistor 201 and N-type transistor 202 are 20 microns and 30 nanometers, respectively. The channel width and channel length of N-type transistor 203 are 40 microns and 200 nanometers, respectively. The channel width and channel length of N-type transistor 311 and N-type transistor 312 are 20 microns and 30 nanometers, respectively. Capacitor 321 and capacitor 322 are both 100 femtofarads. Resistor 331 and resistor 332 are both 10 kilo-ohms. The length of transmission line 120 is 2.6 millimeters. Inductor 410 is 0.5 nanohenry. Capacitor 420 is 260 femtofarads. Capacitor 151, capacitor 152, capacitor 171 and capacitor 172 are all 400 femtofarads. The length of transmission line 153 is 800 microns. The length of transmission line 173 is 650 microns. The channel width and channel length of the N-type transistor 511 and the N-type transistor 521 are 10 micrometers and 30 nanometers, respectively. The channel width and channel length of the P-type transistor 512 and the P-type transistor 522 are 14 micrometers and 30 nanometers, respectively. The feedback resistor 513 and the feedback resistor 523 are both 10 kilo-ohms. A cross-sectional view of the transmission line 600 used to implement the transmission line 120, the transmission line 153, and the transmission line 173 is shown in FIG. Figure 6 As shown. The description of each section line is shown in box 639. Transmission line 600 includes two metal traces (hereinafter referred to as metal trace 631 and metal trace 632) parallel to each other. The width of metal trace 631 and metal trace 632 are both 2 microns, the thickness is both 3 microns, and the spacing between metal trace 631 and metal trace 632 is 6 microns. Metal trace 631 and metal trace 632 are arranged on the top metal layer (RDL layer), and this top metal layer is embedded in the dielectric on the substrate. Transmission line 600 also includes two additional metal traces (hereinafter referred to as metal trace 633 and metal trace 634). Metal trace 633 and metal trace 634 are used to shield metal trace 631 and metal trace 632, and metal trace 633 and metal trace 634 need to be connected to the ground node. The width of metal trace 633 and metal trace 634 are both 2 microns, the thickness is both 3 microns, and they are arranged on the top metal layer (RDL layer). The spacing between metal trace 633 and metal trace 631 is 3 microns, and the spacing between metal trace 634 and metal trace 632 is 3 microns. Transmission line 120 also includes a ground plane 635, which is arranged on the thin metal layer (ME6 layer). Ground plane 635 is used to shield metal trace 631 and metal trace 632, and ground plane 635 needs to be connected to a ground node.

[0117] Figure 7 FIG. 1 is a flowchart of a clock distribution method according to some embodiments of the present disclosure. Figure 7In some embodiments, the clock distribution method includes the following steps: receiving a first voltage signal V1 (step 710); converting the first voltage signal V1 into a first current signal I1 using a voltage-to-current driver 110 (step 720); transmitting the first current signal I1 into a second current signal I2 using a transmission line 120 (step 730); relaying the second current signal I2 into a third current signal I3 using a current buffer 130 (step 740); using the inductor capacitor slot 140 as a load to convert the third current signal I3 into a second voltage signal V2 (step 750); converting the second voltage signal V2 into a third voltage signal V3 using a first capacitor driving line 150 (step 760); amplifying the third voltage signal V3 into a fourth voltage signal V4 using a first inverter buffer 160 (step 770); transmitting the second voltage signal V2 into a fifth voltage signal V5 using a second capacitor driving line 170 (step 780); and amplifying the fifth voltage signal V5 into a sixth voltage signal V6 using a second inverter buffer 180 (step 790).

[0118] Although the technical contents of the present disclosure have been disclosed as above in the form of preferred embodiments, they are not intended to limit the present disclosure. Any slight changes and modifications made by any person skilled in the art without departing from the concept of the present disclosure should be included in the scope of the present disclosure. Therefore, the scope of patent protection of the present disclosure shall be based on that defined in the claims.

Claims

1. A clock distribution network, comprising: a voltage-to-current driver, configured to receive a first voltage signal and output a first current signal; A transmission line, used for receiving the first current signal and outputting a second current signal; a current buffer, configured to receive the second current signal and output a third current signal; an inductor-capacitor slot, for receiving the third current signal and establishing a second voltage signal; a first capacitor driving line, for receiving the second voltage signal and outputting a third voltage signal; a first inverter buffer, configured to receive the third voltage signal and output a fourth voltage signal; a second capacitor driving line, for receiving the second voltage signal and outputting a fifth voltage signal; and A second inverter buffer is used to receive the fifth voltage signal and output a sixth voltage signal.

2. The clock distribution network of claim 1 , wherein the voltage-to-current driver comprises: Two N-type transistors are used as a common-source amplifier differential pair or a common-source amplifier pseudo differential pair.

3. The clock distribution network of claim 1 , wherein the current buffer comprises: Two N-type transistors used as a common-gate amplifier differential pair; and Two capacitors are used to provide cross coupling between the two N-type transistors.

4. The clock distribution network of claim 1 , wherein the LC slot comprises: an inductor having a center tap connected to a power node; and A capacitor is connected in parallel with the inductor.

5. The clock distribution network of claim 1 , wherein the first capacitor driving line and the second capacitor driving line each comprise: a capacitor; and A transmission line is connected in series with the capacitor.

6. A clock distribution method, comprising: receiving a first voltage signal; Converting the first voltage signal into a first current signal using a voltage-to-current driver; Transmitting the first current signal into a second current signal using a transmission line; Relaying the second current signal into a third current signal using a current buffer; Using an inductor-capacitor tank as a load to convert the third current signal into a second voltage signal; Converting the second voltage signal into a third voltage signal using a first capacitor driving line; Amplifying the third voltage signal into a fourth voltage signal by a first inverter buffer; utilizing a second capacitor driving line to transmit the second voltage signal as a fifth voltage signal; and A second inverter buffer is used to amplify the fifth voltage signal into a sixth voltage signal.

7. The clock distribution method as claimed in claim 6, wherein the voltage-to-current driver comprises: Two N-type transistors are used as a common-source amplifier differential pair or a common-source amplifier pseudo differential pair.

8. The clock distribution method as claimed in claim 6, wherein the current buffer comprises: Two N-type transistors used as a common-gate amplifier differential pair; and Two capacitors are used to provide cross coupling between the two N-type transistors.

9. The clock distribution method as claimed in claim 6, wherein the first capacitor driving line and the second capacitor driving line each comprise: a capacitor; and A transmission line is connected in series with the capacitor.

10. A clock distribution method, comprising: receiving a remote voltage signal; The remote voltage signal is converted into a local voltage signal by using a current mode transmission scheme, wherein the current mode transmission scheme includes a voltage-to-current driver, a transmission line, a current buffer and an inductor-capacitor slot, wherein the voltage-to-current driver, the transmission line, the current buffer and the inductor-capacitor slot are connected in series; Transmitting the local voltage signal to a first destination voltage signal using a voltage mode transmission scheme, the voltage mode transmission scheme comprising a first capacitor driving line and a first inverter buffer, wherein the first capacitor driving line and the first inverter buffer are connected in series; and The local voltage signal is transmitted as a second destination voltage signal using the voltage mode transmission scheme, wherein the voltage mode transmission scheme includes a second capacitor driving line and a second inverter buffer, wherein the second capacitor driving line and the second inverter buffer are connected in series.

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