1-line to 3-line ternary decoder circuit based on ternary memristor

Abstract

The present invention discloses a 1-wire-3-wire three-value decoder circuit based on a three-value memristor. The present invention comprises two groups of voltage-controlled switches and three output three-value memristors. The negative pole of the first group of voltage-controlled switches and the positive pole of the second group of voltage-controlled switches are connected to the negative pole of the input three-value memristor, and are connected to the negative poles of the three output three-value memristors through an auxiliary resistor. The positive pole of the first group of voltage-controlled switches is connected to the positive pole of the input three-value memristor and the operating voltage source, and the negative pole of the second group of voltage-controlled switches is grounded. The positive poles of the three output three-value memristors are respectively connected to a control terminal of the first group of voltage-controlled switches, and the other control terminal is respectively connected to a control terminal of the second group of voltage-controlled switches, and the other control terminal of the second group of voltage-controlled switches is connected to the positive pole of the set 1 voltage source. The present invention has a clear and simple structure, is easy to implement, and can be used for application research in many fields such as multi-value digital logic operations, and has important significance.

Description

Technical Field

[0001] The invention belongs to the technical field of circuit design, and relates to a 1-line-3-line ternary decoder circuit based on a ternary memristor. Background Art

[0002] Classic computer architecture is based on binary logic. However, in the era of artificial intelligence, it is difficult for traditional binary computers to efficiently imitate some complex functions of the human brain. Three-valued logic has more logical levels and is expected to realize more complex functions in computers. Although the same number of binary signals is easier to process than three-valued signals, three-valued signals have obvious advantages over binary signals in terms of the amount of information they carry. For example, a single signal line transmits more information, has lower circuit complexity and fewer interconnects, has stronger circuit serial and parallel computing capabilities, and has lower circuit complexity, among other advantages.

[0003] As a representative of multi-valued logic, three-valued logic was first proposed by Thomas Fowler in 1840. However, due to the lack of corresponding actual three-valued devices, the research on three-valued logic has been stagnant. As a multi-valued memristor, the three-valued memristor can show three different resistance states without using any additional devices to represent "0", "1" and "2" in three-valued logic, which creates favorable conditions for building three-valued logic circuits. Further application of three-valued memristors in digital logic circuits can further reduce circuit area, reduce circuit power consumption and increase storage density, which creates favorable conditions for realizing three-valued logic circuits.

[0004] Decoding is the reverse process of encoding. Traditional combinational logic circuits are generally obtained by cascading multiple basic logic gate circuits, using more components and more complex wiring. Compared with binary combinational logic circuits, the design of ternary combinational logic circuits is more difficult. Therefore, introducing ternary memristors into the design of combinational logic circuits and studying decoder circuits based on ternary memristors can reduce the usage rate of components and reduce circuit complexity, which has a certain promoting effect on the further development of modern information circuits. Summary of the invention

[0005] The object of the present invention is to provide a 1-line-3-line ternary decoder circuit based on a ternary memristor.

[0006] The invention comprises an operating voltage source, three output three-value memristors, six voltage-controlled switches, a set-1 voltage source, an auxiliary resistor and an input three-value memristor.

[0007] The first voltage controlled switch S De1 The negative electrode of the second voltage-controlled switch S De2 The negative electrode of the third voltage-controlled switch SDe3 The negative electrode of the fourth voltage-controlled switch S De4 The positive electrode of the fifth voltage-controlled switch S De5 The positive electrode of the sixth voltage-controlled switch S De6 After the positive electrode is connected, the input three-value memristor M in The negative electrode and one end of the auxiliary resistor R;

[0008] The first voltage controlled switch S De1 The positive electrode, the second voltage-controlled switch S De2 The positive electrode, the third voltage-controlled switch S De3 After the positive electrode is connected, the input three-value memristor M in The positive electrode of the fourth voltage-controlled switch S De4 The negative electrode of the fifth voltage-controlled switch S De5 The negative electrode of the sixth voltage-controlled switch S De6 The negative pole is grounded;

[0009] The first output ternary memristor M out1 The positive electrode is connected to the first voltage-controlled switch S De1 A control terminal of the first voltage-controlled switch S De1 The other control terminal is connected to a fourth voltage-controlled switch S De4 A control terminal;

[0010] The second output ternary memristor M out2 The positive electrode is connected to the second voltage-controlled switch S De2 A control terminal of the second voltage-controlled switch S De2 The other control terminal is connected to the fifth voltage-controlled switch S De5 A control terminal;

[0011] The third output ternary memristor M out3 The positive electrode is connected to the third voltage-controlled switch S De3 A control terminal of the third voltage-controlled switch S De3 The other control terminal is connected to the sixth voltage-controlled switch S De6 A control terminal;

[0012] The fourth voltage controlled switch S De4 The other control terminal of the fifth voltage-controlled switch S De5 The other control terminal of the sixth voltage-controlled switch S De6 The other control terminal is connected to the set 1 voltage source V Set1 The positive electrode;

[0013] The first output three-value memristor M out1The negative electrode, the second output three-value memristor M out2 The negative electrode, the third output ternary memristor M out3 The negative pole of the operating voltage source V, the negative pole of the set voltage source V Set1 The negative pole of the auxiliary resistor R is grounded.

[0014] The three-valued logic in this circuit is a multi-valued logic with three different logic states: "0", "1" and "2". The 1-line-3-line three-valued decoder circuit designed by the present invention uses the resistance value of the memristor as the logic state variable. The resistance states of the memristor corresponding to the three logic values ​​are R H , R M and R L , where R H Represents logic "0", R M Represents logic "1", R L Indicates logic "2". Input memristor M in Logic "0", logic "1" and logic "2" can be input according to actual needs. The initial resistance values ​​of the three output memristors are R H .

[0015] The operation of the three-value encoder is driven by an excitation voltage source V, and its working process can be divided into two stages. The first stage is the initial stage, V outputs a small initial voltage V Init , which is used to measure the initial state of each memristor. The second stage is the operation stage, during which V will output a larger operating voltage V Run Used to perform logical operations.

[0016] Set voltage source V Set1 The output set 1 voltage completes the set “1” operation of the output memristor. De1 -S De6 It is a voltage-controlled switch, and the switch is turned on only when the applied control voltage exceeds its threshold voltage.

[0017] The present invention designs a novel 1-line-3-line ternary decoder circuit based on a ternary memristor, and its logic variables are all represented by the resistance value of the memristor. The 1-line-3-line ternary decoder designed by the present invention does not need to cascade basic ternary logic gates, and can directly decode one ternary signal into three binary signals only through circuit design, and the circuit complexity is low. The present invention has a clear and simple structure, is easy to implement, and can be used for application research in many fields such as multi-value digital logic operations, and has important significance. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 The present invention is a schematic diagram of a 1-line-3-line ternary decoder circuit based on a ternary memristor. DETAILED DESCRIPTION

[0019] To enable those skilled in the art to better understand the solution of the present invention, the circuit proposed by the present invention will be further described below in conjunction with the accompanying drawings and specific embodiments.

[0020] The ternary memristor used in the 1-line - 3-line ternary decoder circuit based on the ternary memristor is a voltage threshold type ternary memristor constructed by a parallel connection method on the basis of a voltage threshold type binary memristor.

[0021] The constructed ternary memristor has voltage threshold characteristics, and its two threshold voltages are v th1 = 1V and v th2 = 1.2V, and R L , R M and R H correspond to three different resistance states of the model from low to high, with magnitudes of 100Ω, 400Ω, and 800Ω respectively. When the voltage v ≥ 1.2V, the memristor is set to R L . When 1V ≤ v < 1.2V, if the resistance value of the memristor is R H at this time, it will quickly drop to R M , otherwise it will remain in its original state. When -1V < v < 1V, the memristor will continue to maintain its original state. When -1.2V < v ≤ -1V, if the resistance value of the memristor is less than R M at this time, it will increase to R M , otherwise it will not change. When v ≤ -1.2V, the resistance value of the memristor is set to R H .

[0022] The truth table of the 1-line - 3-line ternary decoder designed by the present invention is shown in the following table, where X represents the input signal of the decoder, and Y0, Y1, and Y2 represent the outputs of the decoder.

[0023]

[0024] When the input X is logic "0", the outputs Y0, Y1, and Y2 are logic "1", "0", "0".

[0025] When the input X is logic "1", the outputs Y0, Y1, and Y2 are logic "0", "1", "0".

[0026] When the input X is logic "2", the outputs Y0, Y1, and Y2 are logic "0", "0", "1".

[0027] The specific circuit structure of a 1-line - 3-line ternary decoder based on the ternary memristor designed by the present invention is as shown in Figure 1As shown, it includes: an operating voltage source, three output three-value memristors, six voltage-controlled switches, a set-1 voltage source, an auxiliary resistor, and an input three-value memristor.

[0028] The first voltage controlled switch S De1 The negative electrode of the second voltage-controlled switch S De2 The negative electrode of the third voltage-controlled switch S De3 The negative electrode of the fourth voltage-controlled switch S De4 The positive electrode of the fifth voltage-controlled switch S De5 The positive electrode of the sixth voltage-controlled switch S De6 After the positive electrode is connected, the input three-value memristor M in The negative electrode and one end of the auxiliary resistor R;

[0029] The first voltage controlled switch S De1 The positive electrode, the second voltage-controlled switch S De2 The positive electrode, the third voltage-controlled switch S De3 After the positive electrode is connected, the input three-value memristor M in The positive electrode of the fourth voltage-controlled switch S De4 The negative electrode of the fifth voltage-controlled switch S De5 The negative electrode of the sixth voltage-controlled switch S De6 The negative pole is grounded;

[0030] The first output ternary memristor M out1 The positive electrode is connected to the first voltage-controlled switch S De1 A control terminal of the first voltage-controlled switch S De1 The other control terminal is connected to a fourth voltage-controlled switch S De4 A control terminal;

[0031] The second output ternary memristor M out2 The positive electrode is connected to the second voltage-controlled switch S De2 A control terminal of the second voltage-controlled switch S De2 The other control terminal is connected to the fifth voltage-controlled switch S De5 A control terminal;

[0032] The third output ternary memristor M out3 The positive electrode is connected to the third voltage-controlled switch S De3 A control terminal of the third voltage-controlled switch S De3 The other control terminal is connected to the sixth voltage-controlled switch S De6 A control terminal;

[0033] The fourth voltage controlled switch S De4The other control terminal of the fifth voltage-controlled switch S De5 The other control terminal of the sixth voltage-controlled switch S De6 The other control terminal is connected to the set 1 voltage source V Set1 The positive electrode;

[0034] The first output three-value memristor M out1 The negative electrode, the second output three-value memristor M out2 The negative electrode, the third output ternary memristor M out3 The negative pole of the operating voltage source V, the negative pole of the set voltage source V Set1 The negative pole of the auxiliary resistor R is grounded.

[0035] The operation of the 1-wire-3-wire ternary decoder based on ternary memristor is driven by an excitation voltage source V, and its working process can be divided into two stages. The first stage is the initial stage, which corresponds to 0-10ms. In this stage, V outputs a small initial voltage V Init , used to measure the initial state of each memristor, and measure the resistance of the memristor by reading the voltage across the memristor and the current passing through. The value of this measured voltage should be small so that the voltage division on each memristor does not exceed the set threshold voltage. The second stage is the operation stage, corresponding to 10-20ms, during which V will output a larger operation voltage V Run Used to complete logical operations. The initial voltage V of the 1-line-3-line three-value decoder Init is 0.5V, the operating voltage V Run 1.2V, S De1 -S De6 The threshold voltages are set to 0.79V, 0.59V, 0.23V, 0.39V, 0.59V, and 0.9V respectively.

[0036] The circuit operation phase of the 1-line-3-line ternary decoder based on the ternary memristor designed by the present invention can be specifically divided into the following three situations:

[0037] When the input is logic "0", the input memristor M in =800Ω. At this time, the voltage divider V on the auxiliary resistor R bc is 0.4V, input memristor M in The voltage divider V ab is 0.8V, control switch S De1 and S De4 The divided voltage of the switch S exceeds its threshold voltage. De1 and S De4 conduction, that is, the voltage source V Set1 Output voltage th1 The output memristor M out1Set to 400Ω. At this time, the logic gate outputs "100".

[0038] When the input is logic "1", the input memristor M in =400Ω. At this time, the voltage divider V on the auxiliary resistor R bc Equal to the input memristor M in The voltage divider V ab Equal to 0.6V. Control switch S De2 , S De3 , S De4 and S De5 The divided voltage of the switch S exceeds its threshold voltage. De2 , S De3 , S De4 and S De5 is turned on, but only the output memristor M out2 Can be connected to a voltage source V Set1 , is set to 400Ω. At this time, the logic gate outputs "010".

[0039] When the input is logic "2", the input memristor M in =100Ω. At this time, the voltage divider V on the auxiliary resistor R bc is 0.96V, input memristor M in The voltage divider V ab is 0.24V. Control switch S De3 , S De4 , S De5 and S De6 The divided voltage of the switch S exceeds its threshold voltage. De3 , S De4 , S De5 and S De6 Both are turned on, but only the output memristor M out3 Can be connected to a voltage source V Set1 , is set to 400Ω. At this time, the logic gate outputs "001".

[0040] Those skilled in the art should realize that the above embodiments are only used to verify the present invention, and are not intended to limit the present invention. As long as they are within the scope of the present invention, any changes or modifications to the above embodiments will fall within the protection scope of the present invention.

Claims

1. A 1-line to 3-line ternary decoder circuit based on a ternary memristor, characterized in that: include: It includes an operating voltage source, three output three-value memristors, six voltage-controlled switches, a set-1 voltage source, an auxiliary resistor, and an input three-value memristor; The first voltage controlled switch S De1 The negative electrode of the second voltage-controlled switch S De2 The negative electrode of the third voltage-controlled switch S De3 The negative electrode of the fourth voltage-controlled switch S De4 The positive electrode of the fifth voltage-controlled switch S De5 The positive electrode of the sixth voltage-controlled switch S De6 After the positive electrode is connected, the input three-value memristor M in The negative electrode and one end of the auxiliary resistor R; The first voltage controlled switch S De1 The positive electrode, the second voltage-controlled switch S De2 The positive electrode, the third voltage-controlled switch S De3 After the positive electrode is connected, the input three-value memristor M in The positive electrode of the fourth voltage-controlled switch S De4 The negative electrode of the fifth voltage-controlled switch S De5 The negative electrode of the sixth voltage-controlled switch S De6 The negative pole is grounded; The first output ternary memristor M out1 The positive electrode is connected to the first voltage-controlled switch S De1 A control terminal of the first voltage-controlled switch S De1 The other control terminal is connected to a fourth voltage-controlled switch S De4 A control terminal; The second output ternary memristor M out2 The positive electrode is connected to the second voltage-controlled switch S De2 A control terminal of the second voltage-controlled switch S De2 The other control terminal is connected to the fifth voltage-controlled switch S De5 A control terminal; The third output ternary memristor M out3 The positive electrode is connected to the third voltage-controlled switch S De3 A control terminal of the third voltage-controlled switch S De3 The other control terminal is connected to the sixth voltage-controlled switch S De6 A control terminal; The fourth voltage controlled switch S De4 The other control terminal of the fifth voltage-controlled switch S De5 The other control terminal of the sixth voltage-controlled switch S De6 The other control terminal is connected to the set 1 voltage source V Set1 The positive electrode; The first output ternary memristor M out1 The negative electrode, the second output three-value memristor M out2 The negative electrode, the third output ternary memristor M out3 The negative pole of the operating voltage source V, the negative pole of the set voltage source V Set1 The negative pole of the auxiliary resistor R is grounded.

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