Phase-shift current sharing and crosstalk suppression driving circuit for multi-tube parallel power device

Abstract

The invention discloses a multi-tube parallel power device phase shift type current sharing and crosstalk suppression drive circuit which is composed of a crosstalk suppression unit, a current balancing unit, a control response unit and a function switching unit. Wherein the crosstalk suppression unit generates a control signal for suppressing the crosstalk voltage of the parallel power device and shields the interference of the current balancing unit; the current balancing unit generates a control signal for balancing the dynamic current of the parallel power device and shields the interference of the crosstalk suppression unit; the control response unit is used for realizing crosstalk active clamping or current active equalization; and the mode switching unit realizes automatic switching of a crosstalk suppression function or a current equalization function according to configuration. Parallel device grid driving signal feedback is introduced, crosstalk voltage active clamping and dynamic current active balancing are achieved through a logic circuit, and the parallel expansibility is high; an exclusive-OR gate is adopted to accurately identify synchronous or asynchronous information of driving signals of the parallel devices, and various different gate sequential modes in parallel application of the hybrid devices can be compatible.

Description

Technical Field

[0001] The present invention relates to a phase-shifted current sharing and crosstalk suppression drive circuit for multi-tube parallel power devices, belonging to the technical field of power electronic device drives. Background Art

[0002] GaN HEMT devices provide opportunities for realizing high-efficiency and high-power-density power electronic converters due to advantages such as fast switching speed, low on-resistance, and high operating voltage, and are expected to be widely used in high-power scenarios such as AI data centers, electric vehicles, and low-altitude economy in the future. Currently, limited by manufacturing processes and manufacturing costs, the improvement of the current density of a single device has gradually become a bottleneck. Moreover, at the same current level, the cost and efficiency of a single high-current device are not necessarily better than those of multiple small-current devices in parallel. Therefore, parallel connection of multiple devices has become an effective solution for high-power applications.

[0003] However, due to reasons such as parameter differences of GaN HEMT devices, asymmetric circuit layouts, and propagation delays of drive chips, current imbalance is very likely to occur when multiple GaN HEMT devices are connected in parallel, leading to reliability problems such as overheating and damage of devices and gate oscillation breakdown. In addition, for GaN HEMT devices with faster switching, narrower dead zones, and lower thresholds, gate drive signal delays will not only cause more serious current imbalance but also more crosstalk spikes, resulting in further decline in the reliability of devices and systems. In fact, the gate signal delays of parallel devices not only come from the above passive effects but also from the active design of different gate timing patterns, which have been proven to be effective methods for improving system efficiency in both single-device parallel connection and hybrid-device parallel connection. Therefore, special attention needs to be paid to whether the gate timing is synchronized when GaN HEMT devices are applied in parallel.

[0004] In existing solutions, including but not limited to parallel connection of single GaN HEMT devices, parallel connection of SiC MOSFET and Si IGBT hybrid devices, gate timing synchronous mode, gate timing asynchronous mode, the basic technical paths for current balancing mainly include: 1) screening devices with consistent parameters, 2) maintaining a symmetric circuit layout, 3) adding passive components, and 4) designing an active gate driver. Among them, screening devices and symmetric layout are called passive balancing, and the two can fundamentally solve the problem of current imbalance. However, device parameters can only be similar and will degenerate to varying degrees over working time. In addition, when more than two devices are connected in parallel, it is very difficult to make the circuit layout completely symmetric. Therefore, in actual design, passive balancing cannot be completely relied on, and active balancing methods such as adding passive components or designing an active gate driver need to be adopted.

[0005] The design of passive components refers to inserting differential-mode or common-mode inductors at the drain, source, or gate of the device to achieve automatic current balancing. This method is very simple and effective and is not limited by the gate timing mode. However, in the current solution, the minimum inductor size is still much larger than the size of the largest 650V 60A GaN HEMT device, which is not conducive to the realization of high power density and is not applicable to scenarios with strict requirements for the volume of power electronic converters. Moreover, introducing inductors into the power loop and the drive loop will inevitably increase voltage oscillation and core loss. The active gate drive design refers to achieving automatic current balancing through the closed-loop control of gate voltage, resistance, and current. Although this method is slightly more complex than the passive component solution, it is easy to integrate and design, better meets the requirements of high power density, and is more conducive to giving full play to the small volume advantage of GaN HEMT devices. However, the existing closed-loop active drive solutions for gate voltage, resistance, and current do not fully consider the impact of gate timing on GaN HEMT devices. Therefore, it is difficult to effectively expand to the parallel mode with different gate timings, and the new crosstalk problem introduced by asynchronous gate timings has not been fully solved. Summary of the Invention

[0006] The purpose of the present invention is to provide a phase-shifted current sharing and crosstalk suppression drive circuit for multi-tube parallel power devices. Through the closed-loop control of different gate timing modes, dynamic current balancing and crosstalk voltage suppression under different gate timing modes can be achieved when GaN HEMT devices are applied in parallel.

[0007] The purpose of the present invention is achieved through the following technical solutions:

[0008] A phase-shifted current sharing and crosstalk suppression drive circuit for multi-tube parallel power devices, comprising: a crosstalk suppression unit, a current balancing unit, a control response unit, and a function switching unit;

[0009] The crosstalk suppression unit includes a single-channel configurable gate E2, a single-channel exclusive OR gate X2, a single-channel NOT gate I1, and a single-channel AND gate A3. Two input terminals of the configurable gate E2 are respectively connected to the output terminal of the drive signal V1 and the output terminal Y of the configurable gate E1 of the function switching unit, and the output terminal is connected to the input terminal of the exclusive OR gate X2 for shielding the logic signal interference of the current balancing unit, and the enable terminal is connected to the freewheeling diode judgment signal;

[0010] The other input terminal of the exclusive OR gate X2 is connected to the output terminal of the drive signal V1, and the output terminal is connected to the common gate of the control signal response unit N-PMOS to provide a crosstalk suppression signal when the parallel gate signals are asynchronous and the power device Q1 is used as a control tube; the input terminal of the NOT gate I1 is connected to the output terminal Y of E1, and the output terminal is connected to one input terminal of the AND gate A3; the other input terminal of the AND gate A3 is connected to the freewheeling diode judgment signal, and together with the configurable gate E2, it is used to provide a crosstalk suppression control signal when the parallel gate signals are asynchronous or synchronous and the power device Q1 is used as a freewheeling diode.

[0011] The current equalization unit includes a single-channel AND gate A2 and a single-channel XOR gate X1. Two input terminals of the AND gate A2 are respectively connected to the output terminal of the driving signal V1 and the output terminal Y of the configurable gate E1, and the output terminal is connected to the input terminal of the XOR gate X1, which is used to shield the logic signal of the crosstalk suppression unit. The other input terminal of the XOR gate X1 is connected to the output terminal of the driving signal V1, and the output terminal is connected to the common gate of the control response unit N-PMOS, so as to provide a current equalization control signal for parallel devices when the parallel gate signals are synchronized, but the device switching transients are asynchronous due to objective factors such as device parameter dispersion, circuit board parasitic parameters, and driving chip propagation delay.

[0012] The control response unit includes an NMOS transistor Mn1 and a PMOS transistor Mp1. The common gate of Mn1 and Mp1 is connected to the output terminals of the XOR gates X1, X2 and the AND gate A3, so as to realize the crosstalk suppression or current equalization function according to the logic output of the crosstalk suppression unit or the current equalization unit. The common drains of Mn1 and Mp1 are connected to the gate of the power device Q1. The source of Mn1 is connected to the source of Q1, the source of Mp1 is connected to one end of the gate resistor Rg1, and a driving loop parasitic inductor Lg1 is also connected between the source of Mp1 and the gate resistor Rg1.

[0013] The function switching unit includes a configurable gate E1, a high-speed digital comparator U1, sampling resistors R1 and Rs. The non-inverting input terminal of U1 is connected to the middle of the series connection of R1 and Rs, the inverting input terminal is connected to the reference voltage Ref, and the output terminal is connected to the enable terminal of E1, which is used to realize the automatic switching between the AND gate / OR gate. The number of input terminals of E1 matches the number of parallel power devices. Multiple input terminals are respectively connected to the output terminals of the driving signals of each parallel device, and the output terminal is connected to the inputs of the current equalization unit and the crosstalk suppression unit in each device drive.

[0014] Preferably, when the power device Q1 is only used as a control tube, such as the upper tube of the Buck circuit, the NOT gate I1 and the AND gate A3 can be omitted; when the power device Q1 is only used as a freewheeling diode, such as the lower tube of the Buck circuit, the configurable gate E2 and the XOR gate X2 can be omitted.

[0015] Preferably, the single parallel power device with gate asynchronous timing operates in an alternating asynchronous state to achieve thermal balance of the parallel devices.

[0016] Preferably, all the logic gates can be designed in a single-channel multi-chip discrete form or in a multi-channel single-chip integrated form.

[0017] Preferably, when the breakdown voltages of Mn1 and Mp1 are greater than the gate-source voltage Vgs of the power device Q1, the conduction voltage drop of the body diode is less than 0.4V, and the requirement for the loss of the drive circuit is not high, Mp1 can be omitted.

[0018] Preferably, the drive circuit is applicable to power devices such as GaN HEMT, SiC MOSFET, and Si IGBT, and is applicable to situations such as parallel connection of the same device and parallel connection of hybrid devices, and is applicable to the gate signal timing working mode of any parallel devices.

[0019] The beneficial effects of the present invention are as follows:

[0020] 1. An active clamping method with zero-voltage turn-off is adopted to suppress the crosstalk spikes generated in the asynchronous timing mode of the gates of parallel devices. While avoiding the risk of mis-conduction of the device, it eliminates the adverse effects of negative-voltage turn-off on GaN HMET devices in the traditional scheme, and improves the reliability of the device and the system.

[0021] 2. An active equalization method with time difference elimination is adopted to reduce the current imbalance generated in the gate timing synchronization mode of parallel devices. While avoiding the large volume of passive inductors in high-power density applications, it eliminates the limitation of high bandwidth in traditional sampling methods.

[0022] 3. A digital-analog hybrid hardware double closed-loop method of the gate loop and the power loop is adopted to realize the automatic switching of the gate asynchronous and synchronous timing functions. While avoiding complex algorithm calculations by the control chip, it speeds up the loop response speed.

[0023] 4. A freewheeling diode judgment logic is introduced to realize the separate suppression of different crosstalk voltages when the power device acts as a control tube and a freewheeling tube respectively.

[0024] 5. All functions are realized by a logic circuit method. The circuit structure is simple, which is easy for parallel expansion design and integrated design of multiple devices, and is beneficial to giving full play to the small-size advantage of GaN HEMT devices.

[0025] 6. The present invention is not limited to different gate timing modes, and the applicable scenarios include single multi-device parallel connection, hybrid multi-device parallel connection, etc. Description of the Drawings

[0026] Figure 1 It is a schematic circuit diagram when two power devices of the present invention are connected in parallel.

[0027] Figure 2 It is a circuit diagram when two GaN HEMT devices in Example 1 are connected in parallel and act as control tubes.

[0028] Figure 3 It is the specific crosstalk suppression and current equalization working waveforms in the circuit of Example 1.

[0029] Figure 4 Circuit diagram when two GaN HEMT devices in Example 2 are connected in parallel and used as a freewheeling diode.

[0030] Figure 5 Specific crosstalk suppression and current equalization working waveforms in the circuit of Example 2.

[0031] Figure 6 Schematic diagram of different gate timing modes applicable to the drive circuit of the present invention.

[0032] Figure 7 Method for expanding the logic circuit of the function switching unit when two or more devices are connected in parallel. Detailed implementation manners

[0033] To make the purpose, technical solutions and advantages of the implementation of the present invention clearer, the technical solutions in the embodiments of the present invention will be described in more detail below with reference to the accompanying drawings in the embodiments of the present invention. In the drawings, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The described embodiments are some, but not all, of the embodiments of the present invention.

[0034] All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention. Figure 1 Shows a schematic diagram of the circuit structure when two power devices of the present invention are connected in parallel.

[0035] Example 1

[0036] This embodiment provides a half-bridge circuit based on two GaN HEMT power devices connected in parallel and used as a control tube. The circuit structure is as Figure 2 shown, including an upper bridge arm circuit and a lower bridge arm circuit. The multi-tube parallel power device phase-shifted current sharing and crosstalk suppression drive circuit of the present invention is applied to the lower bridge arm GaN HEMT device, and the upper bridge arm adopts a traditional drive method.

[0037] In the lower bridge arm circuit, as Figure 2 shown, taking the drive of GaN HEMT device Q1 as an example, the multi-tube parallel power device phase-shifted current sharing and crosstalk suppression drive circuit of the present invention includes a multi-tube parallel power device phase-shifted current sharing and crosstalk suppression drive circuit, including: a crosstalk suppression unit, a current equalization unit, a control response unit and a function switching unit;

[0038] The crosstalk suppression unit includes a single-channel configurable gate E2, a single-channel exclusive-OR gate X2, a single-channel inverter I1, and a single-channel AND gate A3. Two input terminals of the configurable gate E2 are respectively connected to the output terminal of the drive signal V1 and the output terminal Y of the configurable gate E1 of the function switching unit. The output terminal is connected to the input terminal of the exclusive-OR gate X2, which is used to shield the logic signal interference of the current equalization unit and enable the terminal to be connected to the freewheeling diode judgment signal.

[0039] The other input terminal of the exclusive-OR gate X2 is connected to the output terminal of the drive signal V1, and the output terminal is connected to the common gate of the control signal response unit N-PMOS, so as to provide a crosstalk suppression signal when the power device Q1 is used as a control tube when the parallel gate signals are asynchronous. The input terminal of the inverter I1 is connected to the output terminal Y of E1, and the output terminal is connected to one input terminal of the AND gate A3. The other input terminal of the AND gate A3 is connected to the freewheeling diode judgment signal, and it works together with the configurable gate E2 to provide a crosstalk suppression control signal when the power device Q1 is used as a freewheeling diode when the parallel gate signals are asynchronous or synchronous.

[0040] The current equalization unit includes a single-channel AND gate A2 and a single-channel exclusive-OR gate X1. Two input terminals of the AND gate A2 are respectively connected to the output terminal of the drive signal V1 and the output terminal Y of the configurable gate E1, and the output terminal is connected to the input terminal of the exclusive-OR gate X1, which is used to shield the logic signal of the crosstalk suppression unit. The other input terminal of the exclusive-OR gate X2 is connected to the output terminal of the drive signal V1, and the output terminal is connected to the common gate of the control response unit N-PMOS, so as to provide a current equalization control signal for the parallel devices when the parallel gate signals are synchronous but the device switching transients are asynchronous due to objective factors such as device parameter dispersion, circuit board parasitic parameters, and drive chip propagation delay.

[0041] The control response unit includes an NMOS transistor Mn1 and a PMOS transistor Mp1. The common gate of Mn1 and Mp1 is connected to the output terminals of the exclusive-OR gates X1, X2, and the AND gate A3 to realize the crosstalk suppression or current equalization function according to the logic output of any one of the circuit units in claims 2-3. The common drain of Mn1 and Mp1 is connected to the gate of the power device Q1. The source of Mn1 is connected to the source of Q1, and the source of Mp1 is connected to one end of the gate resistor Rg1, where Lg1 is the parasitic inductance of the drive loop.

[0042] The function switching unit includes a configurable gate E1, a high-speed digital comparator U1, sampling resistors R1 and Rs. The non-inverting input terminal of U1 is connected to the middle of the series connection of R1 and Rs, the inverting input terminal is connected to the reference voltage Ref, and the output terminal is connected to the enable terminal of E1 to realize the automatic switching between the AND gate / OR gate. Two input terminals of E1 are respectively connected to the output terminals Vs1 and Vs2 of the drive signals of two parallel devices, and the output terminal is connected to the inputs of the current equalization unit and the crosstalk suppression unit in each device drive.

[0043] As shown Figure 2 in the figure, another parallel power device Q2 adopts a multi-tube parallel power device phase-shifted current sharing and crosstalk suppression drive circuit with the same structure.

[0044] Next, in combination with Figure 2 the circuit shown Figure 3 and the waveform shown

[0045] when the parallel devices are control tubes and the gate drive signals are asynchronous mode and synchronous mode respectively, the working principle of the multi-tube parallel power device phase-shifted current sharing and crosstalk suppression drive circuit of the present invention is described as follows:

[0046] In the stage of t0~t5, the drive signal is in asynchronous mode. Taking light load as an example, at this time, the U1 digital comparator outputs a low level, and the OR logic can be configured for gate E1. The following is the specific analysis in this mode.

[0047] In the stage of t1~t2, device Q1 conducts first, and device Q2 is still in the off state. Id1 rises rapidly. Since the load current is small, the overshoot current is not large enough to have a great impact on Q1 in a short time. At this time, the voltage at the switching node 7 (SW) drops rapidly from the bus voltage to zero, and a Miller current is generated at both ends of the gate-drain capacitance Cgd2 of Q2. After flowing through the gate resistance Rg2 and the gate-source capacitance Cgs2 of Q2, a negative crosstalk voltage spike is generated at both ends of the gate-source, as Figure 3 shown by the dotted line at the negative crosstalk spike indication. Since the drive signals of Q1 and Q2 are inconsistent, the output Y of the OR logic E1 is a signal including any conduction process of Q1 and Q2. Therefore, the exclusive-OR logic X4 in the drive circuit of the device with a low drive signal, that is, Q2, outputs a high level and remains high until Q2 conducts and is pulled low. Since the negative crosstalk spike occurs during the asynchronous time of the drive signals of Q1 and Q2, the high level output by X4 drives the NMOS transistor Mn2 to conduct, providing a low-impedance path for the displacement current and reducing the negative crosstalk spike, as Figure 3 shown by the solid line at the negative crosstalk spike indication. During this process, the OR logic E3 only serves as a transmission gate for the OR logic E1, that is, the signal at node 5 is consistent with the Y signal. And since the output at the output end of the AND logic A4, that is, node 4, generates an output that is exactly the same as the drive signal of Q2, the exclusive-OR logic X3 output is always zero, avoiding interference with the X4 logic. In addition, for device Q1, the output Y signal of E1 is always synchronized with the Vs1 signal. Therefore, the voltages at nodes 1 and 2 are also synchronized with the Vs1 signal, that is, the outputs of X1 and X2 are both zero, and the PMOS transistor Mp1 conducts. The voltage of the driver V1 drives Q1 to remain conducting through Mp1.

[0048] During the t2 - t3 stage, both devices Q1 and Q2 are conducting. The load current is shared by Q1 and Q2 together, and the equivalent on - resistance is 1 / 2 of that of a single device. Moreover, Q2 achieves soft - switching and the switching loss is almost zero. Therefore, compared with the traditional method of reducing the number of phases, the multi - transistor parallel phase - shift method reduces the conduction loss under light load, which helps to improve the light - load efficiency of the system.

[0049] During the t3 - t4 stage, device Q1 turns off first, and Q2 remains conducting. Id2 rapidly rises from 1 / 2 of the load current to the load current, and the current overshoot is less than the maximum current limit of a single device. The voltage at the switching node 7 only rises when Q2 also turns off, and a positive crosstalk voltage is generated across the gate - source terminals of Q1, as Figure 3 shown by the dotted line at the positive crosstalk spike indication. Similar to the t1 - t2 stage, during this process, X2 in the driving circuit of Q1 generates a logic - high output, controlling the NMOS transistor Mn1 to conduct, providing a low - impedance path for the Miller current generated by the gate - drain capacitance Cgd1 of Q1, reducing the positive crosstalk spike, as Figure 3 shown by the solid line at the positive crosstalk spike indication. The specific process of its logic implementation will not be elaborated further.

[0050] During the t5 - t9 stage, the driving signals are in the synchronous mode. Taking heavy load as an example, at this time, the U1 digital comparator outputs a high level, and the configurable gate E1 is an AND logic. The following is the specific analysis in this mode.

[0051] During the t5 - t6 stage, both devices Q1 and Q2 are in the off state, and the logic outputs of X1, X2, A3, X3, X4, and A4 are all low, that is, Vc1 and Vc2 are 0V. Therefore, the driving circuit does not work.

[0052] During the t6 - t7 stage, the control signals of devices Q1 and Q2 are in the synchronous mode. However, due to objective factors such as the propagation delay of the driving chip, the parasitic parameters of the circuit board wiring, or the asymmetry of the driving loop layout, there is an asynchronous phenomenon when the driving signals reach the gate - source terminals of different devices, which may lead to the problem of current imbalance and even exceed the maximum current limit of a single device, as Figure 3As shown by the dotted line in the driving signal synchronization mode, it will further cause reliability problems. For GaN HEMT devices with faster switching speeds, this problem needs to be given extra attention. Assume that Q1 conducts first in this stage and Q2 is still in the off state. Id1 rises rapidly. Since the load current is large and has exceeded the maximum current limit of a single device, device Q1 will bear the entire load current and is extremely prone to thermal failure. Since the driving signals of Q1 and Q2 are inconsistent, the output Y of logic E1 is a signal containing the simultaneous conduction process of Q1 and Q2. Therefore, for the device with a high driving signal, that is, the exclusive-OR logic X1 in the driving circuit of Q1 outputs a high level and remains high until Q2 conducts and pulls it low. The high level output by X1 controls Mn1 to conduct, and the gate-source voltage of Q1 is zero, and the device turns off. During this process, although the output of driver V1 is high at this time, since Mp1 is off, its current will not flow through the gate resistor Rg1 to generate additional gate losses. In addition, AND logic A2 only serves as a transmission gate for E1, that is, the signal at node 1 is the same as the Y signal, and the output of OR logic E2 at node 2 generates an output that is exactly the same as the driving signal of Q1. Therefore, the output of exclusive-OR logic X2 is always zero, avoiding interference with the X1 logic. Until Q2 also conducts and the output of X1 is pulled low, Mn1 turns off, Mp1 conducts, and the gate-source signals of Q1 and Q2 rise synchronously, thereby achieving current balance, as Figure 3 shown by the solid line in the driving signal synchronization mode.

[0053] In the stage of t7 - t8, both devices Q1 and Q2 are conducting, and the load current is borne by Q1 and Q2 together. The equivalent on-resistance is 1 / 2 of that of a single device, and the conduction loss is reduced, which helps to improve the heavy-load efficiency of the system.

[0054] In the stage of t8 - t9, assume that device Q1 turns off first and Q2 is still in the conducting state. Id2 rises rapidly. Therefore, Q2 will bear the entire load current and is extremely prone to thermal failure. The logic of the driving circuit for achieving current balance in this stage is similar to that in the stage of t6 - t7 and will not be elaborated here.

[0055] In addition, since the asynchronous stage of the driving signal is obtained by the OR logic result of the gate signals of the parallel devices and the exclusive-OR logic of the gate signal of each device, it executes the logic of "pull down whoever is low", while the synchronous stage of the driving signal is obtained by the AND logic result of the gate signals of the parallel devices and the exclusive-OR logic of the gate signal of each device, so it executes the logic of "pull down whoever is high". Both are independent of the front-back order and mode of the gate timing. Therefore, the crosstalk suppression and current balance methods of the driving circuit described in the present invention are applicable Figure 6 to various different gate timing modes shown.

[0056] Embodiment 2

[0057] This embodiment provides a half-bridge circuit based on two parallel GaN HEMT power devices as freewheeling diodes, and its circuit structure is asFigure 4 As shown, it includes an upper bridge arm circuit and a lower bridge arm circuit. The phase-shifted current sharing and crosstalk suppression driving circuit of the multi-transistor parallel power device of the present invention is applied to the two GaN HEMT devices in the lower bridge arm, and the upper bridge arm adopts the traditional driving method.

[0058] The following combination Figure 4 The circuit shown and Figure 5 The waveforms shown illustrate the operating principle of the phase-shifted current sharing and crosstalk suppression driving circuit for multi-transistor parallel power devices of the present invention when the parallel devices are freewheeling transistors and the gate drive signals are in asynchronous mode and synchronous mode respectively:

[0059] When the parallel device is a freewheeling diode, device Q3 is in the complementary switching state of devices Q1 and Q2, and the freewheeling diode judgment signal is always high. At this time, the configurable gates E2 and E3 are both AND logic.

[0060] Similarly, during the t0 to t5 phase, the drive signal is in asynchronous mode. Taking light load as an example, the U1 digital comparator outputs a low level at this time, and the gate E1 can be configured as OR logic. The following is a specific analysis of this mode.

[0061] During the period t0 to t1, the voltage at the switch node 7 (SW) decreases as the upper arm Q3 device turns off. At this time, due to the existence of dead time, both Q1 and Q2 are in the off state. Different from the cause of crosstalk generated by the control tube, the negative crosstalk voltage spike appears at the gates of Q1 and Q2 at the same time, such as Figure 5 The negative crosstalk peak is indicated by the dotted line. At this time, the voltage at node 3 is the inverse of the Y signal output by the OR logic E1. Since the freewheeling tube judgment signal is high, that is, the voltages of Vc1 and Vc2 are high when both Q1 and Q2 are low, the NMOS tubes Mn1 and Mn2 are controlled to be turned on, thereby reducing the negative crosstalk peaks at both ends of the gate and source of Q1 and Q2, as shown in Figure 2. Figure 5 The negative crosstalk peak is indicated by a solid line. During this process, the voltages at nodes 1, 2, 4, and 5 are all zero, consistent with the gate signals of Q1 and Q2, thus preventing the influence of X1 and X2 on the output of A3.

[0062] During the period t1 to t2, the Y signal is pulled high, so the voltages at 3 and 6 are both low, and A3 and A5 are no longer effective. In addition, A2, A4, E2, and E3 are all in AND logic, so the voltages at 1, 2, 4, and 5 remain consistent with the gate signals of Q1 and Q2, and X1 and X2 remain low.

[0063] During the t2~t3 and t3~t4 stages, the logic function of the driving circuit is the same as that during the t1~t2 stage and will not be further described.

[0064] During the t4 to t5 phase, the logic function of the driving circuit is the same as that during the t0 to t1 phase and will not be further described.

[0065] Similarly, in the stages of t5 to t9, the driving signal is in the synchronous mode. Taking the heavy load as an example, at this time, the digital comparator of U1 outputs a high level, and the configurable gate E1 is in the AND logic. The following is the specific analysis in this mode.

[0066] In the stages of t5 to t6, since the reason for the crosstalk of the freewheeling diode has nothing to do with whether the gate driving signal is synchronous, there will also be corresponding crosstalk voltage spikes under heavy load. The difference is that under heavy load in the synchronous mode, the load current is larger and the peak value of the crosstalk voltage is greater. However, the logic function of the driving circuit is still the same as that in the stages of t0 to t1. And because the on-resistances of NMOS transistors Mn1 and Mn2 are small enough, the crosstalk suppression effect has little to do with the magnitude of the load current. Therefore, the implementation process of crosstalk suppression will not be elaborated here.

[0067] In the stages of t6 to t7, the driving signals at both ends of the gate-source of Q1 and Q2 are asynchronous. Assuming that Q1 conducts first, at this time, since A2, A4, E2, and E3 are all in the AND logic, the outputs of X1 and X2 are equivalent to high levels, controlling Mn1 to conduct, pulling down the voltage at both ends of the gate-source of Q1, and controlling Mp1 to turn off to avoid additional losses introduced by Rg1. The outputs of X1 and X2 remain high until Q2 conducts and then become low, realizing the synchronous conduction and current balance of Q1 and Q2. During this process, since the high levels output by X1 and X2 pull down the gate-source voltage of Q1 and keep it low at the same time as the gate-source voltage of Q2, A3 also outputs a high level to jointly control the pulling down of the gate-source voltage of Q1 and reduce the possible noise and interference.

[0068] In the stages of t7 to t8, both devices Q1 and Q2 are conducting, Vc1 and Vc2 are always low, Mp1 and Mp2 are conducting, and the voltage of driver V1 drives Q1 and Q2 to remain conducting through Mp1 and Mp2.

[0069] In the stages of t8 to t9, the logic function of the driving circuit is the same as that in the stages of t6 to t7, and will not be elaborated here.

[0070] In the stages of t9 to t10, the logic function of the driving circuit is the same as that in the stages of t5 to t6, and will not be elaborated here either.

[0071] In addition, when the number of parallel power devices is expanded to more than 2, each device adopts a multi-transistor parallel power device phase-shifted current sharing and crosstalk suppression driving circuit with the same structure, and only the circuit structure of the function switching unit needs to be slightly adjusted. Taking the case of 3 parallel devices as an example, as Figure 7 shown, E1 and E2 form a three-input one-output logic gate, and its three input terminals are respectively connected to the output terminals Vs1, Vs2, and Vs3 of the driving signals of 3 parallel devices, and the output terminal is connected to the inputs of the current balance unit and the crosstalk suppression unit in the driving of each device, and the enable terminals are commonly connected to the output terminal of the converter output sampling U1.

[0072] The above embodiments are preferred embodiments of the present invention, but the embodiments of the present invention are not limited to the above embodiments. Any other changes, modifications, substitutions, combinations, or simplifications made without departing from the spirit and principle of the present invention shall be equivalent replacement methods and are all included in the protection scope of the present invention.

Claims

1. A phase-shifted current sharing and crosstalk suppression drive circuit for multi-tube parallel power devices, comprising: A crosstalk suppression unit, a current equalization unit, a control response unit, and a function switching unit, wherein the crosstalk suppression unit generates a control signal for suppressing the crosstalk voltage of parallel power devices and shields the interference of the current equalization unit; The current equalization unit generates a control signal for equalizing the dynamic current of parallel power devices and shields the interference of the crosstalk suppression unit; The control response unit is used to implement crosstalk active clamping or current active equalization; the mode switching unit automatically switches between the crosstalk suppression or current equalization function according to the configuration.

2. The phase-shifted current sharing and crosstalk suppression drive circuit for multi-tube parallel power devices according to claim 1, wherein: The crosstalk suppression unit includes a single-channel configurable gate E2, a single-channel exclusive-OR gate X2, a single-channel inverter I1, and a single-channel AND gate A3. Two input terminals of the configurable gate E2 are respectively connected to the output terminal of the drive signal V1 and the output terminal Y of the configurable gate E1 of the function switching unit, and the output terminal is connected to the input terminal of the exclusive-OR gate X2, which is used to shield the logic signal interference of the current equalization unit. The enable terminal of E2 is connected to the freewheeling diode judgment signal; The other input terminal of the exclusive-OR gate X2 is connected to the output terminal of the drive signal V1, and the output terminal is connected to the common gate of the N-PMOS of the control signal response unit, so as to provide a crosstalk suppression signal when the parallel gate signals are asynchronous and the power device is used as a control tube. The input terminal of the inverter I1 is connected to the output terminal Y of E1, and the output terminal is connected to one input terminal of the AND gate A3. The other input terminal of the AND gate A3 is connected to the freewheeling diode judgment signal, and together with the configurable gate E2, it is used to provide a crosstalk suppression control signal when the parallel gate signals are asynchronous or synchronous and the power device is used as a freewheeling diode.

3. The phase-shifted current sharing and crosstalk suppression drive circuit for multi-tube parallel power devices according to claim 2, wherein: The current equalization unit includes a single-channel AND gate A2 and a single-channel exclusive-OR gate X1. Two input terminals of the AND gate A2 are respectively connected to the output terminal of the drive signal V1 and the output terminal Y of the configurable gate E1, and the output terminal is connected to the input terminal of the exclusive-OR gate X1, which is used to shield the logic signal of the crosstalk suppression unit. The other input terminal of the exclusive-OR gate X2 is connected to the output terminal of the drive signal V1, and the output terminal is connected to the common gate of the N-PMOS of the control response unit, so as to provide a current equalization control signal for parallel devices when the parallel gate signals are synchronous but the device switching transients are asynchronous.

4. The phase-shifted current sharing and crosstalk suppression drive circuit for multi-tube parallel power devices according to claim 3, wherein: The control response unit includes an NMOS transistor Mn1 and a PMOS transistor Mp1. The common gate of Mn1 and Mp1 is connected to the output terminals of the exclusive-OR gates X1, X2, and the AND gate A3, so as to implement the crosstalk suppression or current equalization function according to the logic output of the crosstalk suppression unit or the current equalization unit. The common drains of Mn1 and Mp1 are connected to the gate of the power device. The source of Mn1 is connected to the source of the power device. The source of Mp1 is connected to one end of the gate resistor Rg1. There is also a parasitic inductance Lg1 of the drive loop connected between the source of Mp1 and the gate resistor Rg1.

5. The phase-shifted current sharing and crosstalk suppression drive circuit for multi-tube parallel power devices according to claim 4, wherein: The function switching unit includes a configurable gate E1, a high-speed digital comparator U1, a sampling resistor R1, and Rs. The in-phase input terminal of U1 is connected to the middle point when R1 and Rs are connected in series. The anti-phase input terminal is connected to the reference voltage Ref, and the output terminal is connected to the enable terminal of E1, which is used to realize the automatic switching between AND gate and OR gate. The number of input terminals of E1 matches the number of parallel power devices. Multiple input terminals are respectively connected to the output terminals of the drive signals of each parallel device, and the output terminal is connected to the input of the current balancing unit and the crosstalk suppression unit in each device drive.

6. The phase-shifted current sharing and crosstalk suppression drive circuit for multi-tube parallel power devices according to claim 2, wherein: When the power device is only used as a control tube, the NOT gate I1 and the AND gate A3 are omitted; when the power device is only used as a freewheeling diode, the configurable gate E2 and the exclusive-OR gate X2 are omitted.

7. The phase-shifted current sharing and crosstalk suppression drive circuit for multi-tube parallel power devices according to claim 2, characterized in that: Single parallel power devices with gate asynchronous timing all operate in an alternating asynchronous state to achieve thermal balance of the parallel devices.

8. The phase-shifted current sharing and crosstalk suppression drive circuit for multi-tube parallel power devices according to claim 3, characterized in that: All logic gates adopt a single-channel multi-chip discrete design or a multi-channel single-chip integrated design.

9. The phase-shifted current sharing and crosstalk suppression drive circuit for multi-tube parallel power devices according to claim 4, characterized in that: When the breakdown voltages of Mn1 and Mp1 are greater than the gate-source voltage Vgs of the power device Q1, the forward voltage drop of the body diode is less than 0.4V, and the requirements for the loss of the drive circuit are not high, Mp1 is omitted.

10. The phase-shifted current sharing and crosstalk suppression drive circuit for multi-tube parallel power devices according to any one of claims 1-9, characterized in that: The power device is a GaN HEMT, SiC MOSFET or Si IGBT; multiple devices in parallel are the parallel connection of the same type of power device or the parallel connection of different types of power devices.

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