Chip and trimming control circuit and trimming control method thereof

Abstract

The invention provides a chip and a trimming control circuit and a trimming control method thereof, and the trimming control circuit comprises a trimming position generation unit which latches a trimming mode control signal according to a power-on signal so as to generate a trimming enable signal, and counts received trimming clock signals according to the trimming enable signal and a counting enable signal, a trimming position control signal is correspondingly output in each period of counting the trimming clock signal; and a fuse is connected between each trimming control unit and the power supply end, and whether the fuse is fused or not is controlled according to the trimming mode control signal, the corresponding trimming position control signal and the general control signal. According to the method and the device, wrong trimming caused by writing of wrong trimming codes can be avoided, so that the yield and the manufacturing cost of the chip are improved.

Description

Technical Field

[0001] The present invention relates to the field of power electronics technology, and in particular, to a chip, a trimming control circuit thereof, and a trimming control method. Background Art

[0002] The performance of chips integrated in electronic devices often directly affects whether the electronic devices can achieve the predetermined functions. Among them, errors caused by processes such as chip manufacturing and chip packaging will cause deviations between the true test values and the design values of the chips. In order to improve the yield rate of chip production, a trimming circuit is usually added to the chip. By calculating the deviation between the true test value and the design value of the chip parameters, and designing the trimming step to obtain the number of trimming bits, and correcting the parameter deviation through the trimming circuit to ensure that the chip can still reach the design value after repeated power-on.

[0003] However, due to the one-time programming characteristic of the fuse trimming circuit, if an incorrect trimming code is written, it is easy to cause a decrease in the yield rate of the chip, thereby increasing the manufacturing cost of the chip. Summary of the Invention

[0004] In view of the above problems, the purpose of the present disclosure is to provide a chip with a pre-trimming function, a trimming control circuit thereof, and a trimming control method to avoid incorrect trimming caused by writing an incorrect trimming code.

[0005] According to a first aspect of the present disclosure, a trimming control circuit is provided, including:

[0006] A trimming bit generation unit, which receives a power-on signal, a trimming mode control signal, a trimming clock signal, and a counting enable signal, latches the trimming mode control signal according to the power-on signal to generate a trimming enable signal, counts the received trimming clock signal according to the trimming enable signal and the counting enable signal, and outputs a trimming bit control signal corresponding to each cycle of counting the trimming clock signal;

[0007] N trimming control units, each of the trimming control units is connected with a fuse between the power supply terminal, each of the trimming control units receives the corresponding trimming bit control signal, and each of the trimming control units also controls whether to blow the fuse according to the trimming mode control signal, the total control signal, and the corresponding trimming bit control signal, where N is a positive integer.

[0008] Optionally, when the power-on signal is powered on, the trimming control circuit latches the trimming mode control signal in the valid state to generate a trimming enable signal in the valid state and enters the trimming mode; after the trimming control circuit enters the trimming mode, it enters the permanent trimming mode or the pre-trimming mode according to the trimming mode control signal.

[0009] Optionally, in the permanent trimming mode, the trimming control circuit controls the trimming control unit to blow the fuse through the trimming bit control signal in the corresponding valid state and the master control signal in the valid state.

[0010] Optionally, in the pre-trimming mode, the trimming control circuit controls the trimming control unit not to blow the fuse.

[0011] Optionally, the trimming bit generation unit includes:

[0012] A trimming enable unit that receives the power-on signal, the trimming mode control signal, and the input current signal, and controls the generation of a first intermediate signal corresponding to the timing of the trimming mode control signal according to the power-on signal and the input current signal, and latches the first intermediate signal according to the power-on signal to generate the trimming enable signal;

[0013] A trimming counting unit that is connected to the trimming enable unit to receive the trimming enable signal, and receives the counting enable signal and the trimming clock signal, and counts the received trimming clock signal according to the trimming enable signal and the counting enable signal, and outputs the trimming bit control signal correspondingly when each period of the trimming clock signal is counted.

[0014] Optionally, each trimming control unit also generates an analog trimming signal or a real trimming signal according to whether the fuse is blown.

[0015] Optionally, each trimming control unit includes:

[0016] A fuse control module that blows the fuse according to the trimming mode control signal in the valid state, the master control signal in the valid state, and the trimming bit control signal in the corresponding valid state, and does not blow the fuse otherwise;

[0017] A trimming signal generation module that generates the trimming signal according to the master control signal, the power-on signal, the state of the fuse, or the corresponding trimming bit control signal.

[0018] Optionally, when the fuse control module does not blow the fuse, the trimming signal generation module resets the analog trimming signal when powering on next time.

[0019] Optionally, when the fuse control module blows the fuse, the trimming signal generation module continues to output the real trimming signal when powering on next time.

[0020] Optionally, the trimming signal generation module also resets the voltage of the connection node between the fuse control module and the fuse when the power-on signal is powered on, so as to reduce the interference to the voltage of the floating connection node when powering on in the case of fuse blowing.

[0021] Optionally, each of the fuse control modules includes:

[0022] A second AND gate, the first input terminal of the second AND gate receives the corresponding trimming bit control signal, the second input terminal of the second AND gate receives the master control signal, and the third input terminal of the second AND gate receives the trimming mode control signal;

[0023] A third switching transistor, the control terminal of the third switching transistor is connected to the output terminal of the second AND gate, the first terminal of the third switching transistor is grounded, the second terminal of the third switching transistor is connected to the power supply terminal via the fuse, and the third switching transistor conducts to provide a fusing current to the fuse.

[0024] Optionally, each of the trimming signal generating modules includes:

[0025] A second pulse generating unit, which receives the power-on signal and outputs a second pulse signal based on the valid power-on signal;

[0026] A third NOT gate, the input terminal of the third NOT gate is connected to the connection node between the second terminal of the third switching transistor and the fuse;

[0027] A second OR gate, the first input terminal of the second OR gate is connected to the output terminal of the third NOT gate, and the second input terminal of the second OR gate receives the corresponding trimming bit control signal;

[0028] A first delay unit, the first delay unit receives the master control signal and is connected to the second pulse generating unit to receive the second pulse signal, and the first delay unit outputs a delay signal;

[0029] A second flip-flop, the input terminal of the second flip-flop is connected to the output terminal of the second OR gate, the clock terminal of the second flip-flop is connected to the first delay unit to receive the delay signal, the reset terminal of the second flip-flop is connected to the second pulse generating unit to receive the second pulse signal, and the first output terminal of the second flip-flop outputs the real or analog trimming signal of the corresponding bit.

[0030] Optionally, each of the trimming signal generating modules further includes:

[0031] A fourth switching transistor, the control terminal of the fourth switching transistor is connected to the second pulse generating unit and receives the second pulse signal, the first terminal of the fourth switching transistor is grounded, and the second terminal of the fourth switching transistor is connected to the input terminal of the third NOT gate.

[0032] Optionally, it further includes:

[0033] The anti-mis-triggering unit, connected to the trimming counting unit and the trimming enabling unit, receives the trimming enabling signal, the Nth trimming bit control signal, and the trimming clock signal, counts the trimming clock signal after at least one cycle of the trimming clock signal, and ends the counting according to the trimming enabling signal and the Nth trimming bit control signal, so as to output the counting enabling signal in an effective state during the stage when the anti-mis-triggering unit counts the trimming clock signal.

[0034] Optionally, the trimming mode control signal, the power-on signal, the trimming clock signal, and the total control signal are provided by an external port.

[0035] Optionally, the trimming enabling unit includes:

[0036] A first current mirror, which receives the input current signal and outputs a first bias current and a second bias current;

[0037] A second current mirror, connected to the first current mirror to receive the first bias current and output a third bias current;

[0038] A first switching transistor, the control terminal of the first switching transistor is connected to the first current mirror and the second current mirror and receives the first bias current, the first terminal of the first switching transistor receives the trimming mode control signal, and the second terminal of the first switching transistor is connected to the first current mirror and receives the second bias current;

[0039] A second switching transistor, the control terminal of the second switching transistor is connected to the first current mirror and the second terminal of the first switching transistor and receives the second bias current, the first terminal of the second switching transistor is grounded, and the second terminal of the second switching transistor is connected to the second current mirror and receives the third bias current;

[0040] A first NOT gate, the input terminal of the first NOT gate is connected to the second terminal of the second switching transistor, and the output terminal of the first NOT gate outputs the first intermediate signal; and

[0041] A latch, the first input terminal of the latch is connected to the output terminal of the first NOT gate to receive the first intermediate signal, the second input terminal of the latch receives the power-on signal, and the output terminal of the latch outputs the trimming enabling signal.

[0042] Optionally, the trimming counting unit includes:

[0043] A first AND gate, the first input terminal of the first AND gate receives the trimming clock signal, and the second input terminal of the first AND gate receives the counting enabling signal;

[0044] A first NOR gate, a first input end of the first NOR gate receives the counting enable signal, and a second input end of the first NOR gate receives the trimming enable signal;

[0045] M cascaded first flip - flops, an input end of each first flip - flop is connected to its own second output end, a first output end of each first flip - flop outputs a first output signal via a NOT gate, a first output end of each first flip - flop outputs a second output signal via two serially connected NOT gates, a clock end of each first flip - flop is connected to a second output end of the previous - stage first flip - flop, a clock end of the first - stage first flip - flop is connected to an output end of the first AND gate, and a reset end of each first flip - flop is connected to an output end of the first NOR gate; and

[0046] N third AND gates, each third AND gate inputs a first output signal or a second output signal corresponding to each of the M first flip - flops, and an output end of each third AND gate outputs a corresponding trimming bit control signal, , and M and N are positive integers.

[0047] Optionally, the anti - mis - triggering unit includes:

[0048] A second NOT gate, an input end of the second NOT gate receives the trimming enable signal;

[0049] A first pulse generating unit, receives the Nth trimming bit control signal, and outputs a first pulse signal based on the Nth trimming bit control signal at a first level;

[0050] A first OR gate, a first input end of the first OR gate is connected to an output end of the second NOT gate, and a second input end of the first OR gate is connected to the first pulse generating unit to receive the first pulse signal; and

[0051] A counter, a clock end of the counter receives the trimming clock signal, a reset end of the counter is connected to an output end of the first OR gate, an output end of the counter outputs the counting enable signal, and the counter is set to count after at least one cycle of the trimming clock signal.

[0052] Optionally, the first current mirror includes:

[0053] A fifth switching transistor, a control end of the fifth switching transistor is connected to its own second end and receives the input current, and a first end of the fifth switching transistor is grounded;

[0054] A sixth switching transistor, a control end of the sixth switching transistor is connected to the control end of the fifth switching transistor, a first end of the sixth switching transistor is grounded, and a second end of the sixth switching transistor outputs the first bias current; and

[0055] The seventh switching transistor, the control terminal of the seventh switching transistor is connected to the control terminal of the fifth switching transistor, the first terminal of the seventh switching transistor is grounded, and the second terminal of the seventh switching transistor outputs the second bias current;

[0056] The second current mirror includes:

[0057] An eighth switching transistor, the control terminal of the eighth switching transistor is connected to its second terminal and receives the first bias current, and the first terminal of the eighth switching transistor receives the power supply voltage;

[0058] A ninth switching transistor, the control terminal of the ninth switching transistor is connected to the control terminal of the eighth switching transistor, the first terminal of the ninth switching transistor receives the power supply voltage, and the second terminal of the ninth switching transistor outputs the third bias current.

[0059] Optionally, the latch includes:

[0060] A fourth NOT gate, the input terminal of the fourth NOT gate receives the trimming enable signal;

[0061] A first NAND gate, the first input terminal of the first NAND gate is connected to the output terminal of the fourth NOT gate;

[0062] A second NAND gate, the first input terminal of the second NAND gate is connected to the output terminal of the first NAND gate, the second input terminal of the second NAND gate receives the power-on signal, and the output terminal of the second NAND gate is connected to the second input terminal of the first NAND gate; and

[0063] A fifth NOT gate, the input terminal of the fifth NOT gate is connected to the output terminal of the second NAND gate, and the output terminal of the fifth NOT gate outputs the trimming enable signal.

[0064] According to a second aspect of the present disclosure, there is provided a trimming control method, characterized by including:

[0065] Latching the trimming mode control signal according to the power-on signal to generate a trimming enable signal;

[0066] And counting the received trimming clock signal according to the trimming enable signal and the counting enable signal, and correspondingly outputting a trimming bit control signal when each period of the trimming clock signal is counted;

[0067] Controlling whether to blow the corresponding fuse according to the trimming mode control signal, the total control signal and the corresponding trimming bit control signal, where N is a positive integer.

[0068] Optionally, when the power-on signal is powered on, the trimming mode control signal in the latched valid state is used to generate a trimming enable signal in the valid state, and the trimming mode is entered; after entering the trimming mode, the permanent trimming mode or the pre-trimming mode is entered according to the trimming mode control signal.

[0069] Optionally, in the permanent trimming mode, the corresponding fuse is controlled to be blown through the trimming bit control signal in the corresponding valid state and the master control signal in the valid state.

[0070] Optionally, in the pre-trimming mode, it is controlled that the corresponding fuse is not blown.

[0071] Optionally, it further includes: generating an analog trimming signal or a real trimming signal according to whether the corresponding fuse is blown.

[0072] Optionally, when the corresponding fuse is not blown, the analog trimming signal is reset at the next power-on.

[0073] Optionally, when the corresponding fuse is blown, the real trimming signal is continuously output at the next power-on.

[0074] Optionally, it further includes: resetting the voltage of the connection node between the fuse control module and the fuse when the power-on signal is powered on, so as to reduce the interference of the voltage of the floating connection node during power-on in the case of fuse blowing.

[0075] According to a third aspect of the present disclosure, a chip is provided, including: N trimming circuits, each trimming circuit contains a fuse; and the trimming control circuit as described above.

[0076] The chip, its trimming control circuit and trimming control method provided by the present disclosure latch the trimming mode control signal according to the power-on signal to generate a trimming enable signal, count the received trimming clock signal according to the trimming enable signal and the count enable signal, and correspondingly output a trimming bit control signal when counting one cycle of the trimming clock signal. Each trimming control unit controls whether to blow the fuse according to the trimming mode control signal, the master control signal and the corresponding trimming bit control signal. That is, the present disclosure enters the trimming mode based on the trimming enable signal in the valid state, and enters the permanent trimming mode or the pre-trimming mode according to the trimming mode control signal. Furthermore, in the permanent trimming mode, the corresponding fuse is controlled to be blown through the trimming bit control signal in the corresponding valid state and the master control signal in the valid state. In the pre-trimming mode, it is controlled that the fuse is not blown. The above solution has a pre-trimming function, which can avoid incorrect trimming caused by writing incorrect trimming codes, thereby improving the yield and manufacturing cost of the chip.

[0077] Further, each trimming control unit also generates an analog trimming signal or a real trimming signal according to whether the fuse is blown. When the fuse is not blown, the analog trimming signal is reset when power is applied next time. When the fuse is blown, the real trimming signal is continuously output when power is applied next time. In this way, in the case of pre-trimming, it is possible to first judge whether the desired trimming effect can be achieved based on the output analog trimming signal without blowing the fuse, further improving the trimming efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0078] Through the following description of the embodiments of the present invention with reference to the drawings, the above and other objects, features and advantages of the present invention will become more apparent. In the drawings:

[0079] Figure 1 shows a structural diagram of a trimming control circuit provided according to the first embodiment of the present disclosure;

[0080] Figure 2 shows another structural diagram of a trimming control circuit provided according to the first embodiment of the present disclosure;

[0081] Figure 3 shows a structural diagram of a trimming control circuit provided according to the second embodiment of the present disclosure;

[0082] Figure 4 shows a schematic circuit diagram of a trimming enable unit provided according to the embodiment of the present disclosure;

[0083] Figure 5 shows a schematic circuit diagram of a trimming counting unit provided according to the embodiment of the present disclosure;

[0084] Figure 6 shows a schematic circuit diagram of a trimming control unit provided according to the embodiment of the present disclosure;

[0085] Figure 7 shows a schematic circuit diagram of an anti-mis-triggering unit provided according to the embodiment of the present disclosure;

[0086] Figure 8 shows a schematic timing waveform diagram of a trimming control circuit provided according to the embodiment of the present disclosure. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0087] The various embodiments of the present invention will be described in more detail below with reference to the drawings. In each of the drawings, the same elements are denoted by the same or similar reference numerals. For the sake of clarity, the various parts in the drawings are not drawn to scale.

[0088] Currently, the main trimming methods are as follows: laser trimming, diode anti-fuse trimming, memory cell trimming, and fuse trimming. Laser trimming has a very high trimming accuracy, but the trimming cost is high, and it can only be implemented on a bare die. Therefore, the influence of packaging is inevitable. Although diode anti-fuse trimming can be performed after packaging, it has the disadvantage of large occupied area. Memory cell trimming can be erased and rewritten repeatedly, but the design structure and manufacturing process are complex and the manufacturing cost is high.

[0089] The chip trimming method provided by the present disclosure adopts fuse trimming. The present disclosure provides a trimming control circuit with a pre-trimming function.

[0090] Figure 1 The structural diagram of a trimming control circuit according to the first embodiment of the present disclosure is shown. Figure 2 The structural diagram of another trimming control circuit according to the first embodiment of the present disclosure is shown.

[0091] As Figure 1 shown, the trimming control circuit 100 includes a trimming bit generation unit 150 and N trimming control units 130.

[0092] The trimming bit generation unit 150 receives a power-on signal VCC, a trimming mode control signal TM_FUSE, a trimming clock signal TM_CLK, and a counting enable signal START. And latches the trimming mode control signal TM_FUSE according to the power-on signal VCC to generate a trimming enable signal TM_EN, counts the received trimming clock signal TM_CLK according to the trimming enable signal TM_EN and the counting enable signal START, and outputs a trimming bit control signal Date corresponding to each cycle of counting the trimming clock signal TM_CLK <n>。1 ≤ n ≤ N, where n is a positive integer.

[0093] There are N trimming control units 130, and a fuse is connected between each trimming control unit 130 and the power supply terminal Vcc. Each trimming control unit 130 also receives a corresponding trimming bit control signal Date <n>, each trimming control unit 130 controls according to the trimming mode control signal TM_FUSE, the overall control signal control, and the corresponding trimming bit control signal Date <n>Control whether the fuse is blown.

[0094] Further, when the power supply signal VCC is powered on, the trimming control circuit 100 latches the trimming mode control signal TM_FUSE in the valid state (for example, high level) to generate a trimming enable signal TM_EN in the valid state, and enters the trimming mode. After the trimming control circuit 100 enters the trimming mode, it enters the permanent trimming mode or the pre-trimming mode according to the trimming mode control signal TM_FUSE.

[0095] Further, in the permanent trimming mode, the trimming control circuit 100 controls the signal Date of the trimming bit in the corresponding valid state <n>The total control signal control in the valid state controls the trimming control unit 130 to blow the fuse. In the pre-trimming mode, the trimming control circuit 100 controls the trimming control unit 130 not to blow the fuse.

[0096] As Figure 2 shown, the trimming bit generation unit 150 includes a trimming enable unit 110 and a trimming counting unit 120.

[0097] The trimming enable unit 110 receives the power-on signal VCC, the input current signal IBIAS, and the trimming mode control signal TM_FUSE, and controls the generation of a first intermediate signal corresponding to the timing of the trimming mode control signal TM_FUSE according to the power-on signal VCC and the input current signal IBIAS, and latches the first intermediate signal according to the power-on signal VCC to generate a trimming enable signal TM_EN.

[0098] The trimming counting unit 120 is connected to the trimming enable unit 110 to receive the trimming enable signal TM_EN, and also receives a counting enable signal START and a trimming clock signal TM_CLK. And it counts the received trimming clock signal TM_CLK according to the trimming enable signal TM_EN and the counting enable signal START, and outputs a trimming bit control signal Date correspondingly every time a cycle of the trimming clock signal TM_CLK is counted. <n>。Further, the trimming counting unit 120 outputs N trimming bit control signals (Date<1>, Date<2>, …, Date <n>, …, Date< >.

[0099] Each trimming control unit 130 also generates an analog trimming signal OUT according to whether the fuse is blown <n>or the true trimming signal OUT <n>。

[0100] Furthermore, each trimming control unit 130 controls the non-fusing fuse and the corresponding trimming bit control signal Date of the effective state (e.g., high level) according to the trimming mode control signal TM_FUSE of the invalid state (e.g., low level) and the master control signal Control of the effective state level (e.g., high level). <n>, and output the analog trimming signal OUT corresponding to the bit <n>。And according to the trimming mode control signal TM_FUSE of the valid state (such as high level), the overall control signal Control of the valid state (such as high level), and the trimming bit control signal Date of the corresponding valid state (such as high level) <n>Blow the fuse and output the true trimming signal OUT for the corresponding bit <n>。

[0101] Further, when the fuse is not blown, the reset analog trimming signal OUT is reset when power is applied next time <n>When fusing the fuse, continue to output the true trimming signal OUT during the next power-on <n>。

[0102] Further, the trimming mode control signal TM_FUSE, the power-on signal VCC, the trimming clock signal TM_CLK, and the overall control signal Control are provided by an external port. Exemplarily, when the power-on signal VCC jumps to an effective state (e.g., high level), the external port provides a trimming mode control signal TM_FUSE in an effective state (e.g., high level), a trimming clock signal TM_CLK in an invalid state (e.g., low level), and / or an overall control signal Control in an invalid state (e.g., low level).

[0103] Figure 3 The structure diagram of a trimming control circuit provided according to the second embodiment of the present disclosure is shown.

[0104] As Figure 3 shown, the trimming control circuit 200 further includes an anti-mis-triggering unit 140 connected to the trimming counting unit 120 on the basis of the trimming control circuit 100. The anti-mis-triggering unit 140 receives the trimming enable signal TM_EN, the Nth trimming bit control signal Date< >, and the trimming clock signal TM_CLK, counts the trimming clock signal TM_CLK after at least one cycle of the trimming clock signal TM_CLK, and ends the counting according to the trimming enable signal TM_EN and the Nth trimming bit control signal Date< >. An effective state (e.g., high level) counting enable signal START is output during the stage when the anti-mis-triggering unit 140 counts the trimming clock signal TM_CLK and is provided to the trimming counting unit 120.

[0105] Figure 4 The circuit schematic diagram of a trimming enable unit provided according to the embodiment of the present disclosure is shown.

[0106] As Figure 4 shown, the trimming enable unit 110 in the trimming control circuit includes a first current mirror 111, a second current mirror 112, a latch 113, a first switching transistor M1, a second switching transistor M2, and a first NOT gate NOT1.

[0107] The first current mirror 111 receives an input current signal IBIAS and outputs a first bias current I1 and a second bias current I2. The second current mirror 112 is connected to the first current mirror to receive the first bias current I1 and outputs a third bias current I3. The control terminal of the first switching transistor M1 is connected to the first current mirror 111 and the second current mirror 112 and receives the voltage at the connection node of the eighth switching transistor M8 and the sixth switching transistor M6. The first terminal of the first switching transistor M1 receives a trimming mode control signal TM_FUSE, and the second terminal of the first switching transistor M1 is connected to the first current mirror 111 and receives the second bias current I2. The control terminal of the second switching transistor M2 is connected to the first current mirror 111 and the second terminal of the first switching transistor M1 and receives the voltage at the connection node of the first switch M1 and the seventh switch M7. The first terminal of the second switching transistor M2 is grounded, and the second terminal of the second switching transistor M2 is connected to the second current mirror 112 and receives the third bias current I3. The input terminal of the first NOT gate NOT1 is connected to the second terminal of the second switching transistor M2, and the output terminal of the first NOT gate NOT1 outputs a first intermediate signal. The first input terminal of the latch 113 is connected to the output terminal of the first NOT gate NOT1 to receive the first intermediate signal. The second input terminal of the latch 113 receives a power-on signal VCC, and the output terminal of the latch 113 outputs a trimming enable signal TM_EN.

[0108] Exemplarily, the first current mirror 111 includes a fifth switching transistor M5, a sixth switching transistor M6, and a seventh switching transistor M7. The control terminal of the fifth switching transistor M5 is connected to its second terminal and receives the input current signal IBIAS, and the first terminal of the fifth switching transistor M5 is grounded. The control terminal of the sixth switching transistor M6 is connected to the control terminal of the fifth switching transistor M5, the first terminal of the sixth switching transistor M6 is grounded, and the second terminal of the sixth switching transistor M6 outputs the first bias current I1. The control terminal of the seventh switching transistor M7 is connected to the control terminal of the fifth switching transistor M5, the first terminal of the seventh switching transistor M7 is grounded, and the second terminal of the seventh switching transistor M7 outputs the second bias current I2. Further, the width-to-length ratios of the fifth switching transistor M5, the sixth switching transistor M6, and the seventh switching transistor M7 are equal, for example.

[0109] Exemplarily, the second current mirror 112 includes an eighth switching transistor M8 and a ninth switching transistor M9. The control terminal of the eighth switching transistor M8 is connected to its second terminal, and the first terminal of the eighth switching transistor M8 receives a power supply voltage VCC. The control terminal of the ninth switching transistor M9 is connected to the control terminal of the eighth switching transistor M8, the first terminal of the ninth switching transistor M9 receives a power supply voltage VCC, and the second terminal of the ninth switching transistor M9 outputs the third bias current I3. Further, the width-to-length ratios of the eighth switching transistor M8 and the ninth switching transistor M9 are equal, for example.

[0110] Further, the width-to-length ratio of the first switching transistor M1 is greater than that of the eighth switching transistor M8, and the current flowing through the first switching transistor M1 is greater than the current flowing through the seventh switching transistor M7. The second bias current I2 is greater than the first bias current I1 and also greater than the third bias current I3.

[0111] Exemplarily, the latch 113 includes a fourth NOT gate NOT4, a first NAND gate NAND1, a second NAND gate NAND2, and a fifth NOT gate NOT5. The input terminal of the fourth NOT gate NOT4 receives the trimming enable signal FUSE_EN. The first input terminal of the first NAND gate NAND1 is connected to the output terminal of the fourth NOT gate NOT4. The first input terminal of the second NAND gate NAND2 is connected to the output terminal of the first NAND gate NAND1. The second input terminal of the second NAND gate NAND2 receives the power-on signal VCC, and the output terminal of the second NAND gate NAND2 is connected to the second input terminal of the first NAND gate NAND1. The input terminal of the fifth NOT gate NOT5 is connected to the output terminal of the second NAND gate NAND2, and the output terminal of the fifth NOT gate NOT5 outputs the trimming enable signal TM_EN.

[0112] Exemplarily, after the internal power supply of the chip is established, the power-on signal VCC outputs a high level. When the trimming mode control signal TM_FUSE provided by the external port of the trimming control circuit is at a high level, since the current flowing through the first switching transistor M1 is greater than the current flowing through the seventh switching transistor M7, the control terminal of the second switching transistor M2 is pulled high and then turned on, and the second terminal of the second switching transistor M2 is pulled to a low level. The state of the latch 113 is locked, and the output trimming enable signal TM_EN is at a high level. When the trimming mode control signal TM_FUSE is at a low level, the source-drain voltage difference Vgs of the first switching transistor M1 is less than the threshold voltage Vth, the first switching transistor M1 is turned off, and the current flowing through the seventh switching transistor M7 mirrors the input current signal IBIAS flowing through the fifth switching transistor M5. The control terminal of the second switching transistor M2 is pulled low and then turned off, and the second terminal of the second switching transistor M2 is at a high level. Correspondingly, the state of the latch 113 is locked, and the output trimming enable signal TM_EN remains at a high level. It is not until the trimming control circuit is powered off, that is, when the power-on signal VCC becomes a low level, that the output trimming enable signal TM_EN is reset to a low level.

[0113] Figure 5 The circuit schematic diagram of the trimming counting unit provided by the embodiment of the present disclosure is shown.

[0114] As Figure 5 shown, the trimming counting unit 120 in the trimming control circuit includes a first AND gate AND1, a first NOR gate NOR1, M cascaded first flip-flops (U11, U12,..., U1M), and N third AND gates (AND31, AND32,..., AND3N).

[0115] The first input terminal of the first AND gate AND1 receives the trimming clock signal TM_CLK, and the second input terminal of the first AND gate AND1 receives the counting enable signal START. The first input terminal of the first NOR gate NOR1 receives the counting enable signal START, and the second input terminal of the first NOR gate NOR1 receives the trimming enable signal TM_EN.

[0116] For each of the M cascaded first flip - flops, the input terminal D is connected to its own second output terminal Each first flip - flop outputs a first output signal (B1 or B2 or,..., or BM) at its first output terminal Q through a NOT gate, and outputs a second output signal (A1 or A2 or,..., or AM) at its first output terminal Q through two serially connected NOT gates. The clock terminal Clk of each first flip - flop is connected to the second output terminal of the previous - stage first flip - flop The clock terminal Clk of the first - stage first flip - flop U11 is connected to the output terminal of the first AND gate AND1, and the reset terminal Rest of each first flip - flop is connected to the output terminal of the first NOR gate NOR. M is a positive integer. Exemplarily, the input terminal D of the first - stage first flip - flop U11 is connected to its own second output terminal The first output terminal Q of the first - stage first flip - flop U11 outputs the first output signal B1 through a NOT gate and outputs the second output signal A1 through two NOT gates. The clock terminal Clk of the first - stage first flip - flop U11 is connected to the output terminal of the first AND gate AND1, and the reset terminal Rest of the first - stage first flip - flop U11 is connected to the output terminal of the first NOR gate NOR. The input terminal D of the second - stage first flip - flop U12 is connected to its own second output terminal The first output terminal Q of the second - stage first flip - flop U12 outputs the first output signal B2 through a NOT gate and outputs the second output signal A2 through two NOT gates. The clock terminal Clk of the second - stage first flip - flop U12 is connected to the second output terminal of the first - stage first flip - flop U11 The reset terminal Rest of the second - stage first flip - flop U12 is connected to the output terminal of the first NOR gate NOR. The input terminal D of the last - stage first flip - flop (the M - th stage first flip - flop) U1M is connected to its own second output terminal The first output terminal Q of the M - th stage first flip - flop U1M outputs the first output signal BM through a NOT gate and outputs the second output signal AM through two NOT gates. The clock terminal Clk of the M - th stage first flip - flop U1M is connected to the second output terminal of the previous - stage first flip - flop U1(M - 1) The reset terminal Rest of the M - th stage first flip - flop U1M is connected to the output terminal of the first NOR gate NOR.

[0117] N third AND gates, each of the third AND gates receives, as its inputs, the first output signal or the second output signal corresponding to each of the M first flip-flops, and the output terminal of each third AND gate outputs a corresponding trimming bit control signal. , and M and N are positive integers. Exemplarily, the input terminal of the first third AND gate AND31 receives the second output signal A1 output by the first first flip-flop U11 and the first output signals (B2, B3,..., BM) output by the other first flip-flops among the M first flip-flops, and the output terminal of the first third AND gate AND31 outputs the first trimming bit control signal Date<1>. The input terminal of the second third AND gate AND32 receives the second output signal A2 output by the second first flip-flop U12 and the first output signals (B1, B3,..., BM) output by the other first flip-flops among the M first flip-flops, and the output terminal of the second third AND gate AND32 outputs the second trimming bit control signal Date<2>. The input terminal of the Nth third AND gate AND3N receives the second output signals (A1, A2,..., AM) output by the M first flip-flops (U11 to U1M), and the output terminal of the Nth third AND gate AND3N outputs the Nth trimming bit control signal Date <n>Further, among the M signals input to each third AND gate, at least one second output signal is included, and the remaining inputs are first output signals.

[0118] Exemplarily, taking N = 7 (correspondingly, M = 3) trimming bit control signals as an example. The input terminal of the first third AND gate AND31 receives the second output signal A1 output by the first first flip-flop U11 and the first output signals B2 and B3 output by other first flip-flops among the M first flip-flops. The output terminal of the first third AND gate AND31 outputs the first trimming bit control signal Date< >. The input terminal of the second third AND gate AND32 receives the second output signal A2 output by the second first flip-flop U12 and the first output signals B1 and B3 output by other first flip-flops among the M first flip-flops. The output terminal of the second third AND gate AND32 outputs the second trimming bit control signal Date< >. The input terminal of the third third AND gate AND33 receives the first output signal B3 output by the third first flip-flop U13 and the second output signals A2 and A1 output by other first flip-flops among the M first flip-flops. The output terminal of the third third AND gate AND33 outputs the third trimming bit control signal Date< >. The input terminal of the fourth third AND gate AND34 receives the second output signal A3 output by the third first flip-flop U13 and the first output signals B2 and B1 output by other first flip-flops among the M first flip-flops. The output terminal of the fourth third AND gate AND34 outputs the fourth trimming bit control signal Date< >. The input terminal of the fifth third AND gate AND35 receives the first output signal B2 output by the second first flip-flop U12 and the second output signals A3 and A1 output by other first flip-flops among the M first flip-flops. The output terminal of the fifth third AND gate AND35 outputs the fifth trimming bit control signal Date< >. The input terminal of the sixth third AND gate AND36 receives the first output signal B1 output by the first first flip-flop U11 and the second output signals A3 and A2 output by other first flip-flops among the M first flip-flops. The output terminal of the sixth third AND gate AND36 outputs the sixth trimming bit control signal Date< >. The input terminal of the seventh third AND gate AND37 receives the second output signals A3, A2, and A1 output by the first to M-th first flip-flops U11 to U13. The output terminal of the seventh third AND gate AND37 outputs the seventh trimming bit control signal Date< >.

[0119] When the counting enable signal START is at a high level, the counting of the period of the trimming clock signal TM_CLK provided by the external port of the trimming control circuit starts, and the M first flip-flops are reset until the counting enable signal START becomes low or the trimming enable signal TM_EN becomes low, thereby resetting the trimming counting unit 120 to prepare for the next trimming count. Further, when starting to count, for example, when the first rising edge of the trimming clock signal TM_CLK arrives, the second output signal A1 of the first-stage first flip-flop U11 is 1, and the second output signals of other first flip-flops are 0. Correspondingly, only the first trimming bit control signal Date<1> is 1. When the second rising edge of the trimming clock signal TM_CLK arrives, the second output signal A2 of the second-stage first flip-flop U12 is 1, and the second output signals of other first flip-flops are 0. Correspondingly, only the second trimming bit control signal Date<2> is 1. When the third rising edge of the trimming clock signal TM_CLK arrives, the second output signal A1 of the first-stage first flip-flop U11 is inverted to 1, and the second output signal A2 of the second-stage first flip-flop U12 remains 1, and the first output signal B3 of the third-stage first flip-flop U13 remains 1. Correspondingly, only the third trimming bit control signal Date<3> is 1. When the fourth rising edge of the trimming clock signal TM_CLK arrives, the first output signal B1 of the first-stage first flip-flop U11 is inverted to 1, the first output signal B2 of the second-stage first flip-flop U12 is inverted to 1, and the second output signal A3 of the third-stage first flip-flop U13 is inverted to 1. Correspondingly, only the fourth trimming bit control signal Date<4> is 1. When the fifth rising edge of the trimming clock signal TM_CLK arrives, the second output signal A1 of the first-stage first flip-flop U11 is inverted to 1, the first output signal B2 of the second-stage first flip-flop U12 remains 1, and the second output signal A3 of the third-stage first flip-flop U13 remains 1. Correspondingly, only the fifth trimming bit control signal Date<5> is 1. When the sixth rising edge of the trimming clock signal TM_CLK arrives, the first output signal B1 of the first-stage first flip-flop U11 is inverted to 1, the second output signal A2 of the second-stage first flip-flop U12 is inverted to 1, and the second output signal A3 of the third-stage first flip-flop U13 remains 1. Correspondingly, only the sixth trimming bit control signal Date<6> is 1. And so on, when the seventh rising edge of the trimming clock signal TM_CLK arrives, correspondingly, only the seventh trimming bit control signal Date<7> is 1.

[0120] Figure 6 The circuit schematic diagram of the trimming control unit provided by the embodiment of the present disclosure is shown.

[0121] As Figure 6 As shown, the circuit structures of each trimming control unit 130 in the trimming control circuit are, for example, the same. The trimming control unit 130 includes a fuse control module 133 and a trimming signal generation module 134. The fuse control module 133 controls the trimming mode control signal TM_FUSE in the valid state, the total control signal control in the valid state, and the trimming bit control signal Date in the corresponding valid state <n>Fuse the fuse efuse_n, otherwise do not fuse the fuse efuse_n. The trimming signal generation module 134 generates a trimming signal according to the master control signal control, the power-on signal VCC, the state of the fuse efuse_n or the corresponding trimming bit control signal.

[0122] Each fuse control module 133 includes a second AND gate AND2 and a third switching transistor M3.

[0123] Each trimming signal generation module 134 includes a second pulse generation unit 131, a third NOT gate NOT3, a second OR gate OR2, a first delay unit 132, and a second flip-flop U2. Further, each trimming signal generation module 134 further includes a fourth switching transistor M4, which resets the voltage of the connection node between the fuse control module 133 and the fuse when the power-on signal VCC is powered on, so as to reduce the interference to the voltage of the floating connection node during power-on in the case of fuse blowing.

[0124] The first input terminal of the second AND gate AND2 receives the corresponding trimming bit control signal Date <n>, the second input terminal of the second AND gate AND2 receives the master control signal Control, and the third input terminal of the second AND gate AND2 receives the trimming mode control signal TM_FUSE. Where n is a positive integer and n ≤ N. The control terminal of the third switching transistor M3 is connected to the output terminal of the second AND gate AND2. The first terminal of the third switching transistor M3 is grounded, and the second terminal of the third switching transistor M3 is connected to the power supply terminal Vcc via the fuse efuse_n. The third switching transistor M3 is turned on to provide a fusing current to the fuse. The second pulse generating unit 131 receives the power-on signal VCC and outputs a second pulse signal based on the first level of the power-on signal VCC. The control terminal of the fourth switching transistor M4 is connected to the second pulse generating unit 131 and receives the second pulse signal. The first terminal of the fourth switching transistor M4 is grounded, and the second terminal of the fourth switching transistor M4 is connected to the connection node between the second terminal of the third switching transistor M3 and the fuse efuse_n. The input terminal of the third NOT gate NOT3 is connected to the second terminal of the fourth switching transistor M4. The first input terminal of the second OR gate OR2 is connected to the output terminal of the third NOT gate NOT3, and the second input terminal of the second OR gate OR2 receives the corresponding trimming bit control signal Date <n>. The first delay unit 132 receives the master control signal Control and is connected to the second pulse generation unit 131 to receive the second pulse signal, and the first delay unit 132 outputs a delay signal. The input terminal D of the second flip-flop U2 is connected to the output terminal of the second OR gate OR2. The clock terminal Clk of the second flip-flop U2 is connected to the first delay unit 132 to receive the delay signal. The reset terminal Rest of the second flip-flop U2 is connected to the second pulse generation unit 131 to receive the second pulse signal. The first output terminal Q of the second flip-flop U2 outputs the true trimming signal OUT of the corresponding bit <n>Or the simulated trimming signal OUT <n>。

[0125] Exemplarily, the second pulse generation unit 131 is a circuit that generates a pulse signal based on the high level of an input signal (power-on signal VCC), and can be implemented by, for example, a monostable flip-flop. The first delay unit 132 is a delay circuit that outputs a delayed signal after delaying an input signal (total control signal Control) for a first time, and is implemented by, for example, an OR gate OR3 and a delay module. However, the implementation of the pulse generation unit and the first delay unit in this application is not limited thereto.

[0126] It should be noted that the signal output from the first output terminal Q of the second flip-flop U2 is the true trimming signal OUT <n>It is still the analog trimming signal OUT <n>, depending on whether the fuse efuse_n connected between the power supply terminal Vcc and the trimming control unit 130 is blown. When the power-on signal VCC is valid (for example, high level) during power supply establishment, when the trimming mode control signal TM_FUSE is at the first level and the overall control signal Control is at the first level, the third switching transistor M3 is controlled to conduct, providing a fusing current to the connected fuse efuse_n. When the fuse is blown, the output terminal of the second flip-flop U2 outputs a true trimming signal OUT <n>, this adjustment is a permanent adjustment. When the power-on signal VCC is valid (for example, high level) during power supply establishment, when the adjustment mode control signal TM_FUSE is at the second level and the total control signal Control is at the first level, the third switching transistor M3 is controlled to turn off, and no fusing current is provided to the connected fuse efuse_n. The fuse efuse_n is not blown. According to the valid power-on signal VCC, the fourth switching transistor M4 is controlled to turn on, so that the first input terminal of the second flip-flop U2 inputs the first level, and according to the total control signal Control at the first level, a trigger edge is generated at the second input terminal of the second flip-flop U2, triggering the output terminal of the second flip-flop U2 to output an analog adjustment signal OUT <n>, this adjustment is a simulated pre-adjustment.

[0127] Further, when the adjustment control circuit is just powered on, the adjustment control unit 130 inputs an adjustment mode control signal TM_FUSE of the first level, and the external port needs to provide an adjustment clock signal TM_CLK of the second level and / or an invalid overall control signal Control, so that although the permanent adjustment mode is entered this time, the fuse cannot be blown. It can be seen that when the adjustment control circuit is just powered on, it is necessary to provide an adjustment mode control signal TM_FUSE of the first level and an input current signal IBIAS to latch the adjustment mode control signal TM_FUSE and generate an adjustment enable signal TM_EN of the first level.

[0128] Exemplarily, when the adjustment mode control signal TM_FUSE is at a low level, the adjustment control unit 130 is in the pre-adjustment mode, and the fuse efuse_n will not be blown. When the adjustment mode control signal TM_FUSE is at a high level, the adjustment control unit 130 is in the permanent adjustment mode, and when the overall control signal Control and the corresponding adjustment bit control signal Date <n>When they all jump to the high level, the control terminal of the third switching transistor M3 becomes high level and conducts, and provides a fusing current to the fuse efuse_n to fuse the fuse efuse_n. When the power is re-powered on, the power-on signal VCC becomes high level, the second terminal of the fourth switching transistor M4 is pulled high, and the trimming status signal OUT output from the output terminal Q of the second flip-flop U2 of the trimming control unit 130 <n>is at a high level, and the trimming is completed. Among them, the required fusing current , is the impedance of the fuse efuse-n, is the impedance of the third switching transistor M3. Further, by designing the aspect ratio of the third switching transistor M3, its on-resistance Ron is made smaller. When the flowing current reaches the fusing current , the fuse efuse-n will be blown.

[0129] Figure 7 shows a circuit schematic diagram of an anti-mis-triggering unit according to an embodiment of the present disclosure.

[0130] As Figure 7 shown, the anti-mis-triggering unit 140 in the trimming control circuit includes a second NOT gate NOT2, a first pulse generation unit 141, a first OR gate OR1, and a counter U3.

[0131] The input end of the second NOT gate NOT2 receives the trimming enable signal TM_EN. The first pulse generation unit 141 receives the Nth trimming bit control signal Date <n>, and based on the Nth trimming position control signal Date <n>The first level outputs a first pulse signal. The first input terminal of the first OR gate OR1 is connected to the output terminal of the second NOT gate NOT2, and the second input terminal of the first OR gate OR1 is connected to the first pulse generation unit 141 to receive the first pulse signal. The clock terminal Clk of the counter U3 receives the trimming clock signal TM_CLK, the reset terminal Reset of the counter U3 is connected to the output terminal of the first OR gate OR1, and the output terminal Counter of the counter U3 outputs a count enable signal START. The counter U3 is set to count after at least one cycle of the trimming clock signal TM_CLK.

[0132] Exemplarily, the first pulse generation unit 141 is based on an input signal (the Nth trimming bit control signal Date <n>A circuit that generates a pulse signal at a high level, for example, can be implemented by a monostable flip-flop.

[0133] Exemplarily, when the trimming enable signal TM_EN becomes high, the counter U3 starts counting. Exemplarily, after one cycle of the trimming clock signal TM_CLK, the counting enable signal START output from the output terminal of the counter U3 turns high. The main function of the anti-mis-triggering unit 140 is to prevent the trimming clock signal TM_CLK from being mis-triggered by interference to trigger the trimming counting unit 120.

[0134] It should be noted that the control end of the switching transistor is the gate, the first end of the switching transistor is the source, and the second end of the switching transistor is the drain. However, the embodiments of the present application are not limited thereto.

[0135] Figure 8 The timing waveform schematic diagram of the trimming control circuit provided according to an embodiment of the present disclosure is shown.

[0136] As Figure 8 shown, the waveform shows the timing of trimming the 3rd bit (permanent trimming), the 1st bit (pre-trimming), and the 2nd bit (pre-trimming) of a 4-bit trimming circuit. Taking the trimming control circuit 200 as an example for illustration.

[0137] Power is established, the provided power-on signal VCC jumps to high level, the provided trimming mode control signal TM_FUSE jumps to high level, and at this time, the trimming enable signal TM_EN output by the trimming enable unit 110 jumps to high level. The externally provided trimming clock signal TM_CLK is, for example, a square wave signal with a period of 200 us and lasts for 6 cycles. The first cycle is when the anti-mis-triggering protection does not participate in counting. When the trimming counting unit 120 starts counting, when the 3rd square wave of the trimming clock signal TM_CLK arrives, the first trimming bit control signal Date<1> output by the trimming counting unit 120 turns high, and when the 4th square wave of the trimming clock signal TM_CLK arrives, the second trimming bit control signal Date<2> output by the trimming counting unit 120 turns high. When the 5th square wave of the trimming clock signal TM_CLK arrives, the third trimming bit control signal Date<3> output by the trimming counting unit 120 turns high. Since the 3rd bit needs to be permanently trimmed, the externally provided trimming mode control signal TM_FUSE must turn high before the 5th square wave of the trimming clock signal TM_CLK arrives after turning low. The externally provided overall control signal Control rises at the moments of the 3rd square wave, the 4th square wave, and the 5th square wave of the trimming clock signal TM_CLK respectively, and the corresponding analog trimming signals OUT<1>, OUT<2>, and OUT<3> output by the trimming control unit 130 turn high to complete the trimming.

[0138] Among them, although the trimming signals OUT<1> corresponding to the first trimming bit and OUT<2> corresponding to the second trimming bit are turned high, the corresponding trimming fuses efuse are not blown. After testing the relevant parameters, the chip can be powered off and then powered on again. The power-on signal VCC provided correspondingly is turned high again, and correspondingly, the output trimming signals OUT<1> and OUT<2> jump to the low level. Since the fuse efuse_3 corresponding to the third trimming bit is permanently blown, even after the chip is powered off and then powered on again, the trimming signal OUT<3> corresponding to the third trimming bit remains high.

[0139] As can be seen from the above, before permanent trimming, the trimming control unit 130 corresponding to the trimming bit for pre-trimming will not actually blow the corresponding fuse, but will simulate and output an analog trimming signal OUT indicating the completion of trimming (such as being high level) through the second D flip-flop, so as to determine whether the desired trimming effect (such as the adjustment of the internal reference voltage, etc.) can be achieved. Through this pre-trimming, incorrect trimming caused by writing incorrect trimming codes can be avoided, thereby improving the yield rate and manufacturing cost of the chip.

[0140] It should be noted that in this application, the effective state of the signal is, for example, the high level state, and the invalid state of the signal is, for example, the low level state, but the implementation of this application is not limited thereto.

[0141] The present disclosure also provides a chip, which at least includes the trimming control circuit as described above and N trimming circuits including fuses.

[0142] The present disclosure also provides a trimming control method, including: latching a trimming mode control signal according to a power-on signal to generate a trimming enable signal; counting a received trimming clock signal according to the trimming enable signal and a counting enable signal, and correspondingly outputting a trimming bit control signal when each period of the trimming clock signal is counted; controlling whether to blow the corresponding fuse according to the trimming mode control signal, a total control signal, and the corresponding trimming bit control signal, where N is a positive integer.

[0143] Further, when the power-on signal is powered on, the trimming mode control signal in the effective state is latched to generate a trimming enable signal in the effective state, and the trimming mode is entered. After entering the trimming mode, enter the permanent trimming mode or the pre-trimming mode according to the trimming mode control signal.

[0144] Further, in the permanent trimming mode, the corresponding fuse is blown by the corresponding trimming bit control signal in the effective state and the total control signal in the effective state.

[0145] Further, in the pre-trimming mode, it is controlled that the corresponding fuse is not blown.

[0146] Further, it further includes: generating an analog trimming signal or a real trimming signal according to whether the corresponding fuse is blown.

[0147] Further, when the corresponding fuse is not blown, reset the analog trimming signal at the next power-on.

[0148] Further, when the corresponding fuse is blown, continue to output the real trimming signal at the next power-on.

[0149] Further, it further includes: resetting the voltage of the connection node between the fuse control module and the fuse when the power-on signal is powered on, so as to reduce the interference to the voltage of the floating connection node during power-on in the case of fuse blowing.

[0150] As described above in the embodiments of the present invention, these embodiments do not describe all the details in detail, nor limit the invention to the specific embodiments described. Obviously, according to the above description, many modifications and variations can be made. These embodiments are selected and specifically described in this specification to better explain the principles and actual applications of the present invention, so that those skilled in the art can make good use of the present invention and its modifications based on the present invention. The present invention is only limited by the claims and their full scope and equivalents.< / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. A trimming control circuit, characterized in that: include: a trim bit generating unit, receiving a power-on signal, a trim mode control signal, a trim clock signal and a count enable signal, latching the trim mode control signal according to the power-on signal to generate a trim enable signal, counting the received trim clock signal according to the trim enable signal and the count enable signal, and outputting a trim bit control signal correspondingly when counting one cycle of the trim clock signal; There are N trimming control units, each of which is connected to the power supply end with a fuse, each of which receives the corresponding trimming position control signal, and each of which also controls whether to blow the fuse according to the trimming mode control signal, the master control signal and the corresponding trimming position control signal, and N is a positive integer.

2. The trimming control circuit according to claim 1, characterized in that: When the power-on signal is powered on, the trimming control circuit latches the trimming mode control signal in the effective state to generate a trimming enable signal in the effective state and enters the trimming mode; after the trimming control circuit enters the trimming mode, it enters the permanent trimming mode or the pre-trimming mode according to the trimming mode control signal.

3. The trimming control circuit according to claim 2, characterized in that: In the permanent trimming mode, the trimming control circuit controls the trimming control unit to blow a fuse through the corresponding trimming bit control signal in a valid state and the master control signal in a valid state.

4. The trimming control circuit according to claim 2, characterized in that: In the pre-trim mode, the trim control circuit controls the trim control unit not to blow a fuse.

5. The trimming control circuit according to claim 1, characterized in that: The trimming bit generating unit comprises: a trimming enable unit, receiving the power-on signal, the trimming mode control signal and the input current signal, and controlling to generate a first intermediate signal corresponding to the timing of the trimming mode control signal according to the power-on signal and the input current signal, and latching the first intermediate signal according to the power-on signal to generate the trimming enable signal; A trimming counting unit is connected to the trimming enable unit to receive the trimming enable signal, and receives the count enable signal and the trimming clock signal, and counts the received trimming clock signal according to the trimming enable signal and the count enable signal, and outputs the trimming position control signal correspondingly when counting one cycle of the trimming clock signal.

6. The trimming control circuit according to claim 1, characterized in that: Each of the trimming control units also generates a simulated trimming signal or a real trimming signal according to whether the fuse is blown.

7. The trimming control circuit according to claim 6, characterized in that: Each of the trimming control units comprises: a fuse control module, which blows the fuse according to the trimming mode control signal in a valid state, the master control signal in a valid state and the corresponding trimming position control signal in a valid state, and does not blow the fuse otherwise; The trim signal generating module generates the trim signal according to the master control signal, the power-on signal, the state of the fuse or the corresponding trim bit control signal.

8. The trimming control circuit according to claim 7, characterized in that: When the fuse control module does not blow the fuse, the trim signal generation module resets the simulated trim signal when powered on next time.

9. The trimming control circuit according to claim 7, characterized in that: When the fuse control module blows the fuse, the trimming signal generating module continues to output the real trimming signal when powered on next time.

10. The trimming control circuit according to claim 7, characterized in that: The trim signal generating module also resets the voltage of the connection node between the fuse control module and the fuse when the power-on signal is powered on, so as to reduce the interference to the voltage of the suspended connection node when powering on when the fuse is blown.

11. The trimming control circuit according to claim 7, characterized in that: Each of the fuse control modules comprises: a second AND gate, wherein a first input terminal of the second AND gate receives the corresponding trimming bit control signal, a second input terminal of the second AND gate receives the master control signal, and a third input terminal of the second AND gate receives the trimming mode control signal; A third switch tube, wherein the control end of the third switch tube is connected to the output end of the second AND gate, the first end of the third switch tube is grounded, the second end of the third switch tube is connected to the power supply end via the fuse, and the third switch tube is turned on to provide a fusing current to the fuse.

12. The trimming control circuit according to claim 7, characterized in that: Each of the trimming signal generating modules comprises: a second pulse generating unit, receiving the power-on signal and outputting a second pulse signal based on the power-on signal in a valid state; a third NOT gate, wherein an input end of the third NOT gate is connected to the second end of the third switch tube and a connection node of the fuse; a second OR gate, wherein a first input terminal of the second OR gate is connected to an output terminal of the third NOT gate, and a second input terminal of the second OR gate receives the corresponding trimming bit control signal; A first delay unit, the first delay unit receives the master control signal and is connected to the second pulse generating unit to receive the second pulse signal, and the first delay unit outputs a delay signal; A second trigger, the input end of the second trigger is connected to the output end of the second OR gate, the clock end of the second trigger is connected to the first delay unit to receive the delay signal, the reset end of the second trigger is connected to the second pulse generating unit to receive the second pulse signal, and the first output end of the second trigger outputs the real or simulated adjustment signal of the corresponding bit.

13. The trimming control circuit according to claim 12, characterized in that: Each of the trimming signal generating modules further comprises: A fourth switch tube, wherein the control end of the fourth switch tube is connected to the second pulse generating unit and receives the second pulse signal, the first end of the fourth switch tube is grounded, and the second end of the fourth switch tube is connected to the input end of the third NOT gate.

14. The trimming control circuit according to claim 1, characterized in that: Also includes: An anti-false trigger unit is connected to the trimming counting unit and the trimming enable unit, receives the trimming enable signal, the Nth trimming bit control signal, and the trimming clock signal, counts the trimming clock signal after at least one cycle of the trimming clock signal, and ends counting according to the trimming enable signal and the Nth trimming bit control signal, so as to output the counting enable signal in a valid state when the anti-false trigger unit counts the trimming clock signal.

15. The trimming control circuit according to claim 1, characterized in that: The trimming mode control signal, the power-on signal, the trimming clock signal and the master control signal are provided by an external port.

16. The trimming control circuit according to claim 5, characterized in that: The adjustment enabling unit comprises: A first current mirror receives the input current signal and outputs a first bias current and a second bias current; a second current mirror, connected to the first current mirror to receive the first bias current and output a third bias current; a first switch tube, wherein a control end of the first switch tube is connected to the first current mirror and the second current mirror and receives the first bias current, a first end of the first switch tube receives the trimming mode control signal, and a second end of the first switch tube is connected to the first current mirror and receives the second bias current; a second switch tube, wherein a control end of the second switch tube is connected to the first current mirror and the second end of the first switch tube and receives the second bias current, a first end of the second switch tube is grounded, and a second end of the second switch tube is connected to the second current mirror and receives the third bias current; a first NOT gate, wherein an input end of the first NOT gate is connected to the second end of the second switch tube, and an output end of the first NOT gate outputs the first intermediate signal; and A latch, wherein a first input terminal of the latch is connected to an output terminal of the first NOT gate to receive the first intermediate signal, a second input terminal of the latch receives the power-on signal, and an output terminal of the latch outputs the trimming enable signal.

17. The trimming control circuit according to claim 5, characterized in that: The adjustment counting unit comprises: A first AND gate, wherein a first input terminal of the first AND gate receives the trimmed clock signal, and a second input terminal of the first AND gate receives the counting enable signal; A first NOR gate, wherein a first input terminal of the first NOR gate receives the counting enable signal, and a second input terminal of the first NOR gate receives the trimming enable signal; M cascaded first flip-flops, the input terminal of each of the first flip-flops is connected to the second output terminal of the first flip-flop, the first output terminal of each of the first flip-flops outputs a first output signal via a NOT gate, the first output terminal of each of the first flip-flops outputs a second output signal via two serially connected NOT gates, the clock terminal of each of the first flip-flops is connected to the second output terminal of the first flip-flop of the previous stage, the clock terminal of the first stage first flip-flop is connected to the output terminal of the first AND gate, and the reset terminal of each of the first flip-flops is connected to the output terminal of the first NOR gate; and N third AND gates, each of which inputs a first output signal or a second output signal corresponding to each of the M first flip-flops, and an output terminal of each third AND gate outputs a corresponding trimming bit control signal, , and M and N are positive integers.

18. The trimming control circuit according to claim 14, characterized in that: The anti-false triggering unit comprises: a second NOT gate, wherein an input end of the second NOT gate receives the trimming enable signal; a first pulse generating unit, receiving the Nth trimming bit control signal, and outputting a first pulse signal based on the Nth trimming bit control signal of a first level; a first OR gate, wherein a first input terminal of the first OR gate is connected to an output terminal of the second NOT gate, and a second input terminal of the first OR gate is connected to the first pulse generating unit to receive the first pulse signal; and A counter, wherein a clock end of the counter receives the trimmed clock signal, a reset end of the counter is connected to an output end of the first OR gate, an output end of the counter outputs the counting enable signal, and the counter is configured to count after at least one cycle of the trimmed clock signal.

19. The trimming control circuit according to claim 16, characterized in that: The first current mirror comprises: a fifth switch tube, wherein a control end of the fifth switch tube is connected to the second end thereof and receives the input current, and a first end of the fifth switch tube is grounded; a sixth switch tube, wherein a control end of the sixth switch tube is connected to the control end of the fifth switch tube, a first end of the sixth switch tube is grounded, and a second end of the sixth switch tube outputs the first bias current; and a seventh switch tube, wherein a control end of the seventh switch tube is connected to the control end of the fifth switch tube, a first end of the seventh switch tube is grounded, and a second end of the seventh switch tube outputs the second bias current; The second current mirror comprises: an eighth switch tube, wherein a control end of the eighth switch tube is connected to a second end thereof and receives the first bias current, and a first end of the eighth switch tube receives the power supply voltage; A ninth switch tube, wherein the control end of the ninth switch tube is connected to the control end of the eighth switch tube, the first end of the ninth switch tube receives the power supply voltage, and the second end of the ninth switch tube outputs the third bias current.

20. The trimming control circuit according to claim 16, characterized in that: The latch comprises: a fourth NOT gate, wherein an input end of the fourth NOT gate receives the trimming enable signal; A first NAND gate, wherein a first input terminal of the first NAND gate is connected to an output terminal of the fourth NAND gate; a second NAND gate, wherein a first input terminal of the second NAND gate is connected to an output terminal of the first NAND gate, a second input terminal of the second NAND gate receives the power-on signal, and an output terminal of the second NAND gate is connected to a second input terminal of the first NAND gate; and A fifth NOT gate, wherein the input end of the fifth NOT gate is connected to the output end of the second NAND gate, and the output end of the fifth NOT gate outputs the trimming enable signal.

21. A trimming control method, characterized in that: include: latching the trim mode control signal according to the power-on signal to generate a trim enable signal; and counting the received trimming clock signal according to the trimming enable signal and the counting enable signal, and outputting a trimming position control signal correspondingly when counting one cycle of the trimming clock signal; Whether to blow the corresponding fuse is controlled according to the trimming mode control signal, the master control signal and the corresponding trimming position control signal, and N is a positive integer.

22. The adjustment control method according to claim 21, characterized in that: When the power-on signal is powered on, the trimming mode control signal in the effective state is latched to generate a trimming enable signal in the effective state, and the trimming mode is entered; After entering the trimming mode, the permanent trimming mode or the pre-trimming mode is entered according to the trimming mode control signal.

23. The adjustment control method according to claim 22, characterized in that: In the permanent trimming mode, the corresponding fuse is controlled to be blown by the trimming bit control signal in the corresponding valid state and the master control signal in the valid state.

24. The adjustment control method according to claim 22, characterized in that: In the pre-trim mode, the corresponding fuse is controlled not to be blown.

25. The trimming control method according to claim 21, characterized in that: Also includes: A simulated trimming signal or a real trimming signal is generated according to whether the corresponding fuse is blown.

26. The adjustment control method according to claim 25, characterized in that: When the corresponding fuse is not blown, the simulated trimming signal is reset at the next power-on.

27. The trimming control method according to claim 25, characterized in that: When the corresponding fuse is blown, the real trimming signal continues to be outputted at the next power-on.

28. The trimming control method according to claim 25, characterized in that: Also includes: The voltage of the connection node between the fuse control module and the fuse is reset when the power-on signal is powered on, so as to reduce the interference to the voltage of the suspended connection node when the fuse is blown.

29. A chip, characterized in that: include: N trimming circuits, each trimming circuit comprising a fuse; as well as The trimming control circuit as claimed in any one of claims 1 to 20.

Images