Artificial synapses based on self-selected memory cells

Abstract

Apparatus and method for implementing artificial synapses using an SSM cell. A leakage integrated discharge circuit can provide a feedback signal to the SSM cell in response to a threshold number of pulses applied from a signal line to the gate. The final state of the SSM cell may depend on the time difference between the latest threshold number of pulses and the initial pulse of the feedback signal.

Description

Technical Field

[0001] This disclosure generally relates to memory, and more specifically, to apparatus and methods associated with implementing artificial synapses using self-selected memory. Background Technology

[0002] Memory devices are typically provided as internal circuits, semiconductor circuits, or integrated circuits in computers or other electronic devices. Many different types of memory exist, including volatile and non-volatile memory. Volatile memory requires power to maintain its data and includes random access memory (RAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM), among others. Non-volatile memory provides permanent data by retaining the stored data when no power is supplied and includes NAND flash memory, NOR flash memory, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), erasable programmable ROM (EPROM), and resistive variable memory, such as phase-change random access memory (PCRAM), resistive random access memory (RRAM), and magnetoresistive random access memory (MRAM).

[0003] Memory is also used as a volatile and non-volatile data storage device for a wide range of electronic applications. These include, but are not limited to, personal computers, portable memory sticks, digital cameras, cellular phones, portable music players such as MP3 players, movie players, and other electronic devices. Memory cells can be arranged in an array, wherein the array is used in a memory device.

[0004] Various computing systems include several processing resources coupled to memory (e.g., a memory system), which is accessed in association with a set of execution instructions (e.g., programs, applications, etc.). The processing resources can execute instructions to perform artificial intelligence (AI). The processing resources can be dedicated to performing AI. AI may involve learning and / or problem-solving. For example, AI may be characterized by its ability to solve problems and learn, thereby increasing the success rate of problem-solving with time and / or the number of instances identified. AI may also include the ability to perceive the environment corresponding to the problem being solved. For example, AI can be used to identify features in an image. Success and failure in identification can be used to improve the success rate of feature recognition. Attached Figure Description

[0005] Figure 1 This is a block diagram of a device in the form of a computing system including a memory device, according to several embodiments of the present disclosure.

[0006] Figure 2 This is a block diagram of an SSM unit according to several embodiments of the present disclosure.

[0007] Figure 3 This is a block diagram of an artificial synapse according to several embodiments of the present disclosure.

[0008] Figure 4 This is a block diagram illustrating the setup and reset distribution of an SSM cell array according to several embodiments of the present disclosure.

[0009] Figure 5 This is a block diagram of long-term boost (LTP) and long-term suppression (LTD) for an SSM cell according to several embodiments of the present disclosure.

[0010] Figure 6 This is a block diagram of a presynaptic artificial neuron (PRE), a postsynaptic artificial neuron (POST), and an artificial synapse according to several embodiments of the present disclosure.

[0011] Figure 7 This is a block diagram illustrating the input and output of a neural network and the initial state of the neural network according to several embodiments of the present disclosure.

[0012] Figure 8 Example flowcharts of methods for implementing artificial synapses using SSM units according to several embodiments of the present disclosure are shown.

[0013] Figure 9 An example machine of a computer system is shown, which can execute a set of instructions within the computer system to cause the machine to perform the various methods discussed herein. Detailed Implementation

[0014] This disclosure includes apparatus and methods related to implementing artificial synapses using self-selected memory (SSM) cells. In some instances, a leak-in integrated discharge circuit can be configured to provide a feedback signal to the SSM cell in response to a threshold number of pulses applied to the gate of a transistor coupled to the SSM cell, wherein the provided threshold number of pulses originate from a signal line coupled to the gate. The final state of the SSM cell may depend on the time difference between the latest threshold number of pulses and the initial pulse of the feedback signal.

[0015] Neuromorphic computing architectures encompass neuro-biological architectures that utilize hardware and / or software to simulate those present in biological neural systems. A neuromorphic computing architecture may contain a multi-layered neuronal architecture called a perceptron. Neurons in the multi-layered neuronal architecture of a neuromorphic computing architecture may be referred to as artificial neurons. Artificial neurons can combine one or more received inputs to produce an output. As used herein, the term "artificial" refers to a circuit system configured to represent a biological system. For example, an artificial neuron may contain a circuit system configured to simulate and / or perform the functions of a biological neuron.

[0016] Artificial synapses can be used to propagate the output of a first artificial neuron to a second artificial neuron. Artificial synapses can facilitate connections between neurons and may include configurable weights. In several instances, artificial synapses can be implemented using an SSM unit. The SSM unit can store configurable weights.

[0017] Compared to using different resistors or other types of memory cells in artificial synapses, implementing artificial synapses using SSM cells reduces power consumption. The contribution to energy dissipation can come from the presynaptic artificial neuron (PRE) spike events that trigger current spikes. The use of SSM cells for setup and / or reset transitions exhibits low current leakage compared to using different resistors or memory cells in artificial synapses. Low current leakage results in lower energy consumption values ​​than those obtained using phase-change memory (PCM) and / or resistive RAM (RRAM). SSM cells can be implemented in dense strafed memory arrays with parallelism and energy efficiency, enabling the simulation of biological neuromorphic computing architectures using SSM cells. Given that SSMs are inherently binary, using SSM cells to represent synapses also emphasizes the binary functionality of the synapse. For example, the use of phase-change memory (PCM) in artificial synapses complicates the binary functionality of the artificial synapse, given that PCMs accommodate multiple voltage threshold levels.

[0018] As used herein, “several things” can refer to one or more such things. For example, “several memory devices” can refer to one or more memory devices. “Multiple things” means two or more. Additionally, designations such as “N” as used herein, especially with respect to reference numerals in the drawings, indicate that such specified particular features may be included with several embodiments of this disclosure.

[0019] The figures in this document follow a numbering convention, wherein the first one or more digits correspond to the figure number, and the remaining digits identify elements or components in the figures. Similar elements or components between different figures may be identified by using similar digits. It should be understood that elements shown in various embodiments herein may be added, interchanged, and / or removed to provide several additional embodiments of this disclosure. Furthermore, the scale and / or relative dimensions of the elements provided in the figures are intended to illustrate certain embodiments of this disclosure and are not intended to be limiting.

[0020] Figure 1 This is a block diagram of a device in the form of a computing system 100 including a memory device 103, according to several embodiments of the present disclosure. As used herein, for example, the memory device 103, the memory array 110, and / or the host 102 may also be individually considered as a “device”.

[0021] In this example, system 100 includes a host 102 coupled to memory device 103 via interface 104. The computing system 100 can be a personal laptop, desktop computer, digital camera, mobile phone, memory card reader, or Internet of Things (IoT) enabled device, as well as various other types of systems. Host 102 may include several processing resources (e.g., one or more processors, microprocessors, or other types of control circuitry) capable of accessing memory 120. System 100 may include a separate integrated circuit, or both host 102 and memory device 103 may be on the same integrated circuit. For example, host 102 may be a system controller for a memory system including multiple memory devices 103, wherein the system controller provides access to the respective memory devices 103 via another processing resource, such as a central processing unit (CPU). Host 102 may also be an AI chip configured for AI processing.

[0022] exist Figure 1 In the example shown, host 102 is responsible for executing an operating system (OS) and / or various applications (e.g., AI programs), which can be loaded onto the host (e.g., from memory device 103 via control circuitry 105). The OS and / or various applications can be loaded from memory device 103 by providing access commands from host 102 to memory device 103 for accessing data including the OS and / or various applications. Host 102 can also access the data used by the OS and / or various applications by providing access commands to memory device 103 for retrieving data used during the execution of the OS and / or various applications.

[0023] For clarity, system 100 has been simplified to focus on features particularly relevant to this disclosure. For example, memory array 110 may be an SSM array. Array 110 may include memory cells arranged in rows coupled by access lines (which may be referred to in the art as word lines or select lines) and columns coupled by sense lines (which may be referred to in the art as digital lines, data lines, or bit lines). Although Figure 1 The illustration shows a single array 110, but the embodiments are not limited thereto. For example, the memory device 103 may include several arrays 110 (e.g., arrays of DRAM cells).

[0024] Memory device 103 includes address circuitry 106 to latch address signals provided via interface 104. The interface may include a physical interface employing, for example, a suitable protocol (e.g., a data bus, address bus, and command bus, or a combination of data / address / command buses). This protocol may be custom or proprietary, or interface 104 may employ standardized protocols such as PCIe, Gen-Z, or Cache Coherent Interconnect for Accelerators (CCIX). Address signals are received and decoded by row decoder 108 and column decoder 112 to access memory array 110. Data can be read from memory array 110 by sensing voltage and / or current changes on a sensing line using sensing circuitry 111. Sensing circuitry 111 may include, for example, a sensing amplifier that can read and latch pages (e.g., rows) of data from memory array 110. I / O circuitry 107 is used for bidirectional data communication with host 102 via interface 104. Read / write circuitry 113 is used to write data to or read data from memory array 110. As an example, circuit system 113 may include various drivers, latching circuit systems, etc.

[0025] Control circuitry system 105 decodes signals provided by host 102. These signals may be commands provided by host 102. These signals may include chip enable signals, write enable signals, and address latch signals for controlling operations performed on memory array 110, including data read operations, data write operations, and data erase operations. In various embodiments, control circuitry system 105 is responsible for executing instructions from host 102. Control circuitry system 105 may include a state machine, sequencer, and / or some other type of control circuitry system, which may be implemented in hardware, firmware, or software, or any combination thereof. In some instances, host 102 may be a controller external to memory device 103. For example, host 102 may be a memory controller coupled to the processing resources of a computing device.

[0026] In some instances, memory array 110 can be configured to represent a neuromorphic computing architecture. A neuromorphic computing architecture can be implemented using SSM cells. An SSM cell is a memory cell comprising a single chalcogenide material that operates as both a selection component and a storage component.

[0027] After access, the memory cell can be read or sensed by the sensing circuitry system 111 to determine the programming state of the memory cell. For example, a voltage can be applied to the memory cell (using appropriate access and sensing lines), and the presence of the resulting current through the memory cell can depend on the applied voltage and a threshold voltage of the memory cell. By evaluating the voltage that causes the current flow, the logic state of the memory cell can be determined.

[0028] In addition to the SSM unit, the artificial synapse may further include one or more transistors. The one or more transistors discussed herein may be field-effect transistors (FETs), including three-terminal devices comprising a source, drain, and gate, as well as other types of transistors.

[0029] Various memory cells of memory device 103 can be grouped into memory cells (e.g., neural memory cells) configured to store weights. A memory controller can be coupled to the neural memory cell and is referred to as a neural memory cell controller. The neural memory cell can be configured to mimic a neurobiological architecture. The neural memory cell can take full advantage of the properties of the chalcogenide material within the memory cell to alter the properties of the chalcogenide material. The altered properties of the chalcogenide material can change the threshold voltage of the memory cell. As a result of neural memory cell learning, the threshold voltage of the neural memory (multiple memory cells) of the neural memory cell can be interpreted as weights. Host 102 and / or a portion or the entire memory device 103 can generate and / or receive learning algorithms. The learning algorithm is an algorithm that can be used for machine learning to help the neural memory cell mimic (e.g., simulate, emulate, etc.) a neurobiological architecture.

[0030] The learning algorithm may include variables for learning events. Learning events may be the number of pulses of voltage values, the magnitude of voltage values ​​(e.g., above or below a threshold voltage), and / or the duration for which pulses are applied to a memory cell (e.g., a variable-resistance memory cell) of the neural memory cell. A neural memory cell controller (e.g., controller circuitry 105) may apply the learning algorithm to the array to attempt to elicit learning events from the variable-resistance memory cells of the neural memory cell.

[0031] Figure 2 This is a block diagram of an SSM unit according to several embodiments of the present disclosure. Figure 2 The SSM cell 219 is included as part of the memory array 210. Although the memory array 210 shows only a single memory cell 219, the memory array 210 is similar to... Figure 1 The memory array 110 may contain more memory cells, sensing lines, and access lines than those shown herein. The memory array 210 may also include sensing lines 215 and access lines 214.

[0032] In some cases, memory cell 219 may be an SSM cell and may include a first electrode 216, a chalcogenide material 218, and a second electrode 217. Electrodes 216 and 217 may also be referred to as the bottom electrode (BE) and the top electrode (TE), respectively. In some embodiments, signal lines (e.g., Figure 1The access lines 214 and sensing lines 215 may include electrode layers (e.g., conformal layers) instead of electrodes 216 or 217, and thus may include multilayer access lines. In such embodiments, the electrode layers of the signal lines may interface with a memory material (e.g., chalcogenide material 218). In some embodiments, the signal lines may interface directly with the memory material (e.g., chalcogenide material 218) without an electrode layer or electrodes therein. Chalcogenide material 218 in Figure 3 It is shown as a storage device (SD).

[0033] The architecture of memory array 210 can be referred to as an example of a crossover architecture in some cases because memory cells 219 can be formed at the topological crossover point between access line 214 and sensing line 215, such as... Figure 2 As shown in the diagram, this type of cross-point architecture offers relatively high-density data storage at a lower production cost compared to some other memory architectures. For example, memory arrays with a cross-point architecture can have smaller memory cells and therefore support increased memory cell density compared to some other architectures.

[0034] DRAM memory arrays can use transistors as three-terminal devices as selection components for each memory cell, and therefore a DRAM memory array including a given number of memory cells can have a larger memory cell area compared to a memory array with a cross-point architecture including the same number of memory cells. Although Figure 2 The example illustrates a single-layer memory array (e.g., a memory stack), but other configurations may contain any number of stacks. In some embodiments, one or more of the memory stacks may contain optional memory cells comprising chalcogenide material 218.

[0035] Memory cells (e.g., memory cell 219) may be incorporated as part of a memory cell configured to store values, which in some cases may be or include analog values. In some memory devices, applying an electronic pulse to a chalcogenide material 218 can affect the chalcogenide material 218, which in some cases may contain altered physical forms. Some physical forms of the chalcogenide material 218 include amorphous and crystalline states. These physical forms have different resistances, thereby allowing the chalcogenide material 218 to maintain a physical state that may be referred to as storing logic (e.g., sensing logic and / or analog values). In some embodiments of the memory device, applying an electronic pulse to the chalcogenide material 218 may not change the state of the chalcogenide material 218, and the chalcogenide material 218 may remain amorphous. For example, set and reset states can be obtained by applying pulses of different (e.g., opposite) polarities; furthermore, in some embodiments, a threshold voltage can be modified or tuned by applying a voltage pulse of appropriate amplitude and / or polarity.

[0036] Figure 3 This is a block diagram of an artificial synapse 323 according to several embodiments of the present disclosure. The artificial synapse 323 may be part of an artificial sensor 320. The artificial synapse 323 may connect a presynaptic artificial neuron (PRE) 321 to a postsynaptic artificial neuron (POST) 322.

[0037] The artificial synapse 323 may include an SSM unit 324 and a transistor 325. That is, the artificial synapse 323 comprises a hybrid single-transistor single-SSM (1T1SSM) structure. Although Figure 3 The diagram shows a 1T1SSM structure, but other artificial synaptic structures, such as 2T1SSM or 4T1SSM structures and others, can be implemented. Transistor 325 may include a gate, a first terminal, and a second terminal. The gate may be coupled to a signal line. The signal line may couple the gate of transistor 325 to PRE 321. Although PRE 321 is shown as an artificial neuron, PRE 321 may also represent a spike neural network. For example, PRE 321 may be a portion of the spike neural network that provides PRE spike pulses to transistor 325.

[0038] The SSM unit can have a leakage current of less than one picoampere. The feedback signal can be on the order of hundreds of millivolts. The duration of the initial pulse and subsequent pulses of the feedback signal can be on the order of tens of nanoseconds. The energy consumption associated with the chalcogenide material being in one of two states can be on the order of less than one picojoule.

[0039] SSM unit 324 can be coupled to the first terminal of transistor 325. Leakage integrated discharge circuit 332 can be coupled to the second terminal of transistor 325.

[0040] The SSM unit can be a variable resistive memory unit and can be arranged in an array (e.g., a neural memory unit) to simulate biological functions such as learning. The SSM unit contains a chalcogenide material that can change its logical state (e.g., set or reset) in response to the magnitude of a voltage. The set state can be conductive (e.g., low resistance to current flow), and the reset state can be less conductive (e.g., higher resistance to current flow). The threshold voltage change of the chalcogenide material in the self-selected memory unit can represent synaptic weights in a neuromorphic memory system. Changes in synaptic weights can represent and / or be interpreted as representing learning and other biological functions.

[0041] In various cases, electrodes can couple memory cells to access lines or sensing lines. As used herein, the term "electrode" can refer to an electrical conductor and, in some cases, can serve as an electrical contact to other components of the memory cell or memory array. An electrode may comprise traces, wires, conductive lines, conductive layers, etc., providing a conductive path between elements or components of the memory array 110 of memory device 103. Therefore, the term "electrode" can refer to an access line or sensing line in some cases, and, in others, to an additional conductive element serving as an electrical contact between the access line and the memory cell.

[0042] In some embodiments, the memory cell may include a chalcogenide material positioned between a first electrode and a second electrode. The first electrode couples the chalcogenide material to an access line, and the second electrode couples the chalcogenide material to a sensing line. The first and second electrodes may be the same material (e.g., carbon) or different materials. In other embodiments, the memory cell may be directly coupled to one or more access lines, and electrodes other than the access lines may be omitted.

[0043] Chalcogenide materials can be materials or alloys containing at least one of the elements S, Se, and Te. Chalcogenide materials can be alloys containing S, Se, Te, Ge, As, Al, Sb, Au, indium (In), gallium (Ga), tin (Sn), bismuth (Bi), palladium (Pd), cobalt (Co), oxygen (O), silver (Ag), nickel (Ni), and platinum (Pt). Example chalcogenide materials and alloys may include, but are not limited to, Ge-Te, In-Se, Sb-Te, Ga-Sb, In-Sb, As-Te, Al-Te, Ge-Sb-Te, Te-Ge-A s, In-Sb-Te, Te-Sn-Se, Ge-Se-Ga, Bi-Se-Sb, Ga-Se-Te, Sn-Sb-Te, In-Sb-Ge, Te-Ge-Sb-S, T e-Ge-Sn-O, Te-Ge-Sn-Au, Pd-Te-Ge-Sn, In-Se-Ti-Co, Ge-Sb-Te-Pd, Ge-Sb-Te-Co, Sb-Te-B i-Se, Ag-In-Sb-Te, Ge-Sb-Se-Te, Ge-Sn-Sb-Te, Ge-Te-Sn-Ni, Ge-Te-Sn-Pd or Ge-Te-Sn-Pt. Examples of chalcogenide materials may also include SAG-based glass non-phase change materials, such as SeAsGe. Hyphenated chemical composition symbols as used herein indicate elements contained in a particular compound or alloy and are intended to represent all stoichiometry involving the indicated element. For example, Ge-Te may contain Ge x Te yWhere x and y can be any positive integers. Other examples of variable resistivity materials may comprise binary metal oxide materials or mixed-valence oxides containing two or more metals, such as transition metals, alkaline earth metals, and / or rare earth metals. Embodiments are not limited to one or more specific variable resistivity materials associated with memory elements of memory cells. For example, other examples of variable resistivity materials may be used to form memory elements and may comprise chalcogenide materials, colossal magnetoresistance materials, or polymer-based materials, etc.

[0044] Operations such as read and write operations can be performed on memory cells by activating or selecting access lines and sensing lines. Activating or selecting an access line or sensing line may involve applying a voltage to the corresponding line. Access lines and sensing lines may be made of conductive materials such as metals (e.g., copper (Cu), aluminum (Al), gold (Au), tungsten (W), titanium (Ti)), metal alloys, carbon, conductive doped semiconductors or other conductive materials, alloys, compounds, etc.

[0045] In some architectures, the logic storage devices of a cell (e.g., resistive components in a CBRAM cell, capacitive components in a FeRAM cell) can be electrically isolated from the sense line via a select component. The access line can be connected to and control the select component. For example, the select component can be a transistor, and the access line can be connected to the gate of the transistor.

[0046] As mentioned, the selection component can be a variable resistance component of a variable resistance memory cell that may include a chalcogenide material. Specifically, the variable resistance memory cell can be an SSM cell that includes a single material (e.g., a chalcogenide material) that can serve as both a selection component and a storage component for the memory cell. Activating the access line can cause an electrical connection or closed circuit between the logic storage device of the memory cell and its corresponding sensing line. The sensing line can then be accessed to read from or write to the memory cell. After selecting the memory cell, the resulting signal can be used to determine the stored logic state. In some cases, the first logic state may correspond to zero current or a negligible current passing through the memory cell, while the second logic state may correspond to a finite current. In some cases, the memory cell may include a self-selecting memory cell with two terminals, and the separate selection component may be omitted. Thus, one terminal of the self-selecting memory cell can be electrically connected to the access line, and the other terminal of the self-selecting memory cell can be electrically connected to the sensing line.

[0047] The chalcogenide material of the memory cell can remain in an amorphous state during access operations. In some cases, operating the memory cell may involve applying programming pulses of various shapes to the memory cell to determine a specific threshold voltage of the memory cell; that is, the threshold voltage of the memory cell can be modified by changing the shape of the programming pulses.

[0048] A specific threshold voltage for an SSM cell can be determined by applying read pulses of various shapes to the memory cell. For example, when the applied voltage of the read pulse exceeds the specific threshold voltage of the memory cell, a limited amount of current can flow through the memory cell. Similarly, when the applied voltage of the read pulse is less than the specific threshold voltage of the memory cell, no considerable amount of current can flow through the memory cell.

[0049] POST 322 may include a leakage integrated discharge circuit. The leakage integrated discharge circuit may be configured to receive inputs, integrate inputs, and provide an output (e.g., discharge). As used herein, the integrated input may include a combination input such that two separate inputs are combined into a single input. For example, the leakage integrated discharge circuit may receive multiple inputs including a first charge and a second charge. The first charge and the second charge may be combined (e.g., integrated) to generate a third charge. The third charge may be a combination of the first charge and the second charge. The integrated charge may decrease over time (e.g., leak). For example, the charge stored by the capacitor of the leakage integrated discharge circuit may decrease over time. The leakage integrated discharge circuit system may include an integrated circuit system 326. The leakage integrated discharge circuit also shows a graph 329. The integrated circuit system 326 may include a resistor 327 and a capacitor 328. The integrated circuit system 326 may also be referred to as a resistive-capacitive (RC) circuit reflecting the resistor 327 and the capacitor 328. The capacitor 328 may store charge such that the charge received at the capacitor 328 can be combined. Capacitor 328 can provide combined charge to a circuit system (not shown) configured to provide forward spike pulses and / or feedback signals. Over time, the charge stored in capacitor 328 can decrease (leakage). Resistor 327 can provide a rest potential for the described leakage integrated discharge circuit.

[0050] A feedback signal and / or forward spike pulse can be provided in response to the combined charge reaching a threshold. Graph 329 shows how the combined charge can increase and decrease over time as charge accumulates at capacitor 328. Graph 329 also shows how the combined charge reaches a threshold such that the feedback signal and / or forward spike pulse is provided by artificial synapse 323.

[0051] In some instances, the leakage integrated discharge circuit can also provide a feedback signal to the artificial synapse 323. The integrated circuit system 326 can receive multiple different charges from multiple different artificial synapses including the artificial synapse 323. The integrated circuit system 326 can combine multiple different voltages into a signal known as V. int A single voltage. Although Figure 3 Artificial synapse 323 is shown to provide voltage to POST 322, but POST 322 may receive multiple voltages from multiple artificial synapses 323.

[0052] POST 322 may include a comparator, which may include circuitry configured to compare two voltages. In response to V int Exceeding the comparator's threshold voltage (V TH POST 322 can provide a feedback signal to the artificial synapse 323. The feedback signal may contain two pulses. The first pulse transmits a positive field across the SSM unit 324. The second pulse transmits a negative field across the SSM unit 324.

[0053] The specific shape of the feedback signal can cause a change in the resistance of the SSM cell. The resistance of the SSM cell can depend on the time delay between the signal provided by PRE321 and the signal provided by POST 322 (e.g., the feedback signal). The shape of the feedback signal and its effect on the resistance of the SSM cell can be consistent with the Spike Pulse Time-Related Plasticity (STDP) protocol. Therefore, the STDP protocol specifies that if the signal provided by PRE 321 to POST 322 (e.g., the pre-spiking pulse) tends to occur immediately before the feedback signal of POST 322, then the future signal provided by PRE 321 is stronger. The STDP protocol also specifies that if the signal provided by PRE 321 tends to occur immediately after the feedback signal, then the future signal provided by PRE 321 is weaker. The strength of the signal provided by PRE 321 is determined by the resistivity of the SSM cell. For example, a weak resistivity of the SSM cell provides a strong signal provided by PRE 321, while a strong resistivity of the SSM cell provides a weak signal provided by PRE 321. As used herein, the signals provided by PRE 321 may include signals provided by PRE 321 to transistor 325 and / or signals provided by transistor 325 to POST 322.

[0054] The high resistivity of SSM unit 324 provides a low voltage that defines the reset state. The low resistivity of SSM unit 324 provides a high voltage that defines the set state of SSM unit 324.

[0055] POST 322 maintains the TE of SSM cell 324 at a constant voltage. A signal supplied to the gate of transistor 325 by PRE 321 activates transistor 325. The signal supplied by PRE 321 can have a voltage V that activates transistor 325. G The SSM unit 324 can provide charge to the POST 322 based on the activation of the transistor 325, the constant charge provided by the POST 322, and the resistivity of the SSM unit 324. For example, the charge provided to the POST 322 may depend on the resistance of the SSM unit 324. The SSM unit 324 can provide charge to the first terminal of the transistor 325. Based on activation, the transistor 325 can provide the charge received from the first terminal through the second terminal.

[0056] Depending on the time difference between the signal provided by PRE 321 (e.g., a pre spike pulse) and the signal provided by POST (e.g., a feedback spike pulse), the feedback spike pulse can induce LTP or LTD in SSM cell 324. The feedback signal can contain both positive and negative fields. The feedback signal can set the resistance of SSM cell 324. The resistance can also represent the weights of the SSM cell, such that the weights are combined with the PRE spike pulse provided by PRE 321 to determine the voltage supplied to POST 322.

[0057] Figure 4 This is a block diagram illustrating the setup and reset distribution of an SSM cell array according to several embodiments of the present disclosure. Figure 3 The feedback signal described herein triggers a setting transition and a reset transition.

[0058] Setting the conversion describes the SSM cell as having high resistance. An SSM cell with high resistance provides low charge to the POST. Resetting the conversion describes the SSM cell as having low resistance. An SSM cell with low resistance provides high charge to the POST.

[0059] Therefore, the x-axis 431 of graph 430 represents the threshold voltage of the SSM cell in millivolts. The y-axis 432 of graph 430 represents the statistical deviation, expressed as the standard deviation (σ) from zero.

[0060] Figure 5 This is a block diagram of LTP 541 and LTD 546 for an SSM unit according to several embodiments of the present disclosure. LTP 541 may be the result of a positive time delay between the PRE spike pulse and the feedback spike pulse. LTD 546 may be the result of a negative time delay between the PRE spike pulse and the feedback spike pulse.

[0061] A negative time delay is characterized by providing a feedback spike pulse after the PRE spike pulse is provided. A positive time delay is characterized by providing a feedback spike pulse before the PRE spike pulse is provided.

[0062] For example, if a PRE spike pulse 542-1 is provided before the feedback spike pulse 543-1, the feedback signal provided by the POST can induce an LTP 541 in the SSM cell. That is, the feedback signal can induce a low resistivity in the corresponding SSM cell, making the signal provided by the SSM cell stronger than when the SSM cell has a high resistivity. If a PRE spike pulse 542-2 is provided after the feedback spike pulse 543-2, the feedback signal provided by the POST can induce an LTD 546 in the SSM cell. That is, the feedback signal can induce a high resistivity in the corresponding SSM cell, making the signal provided by the SSM cell weaker than when the SSM cell has a low resistivity.

[0063] Feedback spike pulses 543-1 and 543-2 are both displayed with positive and negative fields. Positive and negative time delays can be calculated based on the positive field of the feedback signal. In some instances, the time delay can be calculated from either the beginning or end of the positive field. The time delay can be measured from a reference point of the PRE spike pulse. For example, the time after the PRE spike pulse has been issued is considered positive, and the time before the PRE spike pulse has been issued is considered negative.

[0064] Figure 5 Figure 506 is also shown. Figure 506 includes an x-axis showing time delays in milliseconds (ms). The y-axis of Figure 506 shows voltage. Figure 506 shows that if the feedback signal provided to the artificial synapse triggers an LTP, then the voltage 547 provided by the artificial synapse increases. Figure 506 also shows that if the feedback signal provided to the artificial synapse triggers an LTD, then the voltage 546 provided by the artificial synapse decreases. However, if the time difference between the PRE spike pulse and the feedback spike pulse is greater than a first threshold, then the feedback signal provided to the artificial synapse may not trigger an LTP or LTD and may remain unchanged. If the time difference between the PRE spike pulse and the feedback spike pulse is less than a second threshold, then the feedback signal provided to the artificial synapse may not trigger an LTP or LTD and may remain unchanged.

[0065] Figure 6This is a block diagram of PRE 601-1, 601-2, 601-3... and 601-9, POST 622, and artificial synapses 623-1, 623-2, 623-3... 623-9 according to several embodiments of this disclosure. PRE 601-1, 601-2, 601-3... and 601-9, referred to as PRE 601, can be coupled to POST 622 via artificial synapses 623-1, 623-2, 623-3... 623-9. For example, PRE 601-1 is coupled to artificial synapse 623-1, PRE 601-2 is coupled to artificial synapse 623-2, PRE 601-3 is coupled to artificial synapse 623-3... and PRE 601-9 is coupled to artificial synapse 623-9.

[0066] PRE 601, artificial synapse 623, and POST 622 may include neural network 600. Although neural network 600 has already... Figure 6 While simplified, the neural network 600 may contain more or fewer PREs, artificial synapses, and / or POSTs compared to those shown in this paper.

[0067] POST 622 can receive multiple charges from artificial synapse 623. POST 622 can integrate the multiple charges into a single charge. In response to the integrated charge exceeding a threshold, POST 622 can provide a POST spike pulse and generate a unique feedback signal, which is then provided to each of the artificial synapses 623 to update the weights stored in the artificial synapses 623.

[0068] The feedback signal can alter the conductivity of the chalcogenide material contained in the artificial synapse 623. The feedback signal can make the conductivity of the SSM units contained in the artificial synapse 623 stronger or weaker. The conductivity of the SSM units reflects the weighting of the artificial synapse 623.

[0069] PRE 601 can receive input and provide PRE spikes based on the input. The weights stored by the artificial synapse 623 can be the result or output of the neural network 600. Although the POST spike can represent the logical result of the network, the POST spike can be used to update the weights of the artificial synapse 623, making the artificial synapse 623 usable to represent the result of the neural network 600. Given that the artificial synapse 623 includes SSM units, the artificial synapse 623 can be read.

[0070] For example, if the artificial synapse 623 is in a reset state (e.g., non-conductive), the state of the SSM cell managed by the artificial synapse 623 can be logic 0. If the artificial synapse 623 is in a set state, the state of the SSM cell managed by the artificial synapse 623 can be logic 1. The reset state represents bit 0, and the set state represents bit 1. However, the reset and set states can represent other bits or logic states of the SSM cell. The logic state of the artificial synapse 623 can be converted into color, for example, in a pattern learning example.

[0071] Figure 7 This is a block diagram of the input 771 and output 773 of a neural network according to several embodiments of the present disclosure, as well as the initial state of the neural network. The input 771 may comprise an image divided into nine segments. Each of the nine segments may, for example, represent a pixel of the image such that the image comprises nine pixels or nine segments.

[0072] Each segment can have one of two values. For example, each segment can have a first value representing a first color or a second value representing a second color. Logical values ​​for the colors of the image segments can be specified, such as 1 bit or 0 bits. Logical values ​​of the image can be provided to PRE as input. Input 771 reflects the X pattern. The X pattern is displayed as segments of the input with a logical 1-bit value, while the remainder of input 771 is displayed as segments with 0-bit values.

[0073] The initial state 772 of the neural network can be interpreted as an image, where each segment of the image includes the same color / logical state. Each logical state of the neural network can be stored in an artificial synapse. The artificial synapse can store the logical state in an SSM unit. For example, all SSM units hosted by the artificial synapse can have a reset state.

[0074] The input, along with random noise, can be fed into the neural network. The input and random noise can be provided randomly. As learning progresses, in response to the feedback signal provided by POST, the weights (e.g., conductivity) of the artificial synapse can be changed to mirror the input 771. The weights of the artificial synapse can be read to produce the output 773. Learning can be performed unsupervised. That is, learning can be performed without processing the expected outcome.

[0075] Figure 8An example flowchart of a method for supplementing AI processing in supplemental memory according to several embodiments of the present disclosure is shown. At 850, a spike neural network may provide a first signal to a transistor of an artificial synapse. The first signal may also be referred to as a PRE spike pulse. At 852, in response to receiving the first signal, the transistor may be activated to provide a second signal from the SSM cell to the leakage integrated discharge circuit. Activating the transistor provides a conductive path from the SSM cell to the leakage integrated discharge circuit.

[0076] Providing a conductive path from the SSM cell to the leakage integrated discharge circuit allows the SSM cell to deliver voltage to the leakage integrated discharge circuit. The magnitude of the voltage provided by the SSM cell can depend on a weighted value stored by the SSM cell in the form of resistance of the chalcogenide material comprising the SSM cell. For example, a first voltage can be provided to the SSM cell, and a second voltage can be provided from the SSM cell to the leakage integrated discharge circuit, wherein the difference between the first voltage and the second voltage can be attributed to the resistance (weight) of the SSM cell.

[0077] At 854, the leakage integrated discharge circuit can provide a feedback signal to update the SSM cell. The feedback signal can set the resistance of the SSM cell. The feedback signal can trigger a set state of the SSM cell in response to a first signal provided by the leakage integrated discharge circuit before the feedback signal is provided. The feedback signal can be provided by the leakage integrated discharge circuit in response to the integral of a second signal being greater than a threshold voltage (compared at the leakage integrated discharge circuit). The feedback signal can trigger a reset state of the SSM cell in response to a first signal provided after the feedback signal.

[0078] In some instances, burst patterns can be used to reduce the energy consumed by neural networks. Multiple SSM units can be updated using burst patterns in response to the integration of voltages provided by artificial synapses to reach a threshold voltage.

[0079] In burst mode, a voltage threshold is used to initiate the integration of a voltage supplied by an artificial synapse, which is provided to the POST using a burst pulse. The voltage threshold can be provided using a burst pulse instead of a direct current (DC) voltage. The pulse saves energy due to the intermittent delivery of the current to be used as the threshold voltage in the POST.

[0080] Figure 9 An example machine of computer system 940 is shown, which can execute a set of instructions within the computer system to cause the machine to perform the various methods discussed herein. In various embodiments, computer system 940 may correspond to including, coupled to, or utilizing a memory subsystem (e.g., Figure 1 The memory device 103) or the controller that can be used to execute the controller (e.g., Figure 1 The system operating the control circuit system 105) (e.g., Figure 1 (System 100). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment within the capacity of a server or client machine in a client-server network environment.

[0081] A machine can be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network device, server, network router, switch, or bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions specifying actions to be taken by the machine. Furthermore, while a single machine is shown, it should also be understood that the term "machine" includes any collection of machines that individually or collectively execute (one or more) sets of instructions to perform any one or more of the methods discussed herein.

[0082] Example computer system 940 includes processing devices 902 that communicate with each other via bus 930, main memory 904 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), static memory 906 (e.g., flash memory, static random access memory (SRAM), etc.), and data storage system 918.

[0083] Processing device 902 represents one or more general-purpose processing devices, such as microprocessors, central processing units, or the like. More precisely, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets or combinations of instruction sets. Processing device 902 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, or the like. Processing device 902 is configured to execute instructions 926 for performing the operations and steps discussed herein. Computer system 940 may further include a network interface device 908 for communication via network 920.

[0084] Data storage system 918 may include machine-readable storage medium 924 (also referred to as computer-readable medium) on which one or more sets of instructions 926 or software embodying any one or more of the methods or functions described herein are stored. The instructions 926 may also reside wholly or at least partially within main memory 904 and / or processing device 902 during execution by computer system 940, which also constitute the machine-readable storage medium.

[0085] In one embodiment, instruction 926 includes implementation corresponding to Figure 1 The machine-readable storage medium 924 is shown as a single medium in the exemplary embodiment, but the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions that are executable by a machine and causing a machine to perform any one or more of the methods of this disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0086] Although specific embodiments have been shown and described herein, those skilled in the art will understand that arrangements calculated to achieve the same results may replace the specific embodiments shown. This disclosure is intended to cover modifications or variations of various embodiments of this disclosure. It should be understood that the above description is illustrative rather than restrictive. After reviewing the above description, combinations of the above embodiments and other embodiments not specifically described herein will be apparent to those skilled in the art. The scope of the various embodiments of this disclosure includes other applications using the above structures and methods. Therefore, the scope of the various embodiments of this disclosure should be determined with reference to the appended claims and the full scope of the equivalents to which such claims are given.

[0087] In the foregoing detailed embodiments, various features are grouped together in a single embodiment for the purpose of simplification. This approach of the present disclosure should not be construed as reflecting an intention that the disclosed embodiments of the present disclosure must use more features than those expressly stated in each claim. Rather, as reflected in the appended claims, the subject matter of the invention lies in fewer than all features of a single disclosed embodiment. Therefore, the appended claims are hereby incorporated into the detailed embodiments, wherein each claim is, in itself, a separate embodiment.

Claims

1. An apparatus for implementing artificial synapses using a self-selected memory, comprising: A transistor, comprising a gate, a first terminal, and a second terminal; The self-selected memory SSM cell is coupled to the first terminal; Signal lines that are coupled to the gate; as well as A leakage integrated discharge circuit is coupled to the SSM unit and also coupled to the second terminal; The leakage integrated discharge circuit is configured to provide a feedback signal to the SSM cell in response to a threshold number of pulses applied from the signal line to the gate; The final state of the SSM unit depends on the time difference between the latest threshold number of pulses and the initial pulse of the feedback signal; The feedback signal is used to cause the chalcogenide material contained in the SSM unit to be in one of two states; The feedback signal includes the initial pulse and an additional pulse of opposite polarity; The SSM unit described therein has a leakage current of less than one picoampere; The feedback signal is on the order of hundreds of millivolts; The durations of the initial pulse and the additional pulse of the feedback signal are on the order of tens of nanoseconds; and The energy consumption associated with bringing the chalcogenide material to one of its two states is on the order of less than a picojoule.

2. The device of claim 1, wherein the signal line is coupled to a spike neural network to represent a presynaptic artificial neuron configured to collect sensory stimuli; The spike neural network is configured to provide the threshold number of pulses to the gate corresponding to the collected sensory stimuli; The transistor and the SSM unit represent artificial synapses; and The leakage integrated discharge circuit mentioned above represents a postsynaptic artificial neuron configured to update the synaptic weights of the artificial synapse.

3. The device of claim 1, wherein the leakage integrated discharge circuit includes a comparator having a threshold voltage coupled to a resistor-capacitor (RC) circuit.

4. The device according to claim 1, wherein the chalcogenide material serves as a switching device and a storage device.

5. The device of claim 4, wherein the SSM unit comprises a top electrode, a storage device SD, and a bottom electrode; The SD includes the chalcogenide material; The top electrode is coupled to the leakage integrated discharge circuit; and The bottom electrode is coupled to the first terminal.

6. The device of claim 1, wherein the feedback signal triggers a setting transition of the SSM unit in response to providing the latest threshold number of pulses prior to the initial pulse of the feedback signal.

7. The device of claim 1, wherein in response to providing the latest threshold number of pulses after the initial pulse of the feedback signal, the feedback signal triggers a reset transition of the SSM unit.

8. The device of claim 1, wherein the shape of the feedback signal affects the resistance of the SSM unit.

9. The device according to any one of claims 1 to 5, further comprising a plurality of transistors coupled to the SSM unit.

10. A method for implementing an artificial synapse using a self-selected memory, comprising: The first signal is provided to the transistor via a spike neural network; In response to receiving the first signal, the transistor is activated to provide a second signal from the self-selected memory (SSM) cell to the leakage integrated discharge circuit; as well as The SSM unit is updated by providing a feedback signal from the leakage integrated discharge circuit to the SSM unit, wherein the feedback signal sets the resistance of the SSM unit; The SSM unit is configured in response to a third signal provided by the leakage integrated discharge circuit after the first signal is provided to the transistor as an input to a different transistor.

11. The method of claim 10, wherein the SSM cell is reset in response to the third signal being provided by the leakage integrated discharge circuit prior to the first signal being provided to the transistor.

12. An apparatus for implementing artificial synapses using a self-selected memory, comprising: Multiple spike neural networks are configured to provide multiple first signals to multiple transistors; The plurality of transistors are coupled to a plurality of self-selected memory (SSM) cells and are configured to provide a plurality of second signals to the leakage integrated discharge circuit in response to activation of the plurality of transistors via the plurality of first signals. and The leakage integrated discharge circuit is configured to update the plurality of SSM units using a burst mode in response to integrating the plurality of second signals to reach a threshold, wherein the leakage integrated discharge circuit is further configured to generate different feedback signals for each of the plurality of SSM units.

13. The device of claim 12, wherein the leakage integrated discharge circuit is configured to receive pulses in burst mode, wherein the threshold describes the number of pulses.

14. The device of claim 13, wherein the leakage integrated discharge circuit is further configured to compare the plurality of second signals with the threshold using the pulse.

15. The device of claim 12, wherein the leakage integrated discharge circuit is further configured to update each of the SSM units based on a time difference between a corresponding first signal from the plurality of first signals and a corresponding second signal from a plurality of feedback signals provided by the leakage integrated discharge circuit.

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