Memory system and wafer

Abstract

To inhibit deterioration of communication reliability between a probe electrode and a pad electrode. A storage system of one embodiment has a wafer including a memory chip unit including a pad electrode including a first portion and a second portion electrically connected to each other and a memory cell array electrically connected to the pad electrode, and a prober capable of holding the wafer and performing reading and writing to the memory cell array. The prober includes a probe card including a probe electrode capable of contacting the pad electrode and a memory controller capable of performing reading and writing to the memory cell array via the probe electrode, and a moving mechanism that moves the probe card or the held wafer so that the pad electrode of the held wafer and the probe electrode are brought into contact with each other. The moving mechanism is capable of performing a first operation of bringing the probe electrode into contact with the first portion of the pad electrode and not into contact with the second portion and a second operation of bringing the probe electrode into contact with the second portion of the pad electrode and not into contact with the first portion.

Description

Technical Field

[0001] The implementation methods involve storage systems and chips. Background Technology

[0002] Given a wafer and a probe, the wafer has multiple NAND flash memory chips that serve as semiconductor memory, and the probe makes contact between pad electrodes on the wafer and probe electrodes.

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: U.S. Patent Application Publication No. 2014 / 0181376 Summary of the Invention

[0006] The technical problem to be solved by the present invention

[0007] The technical problem to be solved by this invention is to suppress the degradation of communication reliability between the probe electrode and the pad electrode.

[0008] Means for solving technical problems

[0009] The storage system of the embodiment includes: a first wafer including a first memory chip cell, the first memory chip cell including a first pad electrode and a first memory cell array electrically connected to the first pad electrode, the first pad electrode including a first portion and a second portion electrically connected to each other; and a detector capable of holding the first wafer and reading and writing to the first memory cell array of the held first wafer. The detector includes: a probe card including a first probe electrode capable of contacting the first pad electrode of the held first wafer, and a first memory controller electrically connected to the first probe electrode and capable of reading and writing to the first memory cell array via the first probe electrode; and a moving mechanism for moving the probe card or the held first wafer to bring the first pad electrode of the held first wafer into contact with the first probe electrode. The moving mechanism is capable of performing a first action that causes the first probe electrode to contact the first portion of the first pad electrode but not the second portion of the first pad electrode, and a second action that causes the first probe electrode to contact the second portion of the first pad electrode but not the first portion of the first pad electrode. Attached Figure Description

[0010] Figure 1 This is a block diagram used to explain the structure of the storage system according to the first embodiment.

[0011] Figure 2This is a side view used to explain the structure of the detector according to the first embodiment.

[0012] Figure 3 This is a top view used to explain the structure of the probe card according to the first embodiment.

[0013] Figure 4 This is a top view used to explain the structure of the memory chip according to the first embodiment.

[0014] Figure 5 It means Figure 4 A top view of the NAND chip cell in region V.

[0015] Figure 6 This is a block diagram used to illustrate the connection between the detector and the memory chip according to the first embodiment.

[0016] Figure 7 This is a block diagram used to explain the structure of the NAND chip cell according to the first embodiment.

[0017] Figure 8 This is a schematic diagram used to illustrate the structure of the NAND chip cell according to the first embodiment.

[0018] Figure 9 This is a circuit diagram used to explain the structure of the memory cell array according to the first embodiment.

[0019] Figure 10 This is a cross-sectional view used to illustrate the structure of the memory cell array according to the first embodiment.

[0020] Figure 11 It is along Figure 7 Cross-sectional view of the probe card and memory chip of the XI-XI line.

[0021] Figure 12 It is along Figure 7 Cross-sectional view of the probe card and memory chip of the XII-XII line.

[0022] Figure 13 This is a conceptual diagram of the probe management table in the storage system according to the first embodiment.

[0023] Figure 14 This is a flowchart used to explain the basic processing in the storage system according to the first embodiment.

[0024] Figure 15 This is a flowchart illustrating the selection process of wafers and pad groups in the memory system according to the first embodiment.

[0025] Figure 16 This is a flowchart used to explain the wafer transport process in the memory system according to the first embodiment.

[0026] Figure 17 This is a flowchart used to explain the write process in the storage system according to the first embodiment.

[0027] Figure 18 This is a schematic diagram used to illustrate the touch-down process in the storage system according to the first embodiment.

[0028] Figure 19 This is a schematic diagram used to explain the landing process in the storage system according to the first embodiment.

[0029] Figure 20 This is a flowchart used to explain the read process in the storage system according to the first embodiment.

[0030] Figure 21 This is a top view of the NAND chip cell involved in the first variation of the first embodiment.

[0031] Figure 22 This is a top view of the NAND chip cell involved in the second variation of the first embodiment.

[0032] Figure 23 This is a top view of the NAND chip cell involved in the third variation of the first embodiment.

[0033] Figure 24 This is a cross-sectional view of the probe card and memory chip involved in the fourth variation of the first embodiment.

[0034] Figure 25 This is a cross-sectional view of the probe card and memory chip involved in the fifth variation of the first embodiment.

[0035] Figure 26 This is a cross-sectional view of the probe card and memory chip involved in the second embodiment.

[0036] Figure 27 This is a cross-sectional view of the probe card and memory chip involved in the first variation of the second embodiment.

[0037] Figure 28 This is a cross-sectional view of the probe card and memory chip involved in the second variation of the second embodiment.

[0038] Figure 29 This is a cross-sectional view of the probe card and memory chip involved in the third variation of the second embodiment.

[0039] Figure 30This is a schematic diagram showing the structure of the reconfigured pad electrode according to the third embodiment.

[0040] Figure 31 This is a top view showing the positional relationship between the reconfigured pad electrode and the original pad electrode according to the third embodiment.

[0041] Figure 32 It is observed along the Y direction. Figure 31 A side view of the memory chip when the main elements of region XXXII are configured.

[0042] Figure 33 This is a top view showing the positional relationship between the reconfigured pad electrode and the original pad electrode in the first variation of the third embodiment.

[0043] Figure 34 This is a top view showing the positional relationship between the reconfigured pad electrode and the original pad electrode in the second variation of the third embodiment. Detailed Implementation

[0044] Hereinafter, embodiments will be described with reference to the accompanying drawings. Furthermore, in the following description, common reference numerals are used for constituent elements having the same function and structure. Additionally, when multiple constituent elements sharing common reference numerals are distinguished, subscripts are added to these common reference numerals for differentiation. Furthermore, when multiple constituent elements do not require special distinction, only common reference numerals are used for these multiple constituent elements, without subscripts.

[0045] 1. First Implementation Method

[0046] The storage system according to the first embodiment will be described. Hereinafter, a storage system having a storage chip and a detector will be described. The storage chip has multiple NAND chip cells (memory devices as NAND flash memory), and the detector is configured to include a probe card with multiple NAND controller chips installed, so that the storage chip and the probe card are physically contacted and electrically connected.

[0047] 1.1 Structure

[0048] The structure of the storage system according to the first embodiment will be described.

[0049] 1.1.1 Storage System Structure

[0050] First, use Figure 1 A summary of the structure of the storage system according to the first embodiment will be described. For example... Figure 1As shown, the storage system 1 operates, for example, based on instructions from the host device 2. The storage system 1 includes a detector 3, a wafer conveyor 4, and a wafer stocker 5.

[0051] The detector 3 has a probe card 20 and a control unit 30 for mounting the memory wafer 10 or the cleaning wafer 10c. The memory wafer 10 is a wafer before dicing or a wafer obtained by rewiring a wafer before dicing, containing multiple NAND flash memory chips (hereinafter referred to as "NAND chip cells" - not shown) arranged on a chip-by-chip basis, and having multiple pad electrodes 11 disposed on its surface. The cleaning wafer 10c is used for a cleaning process to improve the deteriorated electrical characteristics of the multiple probe electrodes 21 disposed on the probe card 20.

[0052] The probe card 20 includes a plurality of probe electrodes 21. The plurality of probe electrodes 21 are electrically connected to the memory controller (hereinafter referred to as "NAND controller chip"). The chip unit is mounted on the probe card 20.

[0053] The control unit 30 includes, for example, a temperature control system 31, a drive control system 32, and an interface control system 33, which control the overall operation of the detector 3.

[0054] The temperature control system 31 controls the temperature environment exposed to the probe card 20 and the memory chip 10 or cleaning chip 10c within the detector 3. In this embodiment, for example, the temperature control system 31 controls the temperature of the probe card 20 and the memory chip 10 or cleaning chip 10c in a manner that prevents the temperature from changing from a predetermined temperature.

[0055] The drive control system 32 has a mechanism that enables the memory chip 10 to move freely in three dimensions relative to the probe card 20. Moreover, the drive control system 32 has the function of controlling the mechanism to make the plurality of pad electrodes 11 on the memory chip 10 contact with the plurality of probe electrodes 21 on the corresponding probe card 20.

[0056] The interface control system 33 controls the communication between the host device 2 and the probe card 20. Furthermore, based on the control results of this communication, the interface control system 33 controls the temperature control system 31, the drive control system 32, and the wafer conveyor 4, etc.

[0057] The wafer conveyor 4 has the function of conveying the storage wafer 10 or the cleaning wafer 10c between the detector 3 and the wafer storage device 5.

[0058] The wafer storage device 5 stores multiple storage wafers 10 and cleaning wafers 10c that are not located on the detector 3.

[0059] 1.1.2 Detector Structure

[0060] Next, use Figure 2 The structure of the detector of the storage system according to the first embodiment will be described.

[0061] Figure 2 This is a side view schematically showing the structure of the detector 3 with the memory chip 10 installed. Hereinafter, the surface of the memory chip 10 relative to the detector 3 will be defined as the XY plane, and the direction perpendicular to the XY plane and from the memory chip 10 toward the probe card 20 will be defined as the Z direction (or the upward direction). Furthermore, the surface of the memory chip 10 that faces the probe card 20 will also be referred to as the "surface" or "upper surface" of the memory chip 10.

[0062] like Figure 2 As shown, the detector 3 has a base 41, multiple mounting stages 42 (42-1, 42-2 and 42-3), a wafer chuck 43, a head mounting stage 44, a stiffener 45, a retainer 46, a fastener 47 and a support 48.

[0063] A stage 42-1 is mounted on the upper surface of the base 41 via an X-displacement mechanism (not shown). The stage 42-1 is configured to move freely relative to the base 41 in the X direction via the X-displacement mechanism. A stage 42-2 is mounted on the upper surface of the stage 42-1 via a Y-displacement mechanism (not shown). The stage 42-2 is configured to move freely relative to the stage 42-1 in the Y direction via the Y-displacement mechanism. A stage 42-3 is mounted on the upper surface of the stage 42-2 via a Zθ-displacement mechanism (not shown). The stage 42-3 is configured to move freely relative to the stage 42-2 in the Z direction via the Zθ-displacement mechanism and to rotate freely in the XY plane. The stages 42-1 to 42-3 are included in the drive control system 32 and are part of a mechanism capable of freely displacing the memory chip 10 relative to the probe card 20.

[0064] A wafer chuck 43 is disposed on the upper surface of the stage 42-3 to hold the storage wafer 10. The wafer chuck 43 includes, for example, a temperature sensor and a heater and cooler (not shown) capable of temperature control of the storage wafer 10. The temperature control system 31 controls the heater and cooler based on information from the temperature sensor, thereby controlling the temperature of the storage wafer 10 via the wafer chuck 43. The temperature sensor, heater, and cooler are included in the temperature control system 31.

[0065] The head mount 44, for example, has a ring shape and is supported above the wafer chuck 43 by a support column 48. A ring-shaped reinforcing plate 45 and a retainer 46 are respectively disposed in the space inside the ring of the head mount 44, supporting the head mount 44. The reinforcing plate 45 is disposed on the upper part of the probe card 20, clamping the probe card 20 between itself and the retainer 46. The retainer 46 supports the probe card 20 in the space inside the ring of the retainer 46. The probe card 20 is fixed to the reinforcing plate 45 and the retainer 46 by a fastener 47, thereby fixing its position relative to the wafer chuck 43 (and the memory wafer 10 on the wafer chuck 43) and suppressing displacement caused by thermal expansion, etc.

[0066] Furthermore, a camera (not shown) can be provided on the head stage 44 to detect representative positions (e.g., the outer edge of the wafer, alignment marks set on the wafer, etc.) on the storage wafer 10 (or cleaning wafer 10c). The drive control system 32 can more accurately identify the reference position based on the information from the camera, enabling precise alignment.

[0067] Figure 3 This is a top view of the probe card 20 fixed inside the detector 3.

[0068] like Figure 3 As shown, the probe card 20 has its outer periphery fixed by a ring-shaped reinforcing plate 45, and multiple NAND controller chips 200 are disposed in the central portion of the probe card 20. Furthermore, in the storage system 1 according to this embodiment, the detector 3 is not subjected to large temperature changes and is maintained at a substantially constant temperature by the temperature control system 31. Therefore, the displacement caused by thermal expansion of the probe card 20 is suppressed to a small amount. Therefore, to address this displacement, the reinforcing plate 45 only needs to fix the outer periphery of the probe card 20, eliminating the need for a structure that fixes the central portion of the probe card 20. This allows for the mounting of more chips on the probe card 20.

[0069] Figure 4 This is a top view of the memory chip 10 held by the chip chuck 43. Figure 5 yes Figure 4 A magnified view of region V.

[0070] like Figure 4 As shown, the memory chip 10 is provided with a plurality of NAND chip cells 100. In addition, a plurality of alignment marks 12 are provided between the NAND chip cells 100. Each NAND chip cell 100 is the smallest unit of memory device that can be controlled based on control signals from the NAND controller chip 200.

[0071] like Figure 5As shown, a rectangular dicing line 13 is provided on the memory wafer 10 to surround the NAND chip cell 100, and an alignment mark 12 is provided on the outside of the dicing line 13. The dicing line 13 is the area traversed by the blade when the memory wafer 10 is separated into each NAND chip cell 100 by a dicing process. Furthermore, in this embodiment, the dicing process is not performed along the dicing line 13. However, the memory wafer 10 according to this embodiment can be manufactured as part of the manufacturing process of a memory device made by cutting NAND chip cells 100 into chip units, so a structure such as the dicing line 13, which is substantially unnecessary in this embodiment, can be provided.

[0072] A rectangular edge sealing portion 14 is provided inside the cutting line 13, and the circuit constituting the NAND chip unit 100 is disposed inside the edge sealing portion 14.

[0073] Inside the edge sealing portion 14, on the upper surface of the memory chip 10, a plurality of pad electrodes 11 are arranged in a matrix. More specifically, n pad electrodes 11_1, 11_2, 11_3, ..., 11_(n-2), 11_(n-1), and 11_n, electrically connected by wiring 15, are arranged sequentially along the -Y direction (n is an integer greater than or equal to 2). These n pad electrodes 11_1 to 11_n correspond to one pad unit PdU. Moreover, the plurality of pad units PdU, which are electrically disconnected from each other, are arranged along the X direction. A group of multiple independent pad electrodes 11_i (1≤i≤n) arranged along the X direction corresponds to one pad group PdGi. That is, n pad groups PdG1 to PdGn with equivalent functions are provided on the upper surface of one NAND chip cell 100.

[0074] 1.1.3 Communication Functional Structure of Detector and Memory Chip

[0075] Next, use Figure 6 The block diagram shown illustrates the structure of the communication function between the detector and the memory chip according to the first embodiment. Figure 6 The image shows an example of the connection relationship when the probe card 20 is brought into contact with and electrically connected to the NAND chip unit 100 by the drive control system 32.

[0076] like Figure 6 As shown, the interface control system 33 is connected to the host device 2 via a host bus. The host device 2 is, for example, a personal computer, and the host bus is, for example, PCIe (PCI Express) based. TM (Peripheral component interconnect express) bus.

[0077] The interface control system 33 includes, for example, a host interface circuit 331, a CPU (Central Processing Unit) 332, a ROM (Read Only Memory) 333, and a RAM (Random Access Memory) 334. Furthermore, the functions of each part 331-334 of the interface control system 33 described below can be implemented through either a hardware structure or a combination of hardware resources and firmware.

[0078] The host interface circuit 331 is connected to the host device 2 via the host bus, and forwards instructions and data received from the host device 2 and instructions from the CPU 332 to any of the multiple NAND controller chips 200 accordingly. In addition, it responds to instructions from the CPU 332 and forwards data from the NAND controller chip 200 to the host device 2.

[0079] The CPU 332 primarily controls the interfaces related to data transfer within the detector 3. For example, when the CPU 332 receives a write command from the host device 2, it responds by determining which NAND controller chip 200 will control the write process and then forwards the write data DAT to that NAND controller chip 200. The same applies to read and delete processes. Additionally, the CPU 332 performs various controls on other control systems within the detector 3 (temperature control system 31 and drive control system 32).

[0080] ROM 333 stores firmware for controlling the temperature control system 31, the drive control system 32, and multiple NAND controller chips 200.

[0081] RAM 334, for example, is DRAM (Dynamic Random Access Memory), which temporarily stores write data DAT and read data DAT. Additionally, RAM 334 is used as a working area for CPU 332, storing various management tables, etc. An example of a management table is a probe management table 335, which manages information such as how many times the probe electrode 21 has been attached and detached relative to the pad electrode 11 on the memory chip 10. Details regarding the probe management table 335 will be described later.

[0082] Each of the multiple NAND controller chips 200 on the probe card 20 is electrically connected to a group of multiple NAND chip units 100 within the memory chip 10.

[0083] exist Figure 6In the example, k NAND chip cells 100_1, 100_2, ..., 100_k are connected in parallel with one NAND controller chip 200. The multiple NAND controller chips 200, each connected to one of the k NAND chip cells 100_1 to 100_k, control the k NAND chip cells 1001 to 100_k in parallel based on instructions from the interface control system 33.

[0084] The NAND controller chip 200 is, for example, a SoC (System-on-a-chip) with FPGA (Field Programmable Gate Array) functionality, including a CPU 210, ROM 220, RAM 230, ECC circuitry 240, and NAND interface circuitry 250. Furthermore, the functions of each part 210-250 of the NAND controller chip 200 described below can be implemented through either a hardware structure or a combination of hardware resources and firmware.

[0085] The CPU 210 controls the overall operation of the NAND controller chip 200. For example, when the CPU 210 receives a write command from the host device 2 via the interface control system 33, it responds by issuing a write command to the NAND interface circuit 250. The same applies to read and delete operations. In addition, the CPU 210 performs various processes for controlling the NAND chip cell 100.

[0086] ROM 220 stores firmware and other components used to control the NAND chip unit 100.

[0087] RAM 230, for example, is DRAM, which temporarily holds the written and read data DAT. In addition, RAM 230 is also used as the working area of ​​CPU 210 to maintain various management tables, etc.

[0088] The ECC circuit 240 performs error detection and correction processing related to the data stored in the NAND chip cell 100. Specifically, during data writing, the ECC circuit 240 generates an error correction code and assigns it to the written data DAT. During data reading, it decodes the data to detect the presence or absence of error bits. Furthermore, when an error bit is detected, its position is determined, and the error is corrected. Error correction methods include, for example, hard bit decoding and soft bit decoding. Hard bit decoding codes used in hard bit decoding can include, for example, BCH (Bose-Chaudhuri-Hocquenghem) codes or RS (Reed-Solomon) codes. Soft bit decoding codes used in soft bit decoding can include, for example, LDPC (Low Density Parity Check) codes.

[0089] The NAND interface circuit 250 is connected to the NAND chip cell 100 via the NAND bus and manages communication with the NAND chip cell 100. Furthermore, based on instructions received from the CPU 210, it outputs various signals to the NAND chip cell 100. During write processing, it transmits write instructions issued by the CPU 210 and write data DAT from the RAM 230 to the NAND chip cell 100 as input / output signals. During read processing, it transmits read instructions issued by the CPU 210 to the NAND chip cell 100 as input / output signals and receives the data DAT read from the NAND chip cell 100 as input / output signals, transmitting it to the RAM 230.

[0090] Based on the structure described above, all NAND chip cells 100 disposed within the memory chip 10 can be controlled in parallel.

[0091] 1.1.4 Structure of NAND Chip Unit

[0092] Next, the structure of the NAND chip cell according to the first embodiment will be described.

[0093] Figure 7 This is a block diagram illustrating the functional structure of the NAND chip cell according to the first embodiment. Figure 7 In, it is shown Figure 6 Details of the connection relationship between one NAND controller chip 200 and one NAND chip unit 100.

[0094] like Figure 7As shown, the NAND chip unit 100 is connected to the NAND controller chip 200 in the probe card 20 via the NAND bus. The NAND bus is a transmission path for transmitting and receiving signals conforming to the NAND interface, and includes probe electrodes 21 and pad electrodes 11.

[0095] Specific examples of signals used in the NAND interface include the chip enable signal CEn, instruction latch enable signal CLE, address latch enable signal ALE, write enable signal WEn, read enable signal REn, ready / busy signal RBn, and input / output (I / O) signals. Furthermore, in the following explanation, when a signal name is appended with "n", it indicates negative logic. That is, the signal represents a signal asserted by a "L" (Low) level.

[0096] The signal CEn is used to enable the NAND chip cell 100 and is activated by the "L" level. Signals CLE and ALE notify the NAND chip cell 100 that the input I / O signals input to it are respectively the instruction CMD and address ADD. The signal WEn is activated by the "L" level and is used to feed the input I / O signals to the NAND chip cell 100. The signal REn is also activated by the "L" level and is used to read the output I / O signals from the NAND chip cell 100. The Ready / Busy signal RBn indicates whether the NAND chip cell 100 is in a ready state (e.g., able to receive instructions from the NAND controller chip 200) or a busy state (e.g., unable to receive instructions from the NAND controller chip 200), with "L" indicating the busy state. The input / output I / O signals are, for example, 8-bit signals. Furthermore, input / output signals (I / O) are the physical entities of data sent and received between the NAND chip cell 100 and the NAND controller chip 200, including instructions (CMD), addresses (ADD), and data (DAT) such as written data and read data.

[0097] Additionally, the NAND chip cell 100 is supplied with voltages VCC and VSS, for example, from the NAND controller chip 200 via the connection between the probe electrode 21 and the pad electrode 11. Voltages VCC and VSS are the power supply voltage and ground voltage in the NAND chip cell 100, respectively.

[0098] The NAND chip unit 100 has a memory cell array 110 and peripheral circuitry 120.

[0099] The memory cell array 110 has multiple block BLKs, each block BLK containing multiple non-volatile memory cells corresponding to rows and columns. A block BLK is, for example, a unit for data deletion. Figure 7As an example, four blocks BLK0 to BLK3 are shown in the diagram. Furthermore, the memory cell array 110 stores data supplied from the NAND controller chip 200.

[0100] The peripheral circuitry 120 includes an I / F circuit 121, an instruction register 126, an address register 127, a data register 128, a driver 129, a row decoder 130, a sense amplifier module 131, and a sequencer 132.

[0101] The I / F circuit 121 is a circuit group inside the NAND chip cell 100 that mainly manages the interface between the pad electrode 11 and other peripheral circuits 120. It includes an input / output circuit 122, a logic control circuit 123, a timing adjustment circuit 124, and an ECC circuit 125.

[0102] Input / output circuit 122 transmits and receives signal I / O with NAND controller chip 200. Upon receiving a signal I / O from NAND controller chip 200, input / output circuit 122 allocates the signal I / O as instruction CMD, address ADD, and data DAT based on information from logic control circuit 123. Input / output circuit 122 transfers instruction CMD to instruction register 126 and address ADD to address register 127. Additionally, input / output circuit 122 transmits and receives write data and read data DAT between itself and data register 128.

[0103] The logic control circuit 123 receives signals CEn, CLE, ALE, WEn, and REn from the NAND controller chip 200, and sends information used to identify the instruction CMD, address ADD, and data DAT within the signal I / O to the input / output circuit 122. Additionally, the logic control circuit 123 forwards signal RBn to the NAND controller chip 200 to notify the NAND controller chip 200 of the status of the NAND chip cell 100.

[0104] The timing adjustment circuit 124, for example, is a latch circuit, located between the pad electrode 11 and the input / output circuit 122 and the logic control circuit 123, to adjust the timing of various signals.

[0105] ECC circuit 125 is, for example, disposed between input / output circuit 122 and instruction register 126, address register 127, and data register 128, to perform error detection and error correction processing related to the data stored in NAND chip cell 100. ECC circuit 125 is configured to have the same structure as ECC circuit 240 and is capable of decoding data encoded by ECC circuit 240. That is, during data writing, the write data DAT after being assigned an error correction code by ECC circuit 240 is decoded, and the presence or absence of error bits is detected. Furthermore, when an error bit is detected, its position is determined, and the error is corrected. Similarly, during data reading, the read data DAT after being assigned an error correction code by ECC circuit 240 is decoded, and the presence or absence of error bits is detected. Furthermore, when an error bit is detected, its position is determined, and after error correction, the read data DAT is re-encoded and sent to NAND controller chip 200.

[0106] Instruction register 126 holds the instruction CMD received from NAND controller chip 200. Address register 127 holds the address ADD received from NAND controller chip 200. This address ADD contains the block address BA and page address PA. Data register 128 holds the write data DAT received from NAND controller chip 200 or the read data DAT received from sense amplifier module 131.

[0107] The driver 129 supplies voltage to the row decoder 130 based on the page address PA in the address register 127 for the selected block BLK.

[0108] The line decoder 130 selects any one of the blocks BLK0 to BLK3 based on the block address BA in the address register 127, and then selects the word line in the selected block BLK.

[0109] When reading data, the sensing amplifier module 131 senses the threshold voltage of the memory cell transistors in the memory cell array 110, thereby reading the data. Furthermore, the read data DAT is output to the NAND controller chip 200 via the data register 128. When writing data, the write data DAT received from the NAND controller chip 200 via the data register 128 is transferred to the memory cell array 110.

[0110] The sequencer 132 controls the overall operation of the NAND chip unit 100 based on the instruction CMD held in the instruction register 126.

[0111] Figure 8This is a perspective view showing an example of the three-dimensional positional relationship of various constituent elements within the aforementioned NAND chip cell 100 in the memory chip 10. Figure 8 The arrangement of the constituent elements of the NAND chip cell 100 along the Z direction is schematically shown in the diagram.

[0112] like Figure 8 As shown, the memory chip 10 includes, for example, a chip LW with peripheral circuitry 120 formed thereon and a chip UW with a memory cell array 110 and a plurality of pad electrodes 11 formed thereon. These two chips, LW and UW, are formed by bonding the side of the chip LW with peripheral circuitry 120 (the side opposite to the exposed side of the chip LW) to the side of the chip UW with memory cell array 110 and a plurality of pad electrodes 11 (the side opposite to the exposed side of the chip UW). Therefore, the NAND chip cell 100 has a structure formed by stacking a peripheral circuitry region PERI corresponding to peripheral circuitry 120, a cell region MCA corresponding to memory cell array 110, and pad regions PdU / PdG corresponding to the plurality of pad electrodes 11 along the Z direction. Furthermore, at the end of the NAND chip cell 100, a pad contact region PdC extending along the Z direction is provided to electrically connect the pad regions PdU / PdG and the peripheral circuitry region PERI. Based on the above structure, any one of the pad groups PdG1 to PdGn can be used to transfer the signal received from the NAND controller chip 200 to the peripheral circuit area PERI via the pad contact area PdC. The peripheral circuit area PERI can then transfer the signal to the cell area MCA based on the transferred signal.

[0113] 1.1.5 Structure of Memory Cell Array

[0114] Next, the structure of the memory cell array 110 described above will be explained.

[0115] Figure 9 This is a circuit diagram of any block BLK of the memory cell array 110.

[0116] like Figure 9 As shown, a block BLK contains, for example, four string units SU (SU0 to SU3). Each string unit SU contains multiple NAND strings NS. The number of blocks within the memory cell array 110 and the number of string units within the block BLK are arbitrary.

[0117] Each NAND string NS contains, for example, eight memory cell transistors MT (MT0 to MT7) and select transistors ST1 and ST2. The memory cell transistors MT have a control gate and a charge storage film to non-volatilely retain data. Furthermore, the memory cell transistors MT are connected in series between the source of select transistor ST1 and the drain of select transistor ST2.

[0118] The gates of the select transistors ST1 in each of the multiple NAND strings NS of each of the string units SU0 to SU3 are respectively connected to select gate lines SGD0 to SGD3. Conversely, the gates of the select transistors ST2 in each of the multiple NAND strings NS of each of the string units SU0 to SU3 are, for example, commonly connected to the select gate line SGS. Alternatively, the gates of the select transistors ST2 in each of the multiple NAND strings NS of each of the string units SU0 to SU3 may be connected to different select gate lines SGS0 to SGS3 for each string unit. Furthermore, the control gates of the memory cell transistors MT0 to MT7 in the multiple NAND strings NS within the same BLK are commonly connected to word lines WL0 to WL7.

[0119] Furthermore, within the memory cell array 110, the drains of the select transistors ST1 of the NAND strings NS in the same column of multiple blocks BLK are commonly connected to the bit line BL (BL0 to BLm, where m is a natural number greater than 2). That is, the bit line BL connects the NAND strings NS in the same column across multiple blocks BLK. Additionally, the sources of multiple select transistors ST2 are commonly connected to the source line SL.

[0120] A string cell (SU) is a collection of NAND strings (NS) connected to different bit lines (BL) and the same select gate line (SGD). A collection of memory cell transistors (MT) within a string cell (SU) that are commonly connected to the same word line (WL) is also called a cell group (CU) (or memory cell group). Furthermore, a block (BLK) is a collection of multiple string cells (SU) shared by the word line (WL). And the memory cell array 110 is a collection of multiple blocks (BLK) shared by the bit line (BL).

[0121] Figure 10 This is a cross-sectional view of a block BLK, showing eight NAND strings NS arranged along the Y direction. Among the eight NAND strings NS, four groups, including two NAND strings NS arranged along the Y direction, correspond to string cells SU0, SU1, SU2, and SU3, respectively. Furthermore, as described above, after the memory cell array 110 is formed on the wafer UW, it is bonded to the wafer LW, thus limiting... Figure 10 The description in the text refers to the area above the paper (in the -Z direction) as "above".

[0122] like Figure 10 As shown, multiple NAND strings NS are formed above the conductor 51, which functions as the source line SL. Specifically, above the conductor 51, there are sequentially stacked conductors 52 (serving as the select gate line SGS), eight layers of conductors 53-60 (serving as word lines WL0-WL7), and conductor 61 (serving as the select gate line SGD). An insulator (not shown) is formed between the stacked conductors. Conductors 52-61 are separated between blocks BLK by an insulator SLT (not shown). Furthermore, conductor 61 is separated between string cells SU by an insulator SHE (not shown). As described above, conductor 61 is shorter than conductors 52-60 in the Y direction.

[0123] Furthermore, a columnar conductor 64 is formed, passing through these conductors 61-52 and reaching conductor 51. A tunnel insulating film 65, a charge storage film 66, and a barrier insulating film 67 are sequentially formed on the side of the conductor 64, through which memory cell transistors MT and select transistors ST1 and ST2 are formed. The conductor 64, for example, contains polysilicon and functions as a current path for the NAND string NS, forming the region where the channels of each transistor are formed. The tunnel insulating film 65 and the barrier insulating film 67, for example, contain silicon oxide (SiO2), and the charge storage film 66, for example, contains silicon nitride (SiN). A conductor 63, functioning as a bit line BL, is provided above the conductor 64. The conductors 64 and 63 are electrically connected, for example, via a conductor 62, functioning as a contact plug. Figure 10 In the example shown, four NAND strings NS, which correspond one-to-one with each of the string units SU0 to SU3, are electrically connected to a conductor 63 in an arrangement of eight NAND strings NS along the Y direction.

[0124] The above structure is arranged in multiple ways in the X direction, forming a block BLK by collecting multiple NAND strings NS arranged in the X direction. Moreover, multiple blocks BLK are arranged in the Y direction, thereby forming a memory cell array 110.

[0125] 1.1.6 Cross-sectional structure of memory chip and probe card

[0126] Next, the cross-sectional structure of the memory chip and probe card according to the first embodiment will be described.

[0127] Structure corresponding to the pad group in 1.1.6.1

[0128] Figure 11 It is along Figure 5 The cross-sectional view along line XI-XI shows an example of a structure corresponding to the pad group according to the first embodiment. Figure 11In addition to the XZ cross-section of the memory chip 10 cut along the pad group PdGn, an XZ cross-section of the probe card 20 with multiple probe electrodes 21 in contact with the pad group PdGn is also shown. Furthermore, in Figure 11 The image shows a cross-section of the probe electrode 21 before it contacts the pad electrode 11 after alignment is completed in the XY plane between the memory chip 10 and the probe card 20.

[0129] First, the cross-sectional structure of the memory chip 10 will be described.

[0130] like Figure 11 As shown, in the chip LW, a peripheral circuit PERI is disposed on the semiconductor substrate 70. Figure 11 (A transistor is illustrated as an example). A conductor 71 is disposed above the peripheral circuit PERI. The conductor 71 is electrically connected to the peripheral circuit PERI via a conductor (not shown). A conductor 72, which functions as a contact portion, is disposed on the upper surface of the conductor 71. A conductor 73 is disposed on the upper surface of the conductor 72. The upper surface of the conductor 73 reaches the bonding surface with the wafer UW (i.e., the upper surface of the wafer LW) and serves as a pad electrode when bonding with the wafer UW. For example, one group of conductors 71 to 73 is disposed corresponding to each of the plurality of pad electrodes 11 in the pad group PdG. Moreover, these plurality of groups of conductors 71 to 73 are electrically insulated from each other by an insulator INS_L.

[0131] The portion of the memory chip 10 above the conductor 73 corresponds to the chip UW. A conductor 74 is provided on the upper surface of the conductor 73 as a pad electrode when bonded to the chip LW. A conductor 75, functioning as a contact portion, is provided on the upper surface of the conductor 74. A conductor 76, functioning as wiring 15 electrically connecting multiple pad electrodes 11_1 to 11_n within the pad unit PdU, is provided on the upper surface of the conductor 75. As described later, the conductor 76 extends, for example, along the Y direction. A conductor 77, functioning as a contact portion electrically connecting the wiring 15 to the pad electrode 11, is provided on the upper surface of the conductor 76. Each group of conductors 74 to 77 corresponds to each of the multiple pad electrodes 11 within the pad group PdG, and one group is provided for each group. Furthermore, these multiple groups of conductors 74 to 77 are electrically insulated from each other by an insulator INS_U.

[0132] A conductor 78, which functions as part of a pad electrode 11, is disposed on the upper surface of the conductor 77. The conductor 78 may contain, for example, aluminum (Al). A conductor 79, which functions as part of the pad electrode 11 and has a contact surface with the probe electrode 21 on the upper surface of the memory chip 10, is disposed on the upper surface of the conductor 78. The conductor 79 may be, for example, a dissimilar metal relative to the conductor 78 grown on the conductor 78 by an electroless electroplating growth method, including at least one metal selected from nickel (Ni), gold (Au), cobalt (Co), palladium (Pd), copper (Cu), and silver (Ag). The conductor 79 may be, for example, harder than the conductor 78 and less prone to damage due to contact with the probe electrode 21. A group of multiple conductors 78 and 79 arranged along the X direction constitutes a pad group PdG (in Figure 11 In the example, the pad group (PdGn) is electrically disconnected from each other by the insulator PI. The upper surfaces of the multiple conductors 79 are located, for example, below (in the -Z direction) the upper surface of the insulator PI.

[0133] Next, the cross-sectional structure of probe card 20 will be described.

[0134] The probe cards 20 all have an insulating base, including a printed circuit board (PCB), an insert (IP), and a probe unit (PBU). The probe unit PBU includes, for example, multiple layers L1, L2, and L3 stacked sequentially along the Z-direction from the insert IP side. The probe electrodes 21 include, for example, a plate-shaped conductor 98 and a probe pin 99.

[0135] A NAND controller chip 200 is mounted on the upper surface of a printed circuit board (PCB), and an insert IP is disposed on the lower surface with a conductor 91 in between. Layer L1 is disposed on the lower surface of the insert IP. Layer L2 is disposed on the lower surface of layer L1 with a conductor 94 in between, and layer L3 is disposed on the lower surface of layer L2 with a conductor 96 in between. A conductor 98 is disposed on the lower surface of layer L3. A probe pin 99 is disposed on the lower surface of the conductor 98. The probe pin 99 is, for example, a cantilever supported on one side by the conductor 98, and its front end on the pad electrode 11 side is formed into a convex needle shape. This suppresses interference between the probe pin 99 and the periphery of the pad electrode 11, and allows the probe electrode 21 to contact the pad electrode 11.

[0136] In addition, conductors 90, 92, 93, 95, and 97, extending along the Z-direction, are respectively disposed inside the printed circuit board (PCB), the insert (IP), and layers L1 to L3. Conductor 90 electrically connects the NAND controller chip 200 to conductor 91. Conductors 92 and 93 electrically connect conductor 91 to conductor 94. Conductor 95 electrically connects conductor 94 to conductor 96. Conductor 97 electrically connects conductor 96 to conductor 98.

[0137] In the structure described above, by properly wiring the conductors 91, 94 and 96, various signals output from the NAND controller chip 200 can be transferred to the desired probe pins 99.

[0138] Moreover, such as Figure 11 As shown, each of the multiple probe electrodes 21 is arranged in the XY plane at a position that can contact the corresponding pad electrode 11 in the pad group PdGn.

[0139] 1.1.6.2 Structure corresponding to pad units and alignment marks

[0140] Figure 12 It is along Figure 5 The cross-sectional view along line XII-XII shows an example of the structure corresponding to the pad cells and alignment marks according to the first embodiment. Figure 12 In addition to the YZ cross-section of the memory chip 10 cut along the pad unit PdU and alignment mark 12, the YZ cross-section of the probe card 20 with the probe electrode 21 in contact with the pad electrode 11_1 in the pad unit PdU is also shown. Furthermore, Figure 12 In, with Figure 11 Similarly, a cross-section is shown in the state before the probe electrode 21 contacts the pad electrode 11 after alignment is completed in the XY plane between the memory chip 10 and the probe card 20.

[0141] First, the cross-sectional structure of the memory chip 10 will be described.

[0142] Regarding the structure of the LW wafer, due to... Figure 11 Equal, therefore the explanation is omitted.

[0143] like Figure 12 As shown, in the wafer UW, a memory cell array MCA is disposed between the boundary between the wafer LW and the wafer UW and the conductor 76. The memory cell array MCA is electrically connected to the peripheral circuit PERI through a conductor (not shown).

[0144] As described above, the conductor 76 extends along the Y direction. More specifically, for example, the length of the conductor 76 along the Y direction is greater than or equal to the distance between the pad electrodes 11_1 and 11_n at both ends of the pad unit PdU.

[0145] A plurality of conductors 78 arranged along the Y direction are provided between the conductor 76 and the pad unit PdU. Furthermore, a plurality of pad electrodes 11_1 to 11_n within the pad unit PdU are connected together to the conductor 76. Thus, the plurality of pad electrodes 11 within the pad unit PdU can function as electrically equivalent pad electrodes.

[0146] Alignment mark 12 is formed, for example, on the upper surface of insulator INS_U with a structure equivalent to pad electrode 11. More specifically, a conductor 80 is provided on the upper surface of insulator INS_U. Conductor 80 comprises, for example, aluminum (Al). A conductor 81 having a surface exposed on the upper surface of memory wafer 10 is provided on the upper surface of conductor 80. Conductor 81 is a dissimilar metal relative to conductor 80 grown on conductor 80 by electroless electroplating, for example, comprising at least one metal selected from nickel (Ni), gold (Au), cobalt (Co), palladium (Pd), copper (Cu), and silver (Ag). The upper surface of conductor 81 is located, for example, below (in the -Z direction) the upper surface of insulator PI. Conductors 80 and 81 are electrically disconnected from other conductors provided on memory wafer 10 by insulator PI.

[0147] Next, the cross-sectional structure of probe card 20 will be described.

[0148] A summary of the structure of probe card 20 is as follows: Figure 11 As explained in the text, but... Figure 12 In this diagram, the number of probe electrodes 21 differs from the number of pad electrodes 11 shown. More specifically, probe electrodes 21 are assigned to any one of the plurality of pad electrodes 11 within the pad unit PdU. That is, the probe electrodes 21 are configured such that only one probe electrode 21 is assigned relative to the electrically equivalent plurality of pad electrodes 11.

[0149] Furthermore, the process of determining whether to make probe electrode 21 contact a certain pad electrode 11 within the pad unit PdU is performed by interface control system 33, for example, based on probe management table 335.

[0150] 1.1.7 Probe Management Table

[0151] Figure 13 This is a conceptual diagram illustrating the probe management table according to the first embodiment. The probe management table 335 can, for example, be non-volatilely maintained in the host device 2. In this case, the probe management table 335 can be transferred from the host device 2 simultaneously with the startup of the storage system 1 and stored in the RAM 334 within the interface control system 33. Alternatively, the probe management table 335 can also be stored in the storage chip 10 in response to events such as updates.

[0152] like Figure 13 As shown, Probe Management Table 335 is information that establishes a correlation between the number of probes and defective flags for each category.

[0153] Categories include, for example, the “chip or card” category that identifies the memory chip 10 and the probe card 20, and the “pad group” category that identifies the pad group PdG within the memory chip 10.

[0154] The "Chip or Card" project is categorized into "Memory Chip" and "Probe Card" projects. The "Memory Chip" project will store multiple memory chips 10 (in...) within the chip storage device 5. Figure 13 Each of the following is uniquely identified: W1, W2, ... . The "Probe Card" item identifies probe card 20 (i.e., probe electrode 21). The "Pad Group" item is associated with the "Memory Wafer" item, uniquely identifying the pad group PdG (PdG1, PdG2, PdG3, ..., PdGn) within the memory wafer 10.

[0155] The probe count indicates the number of times the contact process (landing process) of the probe electrode 21 relative to the pad electrode 11 was performed using the pad group PdG or probe electrode 21 in the memory chip 10, which is determined by the corresponding category. Figure 13 In the example, it is shown that 10, 8, 3, ..., 0 landing processes were performed on the pad groups PdG1, PdG2, PdG3, ..., PdGn of the memory chip W1, respectively, and 9, 1, 0, ..., 0 landing processes were performed on the pad groups PdG1, PdG2, PdG3, ..., PdGn of the memory chip W2, respectively. Additionally, it is shown that the probe electrode 21 was used in a total of 31 landing processes.

[0156] The defect flag indicates whether the pad group PdG in the memory chip 10 is defective, as determined by the corresponding category (i.e., the pad group PdG is unusable during landing processing). Figure 13 The example shows a scenario where pad groups PdG1 and PdG2 of memory chip W1 are defective ("True"), while other pad groups PdG3 to PdGn are good ("False"). Similarly, the example shows a scenario where pad group PdG1 of memory chip W2 is defective ("True"), while other pad groups PdG2 to PdGn are good ("False").

[0157] By referring to the probe management table 335 described above, it can be determined which pad group PdG each memory chip 10 should use for landing processing.

[0158] 1.2 Actions

[0159] Next, the operation of the storage system according to the first embodiment will be described.

[0160] 1.2.1 Basic Processing Accompanying Data Communication

[0161] Figure 14 This is a flowchart illustrating the basic processes performed during data communication in the storage system according to the first embodiment.

[0162] like Figure 14 As shown, in step ST10, if a read request, write request, or other data request is received from the host device 2, the detector 3 performs a wafer and pad group selection process. The wafer and pad group selection process includes selecting the memory wafer 10 disposed within the detector 3 and the pad group PdG in the memory wafer 10 that is in contact with the probe electrode 21.

[0163] In step ST20, the wafer conveyor 4 performs a wafer transport process that transports the storage wafer 10 selected in step ST10 from the wafer storage device 5 to the detector 3.

[0164] In step ST30, the detector 3 performs an alignment process to align the pad electrodes 11 on the memory wafer 10 selected in step ST10 with the probe electrodes 21 on the probe card 20. For example, the detector 3 uses alignment marks 12 or the like provided on the memory wafer 10 to eliminate the offset in the XY plane between the memory wafer 10 and the probe card 20.

[0165] In step ST40, the detector 3 performs a landing process, that is, it moves the memory chip 10, which was positioned opposite the probe card 20 in step ST30, in the Z direction, and brings the probe electrode 21 into contact with the pad group PdG selected in step ST10. Through the landing process, the NAND controller chip 200 on the detector 3 is electrically connected to the NAND chip cell 100 within the memory chip 10.

[0166] In step ST50, the NAND controller chip 200 and the NAND chip unit 100 perform data communication processing based on the request from the host device 2.

[0167] That concludes the basic processing.

[0168] 1.2.2 Chip and Pad Group Selection Process

[0169] Next, use Figure 15 The flowchart shown illustrates the details of the chip and pad group selection process. Figure 15 Steps ST11 to ST19 in the text represent Figure 14 Here is an example of the details of step ST10.

[0170] like Figure 15 As shown, in step ST11, detector 3 selects the memory chip 10 to be accessed based on a request from host device 2. In the following description, the memory chip 10 selected in step ST11 will also be referred to as "selected memory chip 10".

[0171] In step ST12, detector 3 initializes variable i to "1" (1≤i≤n).

[0172] In step ST13, detector 3 refers to probe management table 335 to determine whether the defect flag corresponding to the pad group PdGi of the selected memory chip 10 is "False". If the corresponding defect flag is not "False" (step ST13; No), detector 3 determines that the pad group PdGi is unusable, and the process proceeds to step ST14. If the corresponding defect flag is "False" (step ST13; Yes), detector 3 determines that the pad group PdGi is usable, and the process proceeds to step ST15.

[0173] In step ST14, detector 3 increments variable i and returns the process to step ST13. Thus, steps ST13 and ST14 are repeated until it is determined that the pad group PdGi is usable.

[0174] In step ST15, the detector 3 selects the pad group PdGi as the pad group PdG that is in contact with the probe electrode 21.

[0175] In step ST16, detector 3, for example, confirms whether the selected memory chip 10 has made contact with probe card 20. If the selected memory chip 10 has not made contact with probe card 20 (step ST16; No), the process proceeds to step ST17; if the selected memory chip 10 has made contact with probe card 20 (step ST16; Yes), the process proceeds to step ST18.

[0176] In step ST17, detector 3 refers to probe management table 335 and increments the number of probes corresponding to the pad group PdGi selected in step ST15.

[0177] In step ST18, detector 3 refers to probe management table 335 to determine whether the number of probes corresponding to the pad group PdGi selected in step ST15 is greater than or equal to the threshold Th1. If the number of probes is greater than or equal to the threshold Th1 (step ST18; Yes), the process proceeds to step ST19. If the number of probes is less than the threshold Th1 (step ST18; No), step ST19 is omitted.

[0178] In step ST19, the detector 3 refers to the probe management table 335, and after updating the defect flag corresponding to the pad group PdGi selected in step ST15 to "True", it replaces the pad group PdGi and reselects the pad group PdG(i+1).

[0179] The chip and pad group selection process is now complete. Furthermore, in the following explanation, the pad group PdG selected after the chip and pad group selection process will also be referred to as the "selected pad group PdG".

[0180] 1.2.3 Wafer Delivery Processing

[0181] Next, use Figure 16 The flowchart shown illustrates the details of the wafer transport process. Figure 16 Steps ST21 to ST26 in the text represent Figure 14 Here is an example of the details of step ST20.

[0182] like Figure 16 As shown, in step ST21, detector 3 refers to probe management table 335 to determine whether the number of probes corresponding to probe card 20 is greater than or equal to threshold Th2. As mentioned above, the number of probes corresponding to probe card 20 refers to the total number of landing processes using probe card 20 (total number of probes), therefore threshold Th2 can be set to a value greater than threshold Th1. If the total number of probes is greater than or equal to threshold Th2 (step ST21; Yes), detector 3 determines that cleaning processing of probe electrode 21 is required, and the process proceeds to step ST22. If the total number of probes is less than threshold Th2 (step ST21; No), detector 3 determines that cleaning processing is not required, and the process proceeds to step ST25.

[0183] In step ST22, the wafer conveyor 4 transports the cleaned wafer 10c from the wafer storage container 5 to the detector 3.

[0184] In step ST23, the detector 3 brings the probe electrode 21 into contact with the cleaning wafer 10c to perform a cleaning process. The drive control system 32 drives, for example, the stage 32-1 and stage 32-2, thereby displacing the cleaning wafer 10c relative to the probe electrode 21 in the XY plane. As a result, the tip of the probe electrode 21 can be polished, and contaminants such as metal from the pad electrodes 11 attached to the tip of the probe electrode 21 can be removed, thereby improving the electrical characteristics of the probe electrode 21.

[0185] In step ST24, detector 3 resets the number of probes corresponding to probe card 20 in probe management table 335 to "0".

[0186] In step ST25, detector 3 determines whether the selected memory chip 10 has made contact with probe card 20. If the selected memory chip 10 has not made contact with probe card 20 (step ST25; No), the process proceeds to step ST26. If the selected memory chip 10 has made contact with probe card 20 (step ST25; Yes), step ST26 is omitted.

[0187] In step ST26, the wafer conveyor 4 will select and store the wafer 10 from the wafer storage container 5 to the detector 3.

[0188] The wafer delivery process is now complete.

[0189] 1.2.4 Data Communication Processing

[0190] Next, we will explain the details of data communication processing.

[0191] 1.2.4.1 Write Processing

[0192] First, as an example of data communication processing, using Figure 17 The flowchart shown illustrates the write process. Figure 17 The diagram illustrates an example of the flow of alignment and landing processes performed after the wafer delivery process, and the write process after the detector 3 is electrically connected to the memory wafer 10.

[0193] like Figure 17 As shown, in step ST41, the NAND controller chip 200 in detector 3 issues a write command CMD based on a write request from the host device 2. Furthermore, the NAND controller chip 200 sends a write command set, including the write command CMD, address ADD, and write data DAT, to the NAND chip cell 100. The processing of detector 3 proceeds to step ST44.

[0194] In step ST42, if a write instruction set is received, the ECC circuit 125 within the NAND chip cell 100 performs error detection and correction processing for the write data DAT. If the write data DAT does not contain errors, or if errors can be corrected by the ECC circuit 125 (step ST42; yes), the process proceeds to step ST46. In step ST46, the NAND chip cell 100 performs the write process to store data in the memory cell array 110, and the processing of the NAND chip cell 100 ends.

[0195] On the other hand, if the number of erroneous bits contained in the written data DAT exceeds the number of bits that can be corrected by the ECC circuit 125, and the error cannot be corrected by the ECC circuit 125 (step ST42; no), the process proceeds to step ST43.

[0196] Furthermore, the error detection and correction processing performed by the ECC circuit 125 is based on the error correction code assigned in the ECC circuit 240 within the NAND controller chip 200. Additionally, while the example described above focuses on error detection and correction processing for write data DAT, it is not a limitation; error detection and correction processing can also be performed for write instructions CMD and addresses ADD. Furthermore, as preprocessing for step ST42, the timing adjustment circuit 124 can adjust the timing deviations generated in the various signals input to the NAND chip cell 100, thereby achieving synchronization of the various signals.

[0197] In step ST43, the NAND chip cell 100 determines that the error correction failure of the ECC circuit 125 is caused by a faulty pad electrode 11, and issues a pad fault notification. Furthermore, the pad fault notification is sent to the NAND controller chip 200.

[0198] In step ST44, the NAND controller chip 200 determines whether a pad defect notification has been received. If a pad defect notification has been received (step ST44; Yes), the process proceeds to step ST45. If no pad defect notification has been received (step ST44; No), the processing of detector 3 ends.

[0199] In step ST45, the interface control system 33 refers to the probe management table 335, updates the defect flag corresponding to the selected pad group PdGi to "True", and selects pad group PdG(i+1) as the new selected pad group PdG. Then, the process returns to the alignment process (ST30).

[0200] Figure 18 and Figure 19 This is a cross-sectional view showing the probe card and NAND chip unit after landing processing in the storage system according to the first embodiment. Specifically, Figure 18 Shown in Figure 17 The state shown is the alignment and landing process performed on the selected pad group PdG1 before the write process. Figure 19 Shown in Figure 17 The state during alignment and landing processes after replacing pad group PdG1 with new pad group PdG2 in step ST45 of the write process shown.

[0201] like Figure 18As shown, when the pad group PdG1 is selected as the selection pad group before the execution of the write process, the detector 3 performs alignment and landing processes by contacting the pad group PdG1 with the probe electrode 21. Moreover, the write instruction set, etc., is sent from the NAND controller chip 200 to the NAND chip cell 100 via the pad group PdG1.

[0202] If the signal received via pad group PdG1 cannot be corrected by the ECC circuit 125, it is suspected that pad group PdG1 is damaged due to repeated landing processes, resulting in degraded electrical characteristics. Therefore, the NAND chip cell 100 sends a pad defect notification to the NAND controller chip 200. Corresponding to the NAND controller chip 200 receiving the pad defect notification, regardless of whether the number of probes in pad group PdG1 reaches the threshold Th1, the detector 3 determines that pad group PdG1 is unusable. The detector 3 replaces the unusable pad group PdG1 and selects a new unused pad group PdG2 whose probe count has not reached the threshold Th1.

[0203] Next, as Figure 19 As shown, the detector 3 performs landing processing by contacting the probe electrode 21 with the pad group PdG2. Furthermore, the write instruction set, etc., is sent from the NAND controller chip 200 to the NAND chip cell 100 again via the pad group PdG2.

[0204] By performing the above actions, it is possible to appropriately select the pad group PdG that can communicate well and write the desired data to the NAND chip cell 100.

[0205] Furthermore, it is preferable to select pad groups PdG in order of increasing distance from the conductor 75 that connects the pad area to the surrounding circuit area. Specifically, for example, Figure 18 and Figure 19 As shown, after pad group PdG1 is selected, pad group PdG2, which is closer to conductor 75 than pad group PdG1, is preferably selected. This suppresses the presence of defective pad electrodes in the conductive path between probe electrode 21 and conductor 75. Therefore, it is possible to prevent communication between NAND controller chip 200 and NAND chip cell 100 from being hindered by defective pad electrodes.

[0206] 1.2.4.2 Read Processing

[0207] Next, as an example of further data communication processing, we will use... Figure 20 The flowchart shown illustrates the readout processing. Figure 20 In, with Figure 17Similarly, an example of the readout process is shown after the wafer delivery process, which includes alignment and landing processes and electrical connection of the detector 3 to the memory wafer 10.

[0208] like Figure 20 As shown, in step ST51, the NAND controller chip 200 within the detector 3 issues a read instruction CMD based on a read request from the host device 2. Furthermore, the NAND controller chip 200 sends a read instruction set, including the read instruction CMD and the address ADD, to the NAND chip cell 100. The processing of the detector 3 then proceeds to step ST55.

[0209] In step ST52, if a read instruction set is received, the NAND chip cell 100 reads the data DAT corresponding to the specified address ADD from the memory cell array 110 and stores it in the data register 128. Furthermore, when the read instruction set is received, the timing deviation generated in various signals input to the NAND chip cell 100 can be adjusted by the timing adjustment circuit 124 to achieve synchronization of various signals.

[0210] In step ST53, the ECC circuit 125 performs error detection and correction processing on the read data DAT stored in the data register 128. If the read data DAT does not contain any errors, or if errors can be corrected by the ECC circuit 125 (step ST53; Yes), the NAND chip unit 100 sends the read data DAT to the NAND controller chip 200 via the input / output circuit 122, and the processing of the NAND chip unit 100 ends.

[0211] On the other hand, if the error correction based on the ECC circuit 125 cannot be performed on the read data DAT (step ST53; no), the process proceeds to step ST54. In step ST54, the NAND chip cell 100 attempts to re-execute the read process (retry process) by, for example, changing the conditions of the read process, until the number of error bits contained in the read data DAT is reduced to a level that can be corrected by the ECC circuit 125. If the error detection and correction processing of the read data DAT read through the retry process is successful, the error-detected and corrected read data DAT is sent to the NAND controller chip 200.

[0212] In step ST55, if the ECC circuit 240 within the NAND controller chip 200 receives read data DAT, it performs error detection and correction processing for the read data DAT. If the read data DAT does not contain any errors, or if errors can be corrected by the ECC circuit 125 (step ST55; Yes), the read data DAT is sent to the host device 2, and the processing of the NAND chip unit 100 ends.

[0213] On the other hand, if the error regarding the readout data DAT cannot be corrected based on the ECC circuit 125 (step ST55; no), the process proceeds to step ST56. In step ST56, the detector 3 refers to the probe management table 335, updates the defect flag corresponding to the selected pad group PdGi to "True", and selects pad group PdG(i+1) as the new selected pad group PdG. Then, the process returns to the alignment process (ST30).

[0214] By performing the actions described above, it is possible to appropriately select the pad group PdG that can communicate well and read the desired data from the NAND chip cell 100.

[0215] 1.3 Effects of this implementation method

[0216] According to the first embodiment, it is possible to suppress the degradation of communication reliability between the probe electrode and the pad electrode. This effect will be explained below.

[0217] The NAND chip cell 100 includes multiple pad cells PdU, and each pad cell PdU includes multiple pad electrodes 11_1 to 11_n belonging to different pad groups PdG1 to PdGn. Therefore, even if data communication processing based on a selected pad group PdGi becomes impossible, data communication processing can be performed using a new selected pad group PdG(i+1). Thus, compared to assigning one pad electrode 11 to one signal, the number of times landing processing can be executed increases. Therefore, the degradation of electrical characteristics between the pad electrodes and probe electrodes can be suppressed.

[0218] Furthermore, the interface control system 33 stores information related to the number of landing processes performed on which pad group PdG of which memory chip 10, and information on whether the pad group PdG can be used, as a probe management table 335. Thus, the interface control system 33 can determine whether the selected pad group PdGi can be used for landing processing, or whether a new selected pad group PdG(i+1) should be used for landing processing, based on whether the number of probes corresponding to a selected pad group PdGi of a selected memory chip 10 exceeds a threshold Th1. Therefore, before the pad group PdG becomes unusable due to multiple landing processes, a pad group PdG(i+1) with good electrical characteristics (that has not undergone landing processing) can be selected, thus suppressing the degradation of the response performance of the memory system 1.

[0219] Furthermore, the pad electrode 11 includes: a conductor 78 comprising aluminum (Al); and a conductor 79 comprising a dissimilar metal of aluminum (Al) disposed on the upper surface of the conductor 78. Therefore, compared to pad electrodes typically used as bonding pads in NAND chips, a harder dissimilar metal can be brought into contact with the probe electrode 21. This increases the upper limit (threshold Th1) of the number of landing processes that can be performed on each pad electrode 11.

[0220] Furthermore, the memory chip 10 is formed by bonding a chip LW and a chip UW. More specifically, a chip UW, on which a memory cell array (MCA) is provided, is bonded to the upper surface of the chip LW, which has a peripheral circuitry (PERI). By bonding the chip LW and the chip UW, the peripheral circuitry (PERI) and the memory cell array (MCA) provided on different chips can be stacked along the Z-direction, ensuring sufficient area for either the memory cell array (MCA) or the peripheral circuitry (PERI). Therefore, an ECC circuit 125 can be provided in the peripheral circuitry (PERI), and data encoded on the detector 3 side can be decoded on the memory chip 10 side. Thus, error detection and correction processing of data caused by poor communication between the probe electrode 21 and the pad electrode 11 can be performed, and it can be determined whether the pad electrode 11 is unusable.

[0221] 1.4 Variations

[0222] Furthermore, the first embodiment described above can be modified in various ways. In the various modifications shown below, descriptions of structures and operations that are identical to those of the first embodiment are omitted, and descriptions will mainly focus on structures and operations that differ from those of the first embodiment.

[0223] 1.4.1 First Variation

[0224] In the first embodiment described above, the case where a plurality of pad electrodes 11 corresponding to one NAND chip cell 100 are arranged in the area surrounded by the dicing line 13 and the edge sealing portion 14 has been described, but it is not limited to this. For example, a portion of the plurality of pad electrodes 11 corresponding to one NAND chip cell 100 may also be arranged outside the area surrounded by the dicing line 13 and the edge sealing portion 14.

[0225] Figure 21 This is a top view of the memory chip according to the first variation of the first embodiment, and is different from that in the first embodiment. Figure 5 Correspondingly.

[0226] like Figure 21 As shown, each of the multiple pad units PdU includes: n pad electrodes 11_1 to 11_n arranged within a region surrounded by the cut line 13 and the edge sealing portion 14, and pad electrodes 11_0 arranged outside the region surrounded by the cut line 13 or the edge sealing portion 14. The pad electrodes 11_0 to 11_n within the same pad unit PdU are connected together by wiring 15. Furthermore, the pad electrodes 11_0 can be arranged beyond the cut line 13 and the edge sealing portion 14 corresponding to the adjacent NAND chip units 100, as long as they do not interfere with the pad electrodes 11 and wiring 15 corresponding to the adjacent NAND chip units 100.

[0227] As described above, in this embodiment, the cutting process is not performed along the cutting line 13, so the pad electrode 11_0 configured beyond the cutting line 13 can be used equally with the other pad electrodes 11_1 to 11_n. This increases the number of pad electrodes 11 that can be used per NAND chip cell 100. Therefore, the upper limit of the landing process that can be performed on the memory chip 10 can be increased. Consequently, the degradation of communication reliability between the probe electrode and the pad electrode can be suppressed, thereby extending the lifespan of the memory chip 10.

[0228] 1.4.2 Second Variation

[0229] In the first embodiment and the first variation thereof described above, the case in which the plurality of pad electrodes 11 in a single pad unit PdU are arranged parallel to the Y direction has been described. However, the plurality of pad electrodes 11 in a single pad unit PdU may also be arranged not parallel to the Y direction.

[0230] Figure 22 This is a top view of the memory chip involved in the second variation of the first embodiment. Figure 22 Compared with the first embodiment Figure 5 Correspondingly.

[0231] like Figure 22 As shown, the pad electrode 11_i belonging to pad group PdGi and the pad electrodes 11_(i+1) and 11_(i-1) belonging to pad groups PdG(i+1) and PdG(i-1) can be arranged in a direction intersecting the Y direction (0 < i < n). Therefore, compared to arranging multiple pad electrodes 11 within a single pad unit PdU parallel to the Y direction, the distance between pad electrode 11_i and pad electrodes 11_(i+1) and 11_(i-1) can be increased. Thus, the alignment load between the probe electrode 21 and the pad electrode 11 during the alignment process can be reduced.

[0232] 1.4.3 Third Variation

[0233] In the first embodiment and its first and second modifications described above, the case where the plurality of pad electrodes 11 in a pad group PdG are arranged parallel to the X direction was explained. However, the plurality of pad electrodes 11 in a pad group PdG may also be arranged not parallel to the X direction.

[0234] Figure 23 This is a top view of the memory chip involved in the third variation of the first embodiment. Figure 23 Compared with the first embodiment Figure 5 Correspondingly.

[0235] like Figure 23 As shown, multiple pad electrodes 11_1 to 11_n belonging to a certain pad unit PdU can be arranged in a direction intersecting the X direction with multiple pad electrodes 11_1 to 11_n belonging to adjacent pad units PdU. Therefore, compared to arranging multiple pad electrodes 11 within a single pad group PdG parallel to the X direction, the distance between the pad electrodes 11 within the pad group PdG can be increased. Thus, the alignment load between the probe electrode 21 and the pad electrode 11 during the alignment process can be reduced.

[0236] Furthermore, in the first to third modifications of the first embodiment described above, all pad groups PdG1 to PdGn in all NAND chip cells 100 have the same configuration pattern. That is, the relative positional relationship between the pad electrode 11 belonging to a certain pad group PdG and the corresponding pad electrode 11 belonging to other pad groups PdG does not change depending on the pad cell PdU to which these two pad electrodes 11 are attached. In other words, the quadrilateral formed by the two pad electrodes 11 belonging to a certain pad group PdG and the two pad electrodes 11 corresponding to those two pad electrodes 11 in other pad groups PdG becomes a parallelogram. As a result, any pad group PdG can be selected without changing the configuration of the probe electrode 21.

[0237] 1.4.4 Fourth Variation

[0238] Furthermore, in the first embodiment and the first to third modifications of the first embodiment described above, it was explained that the upper surface of the conductor 79, which is provided as the part of the pad electrode 11 that contacts the probe electrode 21, is located below the upper surface of the insulator PI. However, it is not limited to this and may be located above the upper surface of the insulator PI.

[0239] Figure 24 This is a cross-sectional view showing an example of the structure corresponding to the pad cells and alignment marks involved in the fourth variation of the first embodiment, compared with the first embodiment. Figure 12 Correspondingly.

[0240] like Figure 24 As shown, a conductor 79A is provided on the upper surface of the conductor 78, functioning as part of the pad electrode 11, and having a contact surface with the probe electrode 21 on the upper surface of the memory chip 10. The conductor 79A is, for example, a dissimilar metal grown on the conductor 78 using an electroless electroplating method, including at least one metal selected from nickel (Ni), gold (Au), cobalt (Co), palladium (Pd), copper (Cu), and silver (Ag). A group of multiple conductors 78 and 79A arranged along the X direction constitutes a pad group PdU, which is connected to the conductor 76 via conductors 77 corresponding to each group. The upper surface of the conductor 79A is, for example, located above the upper surface of the insulator PI (in the +Z direction), and has a larger area than the upper surface of the conductor 78. Furthermore, the conductor 79A has a portion above the insulator PI that contacts the upper surface of the insulator PI. That is, the conductor 79A has a convex structure that includes a portion that protrudes upward relative to the insulator PI.

[0241] Additionally, alignment mark 12 includes conductor 80 and conductor 81A disposed on the upper surface of conductor 80. Like conductor 79A, conductor 81A has an upper surface located above (in the +Z direction) the upper surface of insulator PI, and the upper surface of conductor 81A has a larger area than the upper surface of conductor 78. Furthermore, conductor 81A has a portion above insulator PI that contacts the upper surface of insulator PI. That is, conductor 81A has a convex structure that includes a portion protruding upward relative to insulator PI.

[0242] With the above configuration, the area of ​​the upper surface of the pad electrode 11 that can contact the probe electrode 21 can be increased. This relaxes the alignment accuracy requirements between the probe electrode 21 and the pad electrode 11 during landing processing. Furthermore, by making the pad electrode 11 and the alignment mark 12 have the same structure, they can be installed in the same manufacturing process. Therefore, the increase in manufacturing load on the memory wafer 10 can be suppressed. However, making the pad electrode 11 and the alignment mark 12 have the same structure is not necessarily required; the materials of the pad electrode 11 and the alignment mark 12 can be changed depending on their size, shape, and other factors.

[0243] 1.4.5 Fifth Variation

[0244] Furthermore, in the first embodiment and the first to fourth modifications of the first embodiment described above, the case where a probe pin 99 is provided as the portion of the probe electrode 21 that contacts the pad electrode 11 was explained, but it is not limited to this. For example, the probe electrode 21 may also contact the pad electrode 11 through a plate-shaped electrode.

[0245] Figure 25 This is a cross-sectional view showing an example of the structure corresponding to the pad cells and alignment marks in the fifth modification of the first embodiment, and is consistent with the fourth modification of the first embodiment. Figure 24 Correspondingly.

[0246] like Figure 25 As shown, the probe electrode 21 includes a plate-shaped conductor 98, but may not include a probe pin 99.

[0247] As described in the fourth variation of the first embodiment, when the pad electrode 11 protrudes upward relative to the insulator PI, the limitation on interference between the probe electrode 21 and the insulator PI when in contact with the pad electrode 11 is relaxed. This allows for a wider contact area of ​​the probe electrode 21 relative to the pad electrode 11. Therefore, the contact portion of the probe electrode 21 relative to the pad electrode 11 can be changed from a cantilevered probe pin 99 to a flat conductor 98. This simplifies the structure of the probe electrode 21 and reduces the increase in design load on the probe card 20.

[0248] 2. Second Implementation Method

[0249] Next, the storage system according to the second embodiment will be described.

[0250] In the first embodiment, the redundancy of conductors 78 and 79 used as bonding pads when the memory wafer 10 is diced and multiple NAND chip cells 100 are separated for use was described. In the second embodiment, the difference from the first embodiment is that a redistribution layer is provided above one conductor 78 located directly above the pad contact portion PdC, and this redistribution layer functions as the multiple redundant pad electrodes 11. In the following description, descriptions of structures and operations identical to those in the first embodiment are omitted; the descriptions mainly focus on structures and operations different from those in the first embodiment.

[0251] 2.1 Structure corresponding to pad units and alignment marks

[0252] Figure 26 This is an example of a structure corresponding to the pad unit and alignment mark involved in the second embodiment, and the first embodiment. Figure 12 Correspondingly.

[0253] like Figure 26 As shown, a conductor 75A, which functions as a contact portion, is provided on the upper surface of the conductor 74. A conductor 78, for example, comprising aluminum (Al), is provided on the upper surface of the conductor 75A. As described above, the conductor 78 is a bonding pad that bonds to bonding wires when the NAND chip cell 100 is cut from the memory wafer 10. The conductor 75A does not pass through a conductor that functions as wiring 15. Figure 12 The conductor 76 is connected to the conductor 78.

[0254] On the upper surface of conductor 78, conductor 83 is disposed as a redistribution layer, separated from conductor 82 which functions as a barrier metal. Conductor 83 may contain, for example, copper (Cu). Conductors 82 and 83 include: a contact portion extending in the Z direction in contact with conductor 78; and a wiring portion extending in the Y direction above the contact portion, which functions as pad unit PdU and wiring 15.

[0255] Conductors 82 and 83 are provided, for example, by an inlay method. More specifically, after insulator PI is provided on insulator INS_U and conductor 78, a predetermined area within insulator PI that functions as a redistribution layer is etched to expose conductor 78. Furthermore, after conductor 82 is provided in the etched area, conductor 83 is provided in a manner that fills the remaining portion of that area. Therefore, the side of conductor 83 is in contact with conductor 82 in the wiring portion, in addition to the contact portion.

[0256] An insulator PIA is provided on the upper surface of the conductor 83 so that the conductor 83 is divided into n parts along the Y direction when viewed from above. Thus, the conductor 83 has n parts on the upper surface of the memory chip 10 that can contact the probe electrode 21, and these n parts function as n pad electrodes 11_1 to 11_n (i.e., pad units PdU) that are electrically connected to each other.

[0257] Alignment mark 12 is formed, for example, on the upper surface of insulator INS_U with a structure equivalent to pad electrode 11. More specifically, conductor 80 is provided on the upper surface of insulator INS_U. Conductor 80 comprises, for example, aluminum (Al). Conductor 85 is provided on the upper surface of conductor 80, separated from conductor 84 which functions as a barrier metal. Conductor 85 comprises, for example, copper (Cu). Conductors 84 and 85 include: a contact portion that contacts conductor 80; and a portion on the upper part of the contact portion that can be visually distinguished from the surrounding insulators PI and PIA. Conductors 84 and 85 are provided, for example, by an inlay method in the same process as conductors 82 and 83. Conductors 84 and 85 are electrically disconnected from other conductors provided in memory chip 10 by insulator PI.

[0258] 2.2 Effects of this implementation method

[0259] According to the second embodiment, the wiring 15 and the pad unit PdU are provided by rewiring above the conductor 78. Therefore, the pad unit PdU can be provided without performing the steps of placing the wiring 15 between the conductor 78 and the memory cell array MCA, and the steps of placing n conductors 78 electrically connected to the wiring 15. Therefore, in this embodiment where the memory wafer 10 is used on a wafer-by-wafer basis, and in the case where it is cut out on a NAND chip cell basis, the processes up to the placement of the conductor 78 can be made consistent. Therefore, the increase in the manufacturing load of the memory wafer 10 can be suppressed.

[0260] In addition, by providing a redistribution layer above the conductor 78, the flexibility of the pad electrode 11 configuration can be increased.

[0261] More specifically, for example, the conductors 78 disposed in each of the plurality of NAND chip cells 100 can be electrically connected through a redistribution layer. This allows multiple transmission paths transmitting the same information to the plurality of NAND chip cells 100 to be merged into one. Therefore, the number of pad electrodes 11 on the memory chip 10 can be reduced, and the number of probe electrodes 21 on the probe card 20 can be reduced.

[0262] Furthermore, by reconfiguring the pad electrodes 11 from the position of conductor 78, multiple pad electrodes 11 electrically connected to a NAND controller chip 200 can be concentrated near the NAND controller chip 200 when viewed from above. Consequently, probe electrodes 21 electrically connected to the NAND controller chip 200 can be concentrated near the NAND controller chip 200 when viewed from above. Therefore, the wiring length between the NAND controller chip 200 and the probe electrodes 21 can be shortened, the timing deviation of the signal between the wirings can be reduced, and the increase in the design load of the wiring within the probe card 20 can be suppressed.

[0263] Alternatively, the pad electrodes 11 can be reconfigured to arrange them at equal intervals on the memory chip 10. Consequently, the probe electrodes 21 on the probe card 20 can also be arranged at equal intervals. Therefore, restrictions on interference between the probe electrodes 21 can be relaxed, reducing the design load on the probe card 20.

[0264] 2.3 Variations

[0265] Furthermore, the second embodiment described above can be modified in various ways. In the various modifications shown below, descriptions of structures and operations that are identical to those of the second embodiment are omitted, and descriptions will mainly focus on structures and operations that differ from those of the second embodiment.

[0266] 2.4.1 First Variation Example

[0267] In the second embodiment described above, the case of setting the redistribution layer by tiling was explained, but it is not limited to this. For example, the redistribution layer can also be set by etching the conductors provided on the conductors 78 that serve as bonding pads.

[0268] Figure 27 This is an example of a structure corresponding to the pad unit and alignment mark involved in the first variation of the second embodiment, and is consistent with the structure in the second embodiment. Figure 26 Correspondingly.

[0269] like Figure 27 As shown, a conductor 82A is provided on the upper surface of the conductor 78 to function as a barrier metal, and a conductor 83A is provided on the upper surface of the conductor 82A. The conductor 83A may contain, for example, copper (Cu). The conductors 82A and 83A include: a contact portion that is in contact with the conductor 78 and extends in the Z direction; and a wiring portion that extends in the Y direction above the contact portion and functions as a pad unit PdU and wiring 15.

[0270] Conductors 82A and 83A are shaped into appropriate forms, for example, by etching, as a rewiring layer. More specifically, on insulator INS_U and conductor 78, insulator PI is set to a predetermined height for the contact portions of conductors 82A and 83A. Then, a predetermined area in insulator PI where the contact portions are set is etched, exposing conductor 78. Next, conductor 82A is set across the entire surface of the upper surface of conductor 78 and insulator PI, and conductor 83A is set on the upper surface of conductor 82A. Conductor 83A is set to a predetermined height for the wiring portions. Moreover, conductors 82A and 83A are etched into appropriate shapes as a rewiring layer, and the etched area is filled by insulator PI. Therefore, the side of conductor 83A is in contact with conductor 82A at the contact portion, but in contact with insulator PI at the wiring portion.

[0271] Alignment mark 12 is formed, for example, on the upper surface of insulator INS_U, having the same structure as pad electrode 11. More specifically, conductor 80 is provided on the upper surface of insulator INS_U. Conductor 84A, which functions as a barrier metal, is provided on the upper surface of conductor 80, and conductor 85A is provided on the upper surface of conductor 84A. Conductor 85A, for example, contains copper (Cu). Conductors 84A and 85A include: a contact portion that contacts conductor 80; and a portion on the upper part of the contact portion that can be visually distinguished from the surrounding insulators PI and PIA. Conductors 84A and 85A are provided, for example, in the same process as conductors 82A and 83A. Conductors 84A and 85A are electrically disconnected from other conductors provided in memory chip 10 by insulator PI.

[0272] With the structure described above, similar to the second embodiment, wiring 15 and pad unit PdU can also be provided above the conductor 78. Therefore, it can have the same effect as the second embodiment.

[0273] 2.4.2 Second Variation

[0274] Furthermore, in the first variation of the second embodiment described above, the conductors 82A and 83A were described as including a contact portion that contacts the conductor 78 and a wiring portion above the contact portion that functions as a pad unit PdU and wiring 15, but this is not a limitation. For example, a conductor different from the conductor 78 may be provided on the upper surface of the conductor 78 by electroless electroplating growth, and then a conductor corresponding to the wiring portion may be provided.

[0275] Figure 28 This is an example of a structure corresponding to the pad unit and alignment mark involved in the second variation of the second embodiment, and is consistent with the structure in the first variation of the second embodiment. Figure 27 Correspondingly.

[0276] like Figure 28 As shown, a conductor 86 is disposed on the upper surface of the conductor 78. The conductor 86 is a dissimilar metal relative to the conductor 78, grown on the conductor 78 by an electroless electroplating growth method, and includes at least one metal selected from nickel (Ni), gold (Au), cobalt (Co), palladium (Pd), copper (Cu) and silver (Ag).

[0277] On the upper surface of the conductor 86, a conductor 82B is provided, which functions as a barrier metal, and a conductor 83B is provided on the upper surface of the conductor 82B. The conductor 83B contains, for example, copper (Cu). The conductors 82B and 83B have the same structure and manufacturing method as the wiring portions of the conductors 82A and 83A in the first modification of the second embodiment, so their description is omitted.

[0278] Alignment mark 12 is formed, for example, on the upper surface of insulator INS_U with a structure equivalent to pad electrode 11. More specifically, conductor 80 is provided on the upper surface of insulator INS_U, and conductor 87 is provided on the upper surface of conductor 80. Conductor 87, for example, contains at least one metal selected from nickel (Ni), gold (Au), cobalt (Co), palladium (Pd), copper (Cu), and silver (Ag), and contains the same material as conductor 86. Conductor 84B is provided on the upper surface of conductor 86 to function as a barrier to the metal, and conductor 85B is provided on the upper surface of conductor 84B. Conductor 85B, for example, contains copper (Cu). Conductors 84B and 85B have the same structure and manufacturing method as the wiring portion of conductors 84A and 85A in the first modification of the second embodiment, therefore their description is omitted.

[0279] Based on the structure described above, similar to the second embodiment and the first variation of the second embodiment, the wiring 15 and the pad unit PdU can be provided above the conductor 78. Therefore, it can have the same effect as the second embodiment and the first variation of the second embodiment.

[0280] 2.4.3 Third variation

[0281] In the second embodiment and the first and second modifications of the second embodiment described above, the case in which an insulator PIA is provided on the upper surface of the conductor 83, which functions as a pad unit PdU and wiring 15, dividing the exposed surface of the conductor 83 into n parts, was described, but it is not limited to this. For example, the surface of the conductor 83 that reaches the upper surface of the memory chip 10 may not be divided into n parts by the insulator PIA.

[0282] Figure 29 This is an example of a structure corresponding to the pad unit and alignment mark involved in the third variation of the second embodiment, and is consistent with the second embodiment. Figure 26 Correspondingly.

[0283] like Figure 29 As shown, the conductor 83 extends along the Y direction and has a surface whose upper surface reaches the upper surface of the memory chip 10, and the surface is not divided along the Y direction by the insulator PIa.

[0284] By configuring it in the above manner, the pad unit PdU is not divided into multiple pad electrodes 11_1 to 11_n, but becomes a single pad electrode 11s extending along the Y direction. As a result, the area of ​​the pad unit PdU can be increased, and the degree of freedom in the position of contact with the probe electrode 21 can be increased during landing processing.

[0285] Furthermore, in the above example, the number of probes for each pad group PdG was managed through the probe management table 335, but in the second variation of the second embodiment, this is not the limitation. For example, the probe management table 335 may store the number of probes not in units of pad groups PdG, but in units of memory wafers 10. In this case, the detector 3 may continuously change the position of the pad electrode 11s in contact with the probe electrode 21 along the Y direction, corresponding to the number of probes per unit of memory wafer 10. That is, the detector 3 may make the contact position of the pad electrode 11s with the probe electrode 21 different each time the landing process is performed.

[0286] 3. Third Implementation Method

[0287] Next, the storage system according to the third embodiment will be described.

[0288] In the third embodiment, a specific example is shown of a plurality of pad electrodes 11 reconfigured on the memory wafer 10 by means of a structure containing a redistribution layer as described in the second embodiment. In the following description, the pad electrodes 11 containing aluminum (Al) formed on the NAND chip cell 100 will be distinguished as needed from the pad electrodes 11R formed above the pad electrodes 11 separated by the redistribution layer.

[0289] 3.1 Structure of reconfigured pad electrodes

[0290] Figure 30 This is a schematic diagram illustrating an example of the structure of the reconfigured pad electrodes according to the third embodiment. Figure 30 The image schematically illustrates a portion of the connection between a NAND controller chip 200 and a memory chip 10. Figure 31This is a top view showing an example of the positional relationship between the reconfigured pad electrode and the original pad electrode according to the third embodiment. Figure 31 and Figure 30 Correspondingly, the changes in the positions of the pad electrodes before and after reconfiguration are shown when viewing the memory chip 10 from above. Figure 30 and Figure 31 In this text, the interlayer insulating film is appropriately omitted. Furthermore, in... Figure 30 and Figure 31 In the illustration, for ease of explanation, the cutting line 13 and the edge sealing portion 14 are represented as a solid rectangle surrounding the plurality of pad electrodes 11 within the corresponding NAND chip unit 100.

[0291] like Figure 30 and Figure 31 As shown, the memory chip 10 comprises a group (chipset CS) of multiple NAND chip cells 100 connected to a corresponding NAND controller chip 200 via a probe card 20 and probe electrodes 21. Each NAND chip cell 100 includes, for example, multiple pad electrodes 11p and multiple pad electrodes 11q. Figure 30 and Figure 31 In this example, the chipset CS contains eight NAND chip cells 100. Additionally, in... Figure 30 and Figure 31 In the example, the eight NAND chip cells 100 in the chipset CS each contain two pad electrodes 11p.

[0292] Pad electrode 11p is a pad electrode connected to pad electrode 11Rp redistributed within region PdR via redistribution layer RDL. Redistribution layer RDL can be formed across the NAND chip cell 100 (cut line 13 and edge seal 14). That is, redistribution layer RDL can be formed to intersect with cut line 13. Pad electrode 11p is used, for example, in the application of power supply voltage. Pad electrode 11q is a pad electrode connected to pad electrode (not shown) redistributed outside region PdR via redistribution layer (not shown). Pad electrode 11q is used, for example, in the input and output of various control signals. Two adjacent pad electrodes 11 are arranged apart with a spacing p1 when viewed from above. Spacing p1 is, for example, 30 micrometers. In the third embodiment, pad electrode 11p, of pad electrodes 11p and 11q, will be mainly described.

[0293] Region PdR is located directly below the corresponding NAND controller chip 200 and is smaller than the region containing the entire chipset CS. For example, when viewed from above, region PdR is included within the region containing the entire chipset CS and includes the corresponding NAND controller chip 200. That is, when viewed from above, the pad electrode 11Rp reconfigured within region PdR is closer to the NAND controller chip 200 than the original pad electrode 11p.

[0294] Multiple pad electrodes 11Rp are reconfigured, for example, in a manner that extends 2D within the region PdR. Figure 30 In the example shown, two adjacent pad electrodes 11Rp are arranged with a spacing p2 in the X direction and a spacing p3 in a direction intersecting the X direction. Spacing p2 and p3 are longer than spacing p1 (p2 > p1, p3 > p1). Spacing p2 and p3 are preferably longer than 100 micrometers, for example. Spacing p2 and p3 are more preferably longer than 200 micrometers, for example. Furthermore, when viewed from above, the area of ​​pad electrode 11Rp is larger than the area of ​​pad electrode 11p.

[0295] Figure 32 It is observed along the Y direction. Figure 31 A side view of the configuration of the main elements of region XXXII shows an example of a structure including the reconfigured pad electrodes according to the third embodiment. Therefore, in Figure 32 In this paper, for ease of explanation, all elements are shown on the same page, but... Figure 32 The various elements shown in the diagram are not limited to the same position along the Y direction. Figure 32 The structure from the semiconductor substrate 70 to the conductor 78 corresponding to the pad electrodes 11p and 11q is the same as in the first embodiment. Figure 11 Similarly, the explanation is omitted. In addition, the plurality of conductors 78 arranged along the X direction are separated by a distance p1 and are adjacent to each other along the X direction.

[0296] like Figure 32 As shown, a conductor 88, used as a redistribution layer RDL, is disposed on the upper surface of each of the plurality of conductors 78. The plurality of conductors 88, for example, each includes a conductor 88_1 extending in the Y direction and a conductor 88_2 extending in the X direction. Thus, the conductor 88 has at least a two-layer structure having portions extending in different directions from each other.

[0297] Conductor 88_1 is used as the lower redistribution layer RDL in a two-layer redistribution layer RDL. The film thickness of conductor 88_1 is approximately constant. Furthermore, conductor 88_1 is not planarized by CMP (Chemical Mechanical Polishing). Therefore, although in Figure 32Unless explicitly stated, the contact portion of conductor 88_1 with conductor 78 may have a recessed shape relative to the portion extending along the Y direction. Conductor 88_1 includes conductor 88_1a, conductor 88_1b, and conductor 88_1c.

[0298] Conductor 88_1a is used as a seed layer for conductor 88_1b. Conductor 88_1a may contain, for example, titanium copper (TiCu). Conductor 88_1a includes: a first portion connected to conductor 78; a second portion extending in the Y direction above the first portion; and a third portion connecting the first portion and the second portion.

[0299] An oxide film INS_T is provided on the upper surface of the insulator INS_U in such a way that it is in contact with the side surface of the conductor 78, the side surface of the first part of the conductor 88_1a, and the lower surface of the third part of the conductor 88_1a.

[0300] An organic film PI1 is disposed on the upper surface of the oxide film INS_T, in contact with the side surface of the third portion of the conductor 88_1a and the lower surface of the second portion of the conductor 88_1a. The organic film PI1 is used as a passivation layer. The organic film PI1 contains, for example, polyimide.

[0301] Conductor 88_1b is used as the main wiring portion of the lower rerouting layer RDL. Conductor 88_1b contains, for example, copper (Cu). The lower surface of conductor 88_1b is in contact with the upper surface of the corresponding conductor 88_1a. Furthermore, the lower surface of conductor 88_1b may have a portion at its end along the XY plane that is not in contact with conductor 88_1a.

[0302] Conductor 88_1c is used as a protective layer for conductor 88_1b. Conductor 88_1c contains, for example, nickel (Ni). The lower surface of conductor 88_1c is in contact with the upper surface of the corresponding conductor 88_1b. The upper surface of conductor 88_1c has a portion that is in contact with the lower surface of the corresponding conductor 88_2.

[0303] Conductor 88_2 is used as the upper redistribution layer RDL in a two-layer redistribution layer RDL. The film thickness of each conductor 88_2 is approximately constant. Furthermore, conductor 88_2 is not planarized by CMP. Therefore, similar to conductor 88_1, the contact portion of conductor 88_2 with conductor 88_1 can have a recessed shape relative to the portion extending along the X direction. Conductor 88_2 includes conductor 88_2a, conductor 88_2b, and conductor 88_2c.

[0304] Conductor 88_2a is used as a seed layer for conductor 88_2b. Conductor 88_2a comprises, for example, titanium copper (TiCu). Conductor 88_2a includes: a first portion connected to conductor 88_1c; a second portion extending in the X direction above the first portion; and a third portion connecting the first portion and the second portion.

[0305] On the upper surface of the organic film PI1, an organic film PI2 is disposed in contact with the side surface of the second portion of conductor 88_1a, the side surface of conductor 88_1b, the side surface of conductor 88_1c, the side surface of the first portion of conductor 88_2a, and the lower surface of the third portion of conductor 88_2a. The organic film PI2 is used as a passivation layer. The organic film PI2 contains, for example, polyimide.

[0306] An organic film PI3 is disposed on the upper surface of the organic film PI2, in contact with the side surface of the third portion of the conductor 88_2a and the lower surface of the second portion of the conductor 88_2a. The organic film PI3 is used as a passivation layer. The organic film PI3 contains, for example, polyimide.

[0307] Conductor 88_2b is used as the main wiring portion of the lower rerouting layer RDL. Conductor 88_2b contains, for example, copper (Cu). The lower surface of conductor 88_2b is in contact with the upper surface of the corresponding conductor 88_2a. Furthermore, the lower surface of conductor 88_2b may have a portion at its end along the XY plane that is not in contact with conductor 88_2a.

[0308] Conductor 88_2c is used as a protective layer for conductor 88_2b. Conductor 88_2c contains, for example, nickel (Ni). The lower surface of conductor 88_2c is in contact with the upper surface of the corresponding conductor 88_2b. The upper surface of conductor 88_2c has a portion that is in contact with the lower surface of the corresponding conductor 89.

[0309] Conductor 89 is used as pad electrode 11Rp. The upper surface of conductor 89 can have a shape in which the central part is recessed relative to the peripheral part. Conductor 89 includes conductor 89a, conductor 89b and conductor 89c.

[0310] Conductor 89a is used as a seed layer for conductor 89b. Conductor 89a may contain, for example, titanium copper (TiCu). Conductor 89a includes: a first portion connected to conductor 88_2c; and a second portion connected to the first portion and extending in the XY plane above the first portion.

[0311] On the upper surface of the organic film PI3, an organic film PI4 is disposed in contact with the side surface of the second portion of conductor 88_2a, the side surface of conductor 88_2b, the side surface of conductor 88_2c, the side surface of the first portion of conductor 89a, and the lower surface of the second portion of conductor 89a. The organic film PI4 is used as a passivation layer. The organic film PI4 contains, for example, polyimide.

[0312] Conductor 89b is used as a main part of pad electrode 11Rp. Conductor 89b contains, for example, nickel (Ni). The lower surface of conductor 89b is in contact with the upper surface of the corresponding conductor 89a. Furthermore, the lower surface of conductor 89b may have a portion at its end along the XY plane that is not in contact with conductor 89a.

[0313] Conductor 89c is used as a protective layer for conductor 89b. Conductor 89c may contain, for example, gold (Au). The lower surface of conductor 89c is in contact with the upper surface of the corresponding conductor 89b. The upper surface of conductor 89c is positioned above the organic film PI4 for contact with probe electrode 21.

[0314] In addition, Figure 32 For ease of explanation, the diagram shows conductors 78 and 89 located in the same XZ plane. However, in reality, conductor 89 is not positioned directly above conductor 78. This is to avoid conductor 89 being recessed downwards compared to the organic film PI4 due to the recessed shape of the portion of conductor 88_1 directly above conductor 78.

[0315] 3.2 Effects of this implementation method

[0316] According to the third embodiment, the pad electrode 11 before reconfiguration and the pad electrode 11R after reconfiguration are connected through at least two redistribution layers RDL. This allows the pad electrode 11R to be positioned relative to the pad electrode 11 at a desired location in the XY plane.

[0317] Specifically, the spacing p2 and p3 between adjacent pad electrodes 11R can be configured to be longer than the spacing p1 between adjacent pad electrodes 11. This reduces the alignment load during the alignment process of the probe electrode 21 that contacts the reconfigured pad electrode 11Rp.

[0318] Furthermore, the pad electrode 11p is connected to the pad electrode 11Rp, which is arranged across the dicing line, via a redistribution layer RDL that intersects with the dicing line 13. This allows multiple pad electrodes 11p distributed for each NAND chip cell 100 to be integrated into a region PdR that is narrower than the region surrounding the chipset CS and directly below the NAND controller chip 200. Therefore, the wiring length between the probe electrode 21 and the NAND controller chip 200 can be shortened compared to the case where pad electrodes outside the region PdR are used. This reduces the design load of the wiring in the probe card 20.

[0319] 3.3 Variations

[0320] Furthermore, the third embodiment described above can be modified in various ways.

[0321] 3.3.1 First Variation

[0322] In the third embodiment described above, the case where individual pad electrodes 11Rp are assigned to the pad electrodes 11p within each NAND chip cell 100 has been explained, but this is not a limitation. For example, the pad electrodes 11Rp may also be shared among the NAND chip cells 100.

[0323] Figure 33 This is a top view illustrating an example of the positional relationship between the reconfigured pad electrode and the original pad electrode according to the first modification of the third embodiment. Figure 33 In the example shown, the eight NAND chip cells 100 in the chipset CS each contain two pad electrodes 11p.

[0324] like Figure 33 As shown, within region PdR, four pad electrodes 11Rp are allocated relative to the 16 pad electrodes 11p within the chipset CS. That is, one pad electrode 11Rp is connected to four pad electrodes 11p within a different NAND chip cell 100 via at least one redistribution layer RDL.

[0325] Multiple pad electrodes 11p that are connected to the pad electrode 11Rp can be connected to the pad electrode 11Rp via different redistribution layers (RDLs). That is, there can be two or more redistribution layers (RDLs) that connect one pad electrode Rp and multiple pad electrodes 11p.

[0326] Additionally, a certain pad electrode 11p can be connected to other pad electrodes 11p without passing through a redistribution layer RDL (e.g., via a routing layer DL formed on the same layer as the pad electrode 11p). Moreover, the certain pad electrode 11p can be connected to the pad electrode 11Rp via a redistribution layer RDL connected to the other pad electrode 11p.

[0327] Based on the structure described above, when a common signal or voltage is supplied to multiple NAND chip cells 100, the number of pad electrodes 11Rp used to supply the common signal or voltage can be reduced. This allows for a larger margin in the spacing between the pad electrodes 11Rp. Consequently, the alignment load during the alignment process can be reduced.

[0328] 3.3.2 Second variation

[0329] In the third embodiment and the first variation of the third embodiment described above, the case where there is one pad electrode 11Rp connected to one pad electrode 11p was described, but it is not limited to this. For example, multiple pad electrodes 11Rp may be provided for one pad electrode 11p.

[0330] Figure 34 This is a top view illustrating an example of the positional relationship between the reconfigured pad electrode and the original pad electrode according to the second modification of the third embodiment. Figure 34 In the example shown, the eight NAND chip cells 100 in the chipset CS each contain one pad electrode 11p.

[0331] like Figure 34 As shown, within region PdR, 16 pad electrodes 11Rp are allocated relative to the 8 pad electrodes 11p within the chipset CS. That is, one pad electrode 11p is connected to two pad electrodes 11Rp via the redistribution layer RDL.

[0332] Based on the structure described above, as explained in the first and second embodiments, the pad electrodes 11Rp that contact the probe electrode 21 can be made redundant. Therefore, even if the first pad electrode 11Rp becomes unusable due to the landing process, the NAND chip cell 100 and the NAND controller chip 200 can be connected using the second pad electrode 11Rp. Furthermore, in Figure 34The text describes the case where two pad electrodes 11Rp are set for one pad electrode 11p, but it is not limited to this; three or more pad electrodes 11Rp can also be set. Additionally, multiple pad electrodes 11R can be set for pad electrode 11q. The number of pad electrodes 11R set for pad electrode 11q can differ from the number of pad electrodes 11Rp set for pad electrode 11p.

[0333] 4. Other

[0334] Furthermore, in the first to third embodiments and various modifications described above, the case in which the memory chip 10 is moved relative to the fixed probe card 20, thereby connecting the NAND controller chip 200 to the NAND chip cell 100, has been described, but it is not limited to this. For example, the probe card 20 may be moved relative to the fixed memory chip 10, and a drive control system 32 may be provided in which either the memory chip 10 or the probe card 20 can be moved.

[0335] Furthermore, in the first to third embodiments and various modifications described above, the probe management table 335 is stored in the interface control system 33, but this is not a limitation. For example, the probe management table 335 may also be appropriately stored in the memory chip 10, or it may be managed by the host device 2.

[0336] Furthermore, in the first to third embodiments and various modifications described above, the case of providing one detector 3 within the storage system 1 was explained, but multiple detectors 3 may also be provided within the storage system 1. In this case, the probe management table 335 preferably stores the total number of probes performed with respect to the storage chip 10, regardless of whether any of the multiple detectors 3 are used. Therefore, the probe management table 335 can be managed by a device (e.g., host device 2) capable of controlling multiple detectors 3.

[0337] Furthermore, in the first to third embodiments and various modifications described above, the memory chip 10 was provided as being provided by bonding two chips (LW and UW), but this is not a limitation. For example, multiple NAND chip cells 100 within the memory chip 10 may also be provided on a single chip. In this case, the memory cell array (MCA) may be provided in contact with the substrate or may be provided above the substrate without being in contact with it. When the memory cell array (MCA) is provided in contact with the substrate, the peripheral circuitry (PERI) may be provided on the substrate surrounding the memory cell array (MCA). Alternatively, when the memory cell array (MCA) is provided above the substrate, the peripheral circuitry (PERI) may be provided on the substrate below the memory cell array (MCA).

[0338] Furthermore, in the first to third embodiments and various modifications described above, the semiconductor memory device provided on the memory chip 10 is a NAND flash memory, but this is not a limitation. For example, the semiconductor memory device provided on the memory chip 10 may also be a NOR type.

[0339] Several embodiments of the present invention have been described, but these embodiments are given by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention, and are equally included within the scope of the invention as described in the claims and its equivalents.

Claims

1. A storage system, wherein, have: A first memory chip cell, serving as a memory chip unit, includes a first pad electrode and a first memory cell array electrically connected to the first pad electrode. The pad electrode includes a first portion and a second portion electrically connected to each other. The detector is capable of holding the first memory chip cell and reading and writing to the array of the first memory cells held by the first memory chip cell. The detector includes: The probe card includes a first probe electrode capable of contacting the first pad electrode of the held first memory chip cell, and a first memory controller electrically connected to the first probe electrode and capable of reading and writing the first memory cell array via the first probe electrode. as well as The moving mechanism moves the probe card or the held first memory chip cell to bring the first pad electrode of the held first memory chip cell into contact with the first probe electrode. The moving mechanism is capable of performing a first action and a second action, wherein the first action causes the first probe electrode to contact the first portion of the first pad electrode but not the second portion of the first pad electrode, and the second action causes the first probe electrode to contact the second portion of the first pad electrode but not the first portion of the first pad electrode. The moving mechanism is configured such that, If the first condition is not met, perform the first action. The second action is performed if the first condition is met. The first condition includes: the first memory controller fails in the error correction processing of data from the first memory chip cell.

2. The storage system as claimed in claim 1, wherein, The storage system further includes a first wafer as a storage chip, the first wafer containing the first memory chip unit. The detector is capable of holding the first wafer, thereby holding the first memory chip cell. The moving mechanism moves the first memory chip cell by moving the first wafer.

3. The storage system as described in claim 1, wherein, The first condition includes: the number of contacts between the first probe electrode and the first portion of the first pad electrode is greater than or equal to a first threshold.

4. The storage system as claimed in claim 1, wherein, The first condition includes: the first memory chip cell fails in the error correction process of the data from the first memory controller.

5. The storage system as claimed in claim 1, wherein, The first memory chip cell includes a latch circuit that is connected to both the first portion and the second portion of the first pad electrode.

6. The storage system as claimed in claim 3, wherein, The storage system further includes a first wafer as a storage chip, the first wafer containing the first memory chip unit. The detector is capable of holding the first wafer, thereby holding the first memory chip cell. The moving mechanism moves the first memory chip cell by moving the first wafer, and the memory system also includes a second wafer. The moving mechanism is also capable of performing a third action that brings the first probe electrode into contact with the second wafer.

7. The storage system of claim 6, wherein, The moving mechanism is configured such that, if the second condition is met, after performing the third action, it performs either the first action or the second action.

8. The storage system of claim 7, wherein, The second condition includes: the number of contacts between the first probe electrode and the first wafer is greater than the second threshold value of the first threshold value.

9. The storage system as claimed in claim 2, wherein, The first wafer further includes a second memory chip cell as a memory chip unit. The second memory chip cell includes a second pad electrode and a second memory cell array electrically connected to the second pad electrode. The second pad electrode includes a first portion and a second portion electrically connected to each other. The probe card also includes a second probe electrode electrically connected to the first memory controller. The first action further includes: bringing the second probe electrode into contact with the first portion of the second pad electrode. The second action further includes: bringing the second probe electrode into contact with the second portion of the second pad electrode.

10. The storage system of claim 2, wherein, The first wafer further includes a third memory chip cell as a memory chip unit, the third memory chip cell including a third pad electrode and a third memory cell array electrically connected to the third pad electrode, the third pad electrode including a first portion and a second portion electrically connected to each other. The probe card also includes a third probe electrode and a second memory controller electrically connected to the third probe electrode. The first action further includes: bringing the third probe electrode into contact with the first portion of the third pad electrode. The second action further includes: bringing the third probe electrode into contact with the second portion of the third pad electrode.

11. The storage system of claim 2, wherein, The first pad electrode has a shape that protrudes from the first wafer toward the probe card when the first wafer is disposed on the detector. The portion of the first probe electrode that faces the first wafer disposed on the detector has a flat plate shape.

12. The storage system of claim 1, wherein, The memory chip unit has: A memory structure includes a plurality of first conductive layers stacked on a substrate in a first direction, a first semiconductor layer extending in the first direction within the plurality of first conductive layers, and a first charge storage layer disposed between the plurality of first conductive layers and the first semiconductor layer. The first wiring layer and the second wiring layer are disposed above the memory structure in an electrically insulated manner from each other; A second conductive layer is disposed on the upper surface of the first portion of the first wiring layer; A third conductive layer is disposed on the upper surface of the second portion of the first wiring layer; A fourth conductive layer is disposed on the upper surface of the first portion of the second wiring layer; as well as The fifth conductive layer is disposed on the upper surface of the second portion of the second wiring layer. The second, third, fourth, and fifth conductive layers comprise aluminum (Al). In a plane parallel to the substrate, the relative position of the fourth conductor layer with respect to the second conductor layer is the same as the relative position of the fifth conductor layer with respect to the third conductor layer.

13. The storage system of claim 12, wherein, The orientation of the second and third conductive layers is parallel to the orientation of the fourth and fifth conductive layers. The orientation of the second and fourth conductive layers is parallel to the orientation of the third and fifth conductive layers.

14. The storage system of claim 12, wherein, The memory chip unit also has: A sixth conductive layer is disposed on the upper surface of the second conductive layer; and The seventh conductor layer is disposed on the upper surface of the third conductor layer. The sixth and seventh conductive layers contain metals different from those in the second and third conductive layers.

15. The storage system of claim 14, wherein, The sixth and seventh conductive layers comprise at least one metal selected from nickel (Ni), gold (Au), cobalt (Co), palladium (Pd), copper (Cu), and silver (Ag).

16. The storage system of claim 14, wherein, The upper surfaces of the 6th and 7th conductor layers are located above the upper surface of the insulating layer between the 6th and 7th conductor layers.

17. The storage system of claim 12, wherein, The memory chip unit also has a dicing line disposed between the second conductor layer and the third conductor layer.

18. The storage system of claim 2, wherein, The memory chip includes: A memory structure includes: a plurality of first conductive layers stacked on a substrate in a first direction, a first semiconductor layer extending in the first direction within the plurality of first conductive layers, and a first charge storage layer disposed between the plurality of first conductive layers and the first semiconductor layer. A second conductive layer is disposed above the memory structure; A third conductor layer is disposed above the second conductor layer; The fourth conductor layer electrically connects the second conductor layer and the third conductor layer; as well as An insulating layer, disposed between the second conductive layer and the third conductive layer, comprises polyimide. When viewed from above, The fourth conductor layer intersects with the cutting line. The second conductive layer and the third conductive layer sandwich the cutting line.

19. The storage system of claim 18, wherein, The second conductive layer comprises aluminum (Al). The fourth conductor layer contains copper (Cu).

20. The storage system of claim 19, wherein, It also has: The fifth conductor layer is adjacent to the second conductor layer in the first plane parallel to the substrate; as well as The sixth conductive layer is adjacent to the third conductive layer in the second plane parallel to the substrate. The distance between the third conductor layer and the sixth conductor layer is longer than the distance between the second conductor layer and the fifth conductor layer.

21. The storage system of claim 20, wherein, It also has a 7th conductive layer that is electrically connected to the 6th conductive layer within the 1st surface. The distance between the third conductor layer and the sixth conductor layer is shorter than the distance between the second conductor layer and the seventh conductor layer.

22. The storage system of claim 20, wherein, The orientation of the second and fifth conductor layers is different from that of the third and sixth conductor layers.

23. The storage system of claim 19, wherein, When viewed from above, the area of ​​the third conductive layer is larger than the area of ​​the second conductive layer.

24. The storage system of claim 19, wherein, It also has an eighth conductive layer comprising aluminum (Al), which is electrically connected to the third conductive layer via the second conductive layer.

25. The storage system of claim 19, wherein, It also has a 9th conductive layer comprising aluminum (Al), which is electrically connected to the 3rd conductive layer without passing through the 2nd conductive layer.

26. The storage system of claim 19, wherein, It also has a 10th conductive layer comprising aluminum (Al), which is electrically connected to the 3rd conductive layer without passing through the 2nd and 4th conductive layers.

27. The storage system of claim 19, wherein, The third conductive layer contains gold (Au) or nickel (Ni).

Images