Interconnect with lateral connection to substrate

Abstract

An interconnect structure is disclosed. The interconnect structure includes a base substrate, a set of conductive pads disposed on the base substrate, and an interconnect layer disposed on the base substrate. The interconnect layer has an edge positioned adjacent to the set of conductive pads and includes a set of side connection pads positioned and arranged at the edge of the interconnect layer. Each side connection pad is disposed relative to a corresponding one of the conductive pads disposed on the base substrate.

Description

BACKGROUND OF THE INVENTION

[0001] The present invention generally relates to interconnect technologies, and more particularly, to interconnect structures, interconnect layer carrier structures, and methods of manufacturing the same.

[0002] In response to the growing demand for broadband signal transmission between chips (or dies), several techniques for high-density interconnects between chips have been proposed.

[0003] To establish interconnects between chips mounted on an organic substrate, interconnect structures using interconnect members connected to or embedded in the organic substrate have been developed. Examples of such interconnect members disposed on the organic substrate include silicon bridges and organic hierarchical interconnects. The use of such interconnect members often limits the wiring for connecting chips and driving chips. It can also limit the terminal layout of the chips. For example, although it is preferred to arrange the ground terminals and power terminals of the chips above the interconnect members, it is often difficult to route the wiring from the power terminals and ground terminals of the chips to the external power supply and ground wires of the organic substrate. SUMMARY OF THE INVENTION

[0004] According to an embodiment of the present invention, an interconnect structure is provided. The interconnect structure includes a base substrate, a set of conductive pads disposed on the base substrate, and an interconnect layer disposed on the base substrate. The interconnect layer has an edge adjacent to the set of conductive pads and includes a set of side connection pads exposed at the edge of the interconnect layer, wherein each side connection pad is disposed relative to a corresponding one of the conductive pads disposed on the base substrate.

[0005] The interconnect structure according to an embodiment of the present invention allows us to introduce a new type of side connection between the conductive pads of the base substrate and the side connection pads of the interconnect layer. Introducing the new type of side connection improves the flexibility of the wiring and the wiring of the interconnect layer. Therefore, since the wiring can be optimized according to the improved wiring flexibility, the performance of the electronic device using the interconnect structure can be improved. In addition, it relaxes the constraints on the terminal layout of the chips using the interconnect layer.

[0006] In a preferred embodiment, each side connection pad has a top surface exposed at the top surface of the interconnect layer and an edge surface exposed at the edge of the interconnect layer, wherein the edge surface faces a corresponding one of the conductive pads. Therefore, since both the edge surface and the top surface are involved in the side connection to increase the contact area, the reliability and manufacturing yield of the side connection can be improved.

[0007] In a further preferred embodiment, the edge surface and / or the top surface of each side connection pad has a barrier metal. Thereby, the reliability of the side connection can be improved.

[0008] In another preferred embodiment, the interconnect layer further includes an insulating material that gives the top surface of the interconnect layer and a set of first bonding pads exposed from the insulating material at the top surface of the interconnect layer. The set of first bonding pads is used for mounting chips. Each first bonding pad is connected to a corresponding one of the side connection pads via wiring embedded in the insulating material. Thus, an electrical connection can be introduced between the chips mounted on the base substrate and other components of the base substrate via the first bonding pads and the side connections.

[0009] In a specific embodiment, the interconnect layer further includes second bonding pads for mounting chips and third bonding pads for mounting other chips, wherein the second bonding pads are connected to the third bonding pads via traces embedded in the insulating material. Thus, a cheap, reliable high-density interconnect with a novel side connection is provided between the stacked chips.

[0010] In a preferred embodiment, the edge of the interconnect layer has one or more curved or angled shapes to extend its length, and the set of side connection pads and the set of conductive pads are formed along the contour of one or more curved or angled shapes. Thereby, the density of the side connections and / or the contact area of the side connections can be increased.

[0011] In a preferred embodiment, each pair of one side connection pad of the interconnect layer and one corresponding conductive pad provided on the base substrate is independently used for power or ground. Thus, compared with the case where wiring on the base substrate avoids the area of the interconnect layer at the same time, the voltage drop can be suppressed. It is advantageous for high-speed signal transmission to use the interconnect layer to provide a power supply or ground wire that serves as a signal return current path.

[0012] In a preferred embodiment, the base has a top surface. Each conductive pad has a pad surface. The top surface of the base substrate and the pad surface of each conductive pad have respective portions treated by a surface treatment for enhancing surface roughness. Thus, even when the pitch between adjacent side connection portions becomes narrow, bridging between adjacent side connection portions can be prevented, and the reliability of the side connection portions can be improved.

[0013] In a specific embodiment, the interconnect structure further includes a set of solder joints, each solder joint connecting one side connection pad of the interconnect layer to one corresponding conductive pad provided on the base substrate.

[0014] In other specific embodiments, the interconnect structure further includes one or more chips mounted on the base substrate, wherein at least one chip has a terminal that is electrically connected to one of the conductive pads provided on the base substrate via one of the side connection pads.

[0015] According to other embodiments of the present invention, an interconnection layer carrier structure is provided. The interconnection layer carrier structure includes a support substrate, a release layer formed on the support substrate, and an interconnection layer portion disposed on the release layer and having an edge. The interconnection layer portion includes an insulating material and a set of side connection pads embedded in the insulating material, the set of side connection pads being located at and exposed at the edge of the interconnection layer portion and formed at a predetermined interval along the edge of the interconnection layer portion.

[0016] The interconnection layer carrier structure according to other embodiments of the present invention can be used to transfer a precisely formed interconnection layer onto a substrate for manufacturing the above-mentioned interconnection structure. Providing the interconnection layer allows us to improve the wiring flexibility of the wiring and the interconnection layer and relax the restrictions on the terminal layout of the chips using the interconnection layer. By providing the interconnection layer carrier structure, the production cost can be reduced and the production efficiency of the interconnection structure can be improved.

[0017] According to yet another embodiment of the present invention, a method for manufacturing an interconnection structure is provided. The method includes providing a base substrate including a set of conductive pads disposed thereon. The method further includes: disposing an interconnection layer on the base substrate, wherein the interconnection layer includes a set of side connection pads located at and exposed at the edge of the interconnection layer. The interconnection layer is arranged such that the edge of the interconnection layer is located beside the set of conductive pads, and each side connection pad is disposed relative to a corresponding one of the conductive pads disposed on the base substrate.

[0018] The interconnection structure manufactured by the method according to the embodiments of the present invention allows us to introduce a new type of side connection between the conductive pads of the base substrate and the side connection pads of the interconnection layer. Introducing the new type of side connection improves the wiring flexibility of the wiring and the interconnection layer. Therefore, since the wiring can be optimized according to the improved wiring flexibility, the performance of the electronic device using the interconnection structure can be improved. In addition, it relaxes the restrictions on the terminal layout of the chips using the interconnection layer.

[0019] In a preferred embodiment, the base substrate has a top surface and each conductive pad has a pad surface. The method further includes applying a surface treatment for enhancing surface roughness to at least a part of the top surface of the base substrate adjacent to the conductive pads and the pad surfaces of each conductive pad, so that at least a part of the top surface of each conductive pad and the pad surfaces are rougher. Thereby, even if the pitch between adjacent side connection portions is fine, bridging between adjacent side connection portions can be prevented, and the reliability of the side connection portions can be improved.

[0020] In a specific embodiment, setting up the interconnect layer includes placing the interconnect layer carrier structure upside down on the base substrate. The interconnect layer carrier structure includes a support substrate, a release layer on the support substrate, and an interconnect layer portion on the release layer. The steps of setting up the interconnect layer include: releasing the interconnect layer portion from the support substrate by removing the release layer to provide the interconnect layer disposed on the base substrate.

[0021] According to another embodiment of the present invention, a method for preparing an interconnect layer carrier structure is provided. The method includes preparing a support substrate. The method further includes applying a release layer on the support substrate. The method also includes constructing an interconnect layer portion on the release layer. The interconnect layer portion has edges and includes an insulating material and a set of side connection pads embedded in the insulating material. The set of side connection pads is located at the ends of the interconnect layer portion and is exposed, and is formed at a predetermined interval along the ends of the interconnect layer portion.

[0022] The interconnect layer carrier structure manufactured by the method according to the embodiment of the present invention can be used to transfer the precisely formed interconnect layer onto the substrate, thereby manufacturing the above-mentioned interconnect structure. Providing the interconnect layer allows us to improve the wiring flexibility of the wiring and the interconnect layer and relax the constraints on the terminal layout of the chip using the interconnect layer. By setting up the interconnect layer carrier structure, the production cost can be reduced and the production efficiency of the wiring structure can be improved.

[0023] In a specific embodiment, the construction of the interconnect layer includes patterning the conductive material to provide a set of side connection pads on the release layer. The construction of the interconnect layer further includes forming an insulating portion on the release layer to embed the set of side connection pads.

[0024] Additional features and advantages are achieved by the techniques of the present invention. Other embodiments and aspects of the present invention are described in detail herein and are considered to be part of the claimed invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The subject matter regarded as the invention is particularly pointed out and distinctly claimed in the claims at the end of the specification. The above and other features and advantages of the present invention will become apparent from the following detailed description in conjunction with the accompanying drawings. Note that the dimensions and relative positions of the elements and layers in the drawings are not necessarily drawn to scale. Some of these elements or layers are arbitrarily enlarged and positioned for improving the readability of the drawings.

[0026] Figure 1A and Figure 1B is a schematic diagram of an interconnect substrate according to an embodiment of the present invention.

[0027] Figure 2 is a schematic diagram of an interconnect layer carrier structure for transferring an interconnect layer onto a target substrate according to an embodiment of the present invention.

[0028] Figures 3A to 3Cand Figures 4A to 4C is a cross-sectional view of a structure obtained during a manufacturing process of an interconnect substrate using an interconnect layer carrier structure according to an embodiment of the present invention.

[0029] Figure 5 is a schematic view of an interconnect layer carrier structure for transferring an interconnect layer onto a target substrate according to another embodiment of the present invention.

[0030] Figures 6A to 6D and Figures 7A to 7D is a cross-sectional view of a structure obtained during a manufacturing process of an organic base substrate according to an embodiment of the present invention.

[0031] Figure 8 is a cross-sectional view of an electronic device around an interconnect layer according to an embodiment of the present invention.

[0032] Figures 9A to 9C is a cross-sectional view of a structure obtained during a manufacturing process of an electronic device according to an embodiment of the present invention.

[0033] Figures 10A to 10F 、 Figures 11A to 11E 、 Figures 12A to 12D 、 Figures 13A to 13E 、 Figures 14A to 14D and Figures 15A to 15D is a cross-sectional view of a structure obtained during a manufacturing process of an interconnect layer carrier structure according to an embodiment of the present invention.

[0034] Figures 16A to 16D 、 Figures 17A to 17C 、 Figures 18A to 18D 、 Figures 19A to 19D 、and Figures 20A to 20C is a cross-sectional view of a structure obtained during a manufacturing process of an interconnect layer carrier structure according to another embodiment of the present invention.

[0035] Figure 21A and Figure 21B are respectively top views of an interconnect substrate without and with solder joints according to an embodiment of the present invention.

[0036] Figure 22A and Figure 22B is a top view of an interconnect substrate without solder joints according to other embodiments of the present invention. Detailed Embodiments

[0037] Hereinafter, the present invention will be described with reference to specific embodiments, but those skilled in the art should understand that the embodiments described below are only mentioned as examples and are not intended to limit the scope of the present invention.

[0038] One or more embodiments relate to an interconnect structure, an interconnect layer carrier structure for manufacturing the interconnect structure, a method of manufacturing the interconnect structure, and a method of manufacturing the interconnect layer carrier structure, wherein, in addition to high-density interconnects between a plurality of chips mounted on the interconnect structure, the interconnect structure provides a novel side connection between a substrate base and an interconnect layer provided thereon. When referring to Figures 1A to 22B describing embodiments, a plurality of identical elements may be identified by a common reference numeral, while each individual element among the plurality of identical elements may be identified by a separate index reference numeral appended to the common reference numeral. For example, Figure 1A the plurality of bonding pads shown in are commonly referred to by the reference numeral 112 and each individual bonding pad is referred to by the reference numerals 112-1 and 112-2.

[0039] Hereinafter, with reference to Figure 1A and Figure 1B , a schematic diagram of the interconnect structure before chip mounting is described.

[0040] Figure 1A and Figure 1B show schematic diagrams of an interconnect substrate 100 for interconnecting chips mounted thereon. The wiring substrate 100 is a wiring structure before chip mounting. Figure 1A and Figure 1B show a cross-sectional view and a top view of the interconnect substrate 100, respectively. It should be noted that the cross-sectional view shown in Figure 1A corresponds to the cross-section indicated by "X" in the top view of Figure 1B .

[0041] As shown in Figure 1A , the interconnect substrate 100 includes: an organic substrate base 110; a plurality of bonding pads 112 formed on the organic substrate base 110 for chip bonding; a conductive pad group 114 formed on the organic substrate base 110 for side connection; and an interconnect layer 130 provided on the organic substrate base 110.

[0042] The organic substrate 110 can be a build substrate having a core (e.g., a glass epoxy core) and an appropriate number of wiring layers (with interlayer dielectrics), and can be manufactured by any standard build process. The bonding pads 112 and the conductive pads 114 can be the outermost layers of the build substrate. Each bonding pad 112 is connected to a signal line via writing in the organic substrate 110. Each conductive pad 114 is connected to a power supply or a ground line via writing in the organic substrate 110, and the power supply or the ground line can be used as a signal return current path, which is the path that the current takes to return to the source. The bonding pads 112, the conductive pads 114, and the wiring are made of any one of metallic materials (e.g., Cu, Al, etc.) and other conductive materials. In a specific embodiment, metallic copper can be used. Note that, for illustrative purposes, the internal structure inside the organic substrate 110 is omitted from the drawings. It should also be noted that the organic substrate 110 serves as the substrate in the said embodiment. However, an inorganic substrate such as a glass substrate can also be used as the substrate.

[0043] In a specific embodiment, the interconnect substrate 100 further includes a solder mask layer 116 formed on the organic substrate 110. Each bonding pad 112 can be covered by the solder mask layer 116 and exposed from the solder mask layer 116 through an opening formed therein. Each bonding pad 112 can have a pre-solder 118 formed within the opening of the solder mask layer 116. Moreover, each conductive pad 114 can be partially covered by the solder mask layer 116 and exposed from the solder mask layer 116 at an edge close to an interconnect layer 130 disposed on the organic substrate 110. The thickness of the pads 112, 114 can generally be in the range of 1 to 20 microns. The thickness of the solder mask layer 116 can be within the range of its sufficient film thickness and can generally be in the range of 2 to 50 microns. Note that the solder mask layer, which is usually an organic material, serves as an insulating layer disposed on the organic substrate. However, instead of using the solder mask layer 116, a dielectric layer of an insulating material such as an inorganic insulating material other than the solder mask layer material can also be considered.

[0044] The plurality of bonding pads 112 can be divided into a plurality of groups. A group of bonding pads (hereinafter, referred to as the first group) 112-1 is positioned at a flip-chip region (referred to as the first flip-chip region) 110b-1 on the interconnect substrate 100. Other groups of bonding pads (hereinafter, referred to as the second group) 112-2 are located at different flip-chip regions (referred to as the second flip-chip region) 110b-2 on the interconnect substrate 100. The second group of bonding pads 112-2 can be located at a certain distance from the first group of bonding pads 112-1. It should be noted that Figure 1BThe pre-solders 118-1 and 118-2 formed on the bonding pads 112-1 and 112-2 are depicted in the top view. The first flip-chip region 110b-1 and the second flip-chip region 110b-2 are the regions where one chip (hereinafter referred to as the first chip) and another chip (hereinafter referred to as the second chip) will be installed after the subsequent chip mounting process, respectively.

[0045] The interconnect layer 130 is disposed on the top surface of the organic substrate 110 and is located within the defined region 110a between the first and second sets of bonding pads 112-1 and 112-2. The defined region 110a where the interconnect layer 130 is provided does not have a solder mask. By using appropriate alignment marks, the interconnect layer 130 can be accurately positioned at the defined region 110a and attached to the organic substrate 110. Note that the defined region 110a of the interconnect layer 130 partially overlaps both the first flip-chip region 110b-1 and the second flip-chip region 110b-2. In addition, the defined region 110a of the interconnect layer 130 can be recessed to adjust the levels of the top surface of the interconnect layer 130 and the top surface of the solder mask layer 116.

[0046] The interconnect layer 130 is bonded to the top surface of the organic substrate 110 by an adhesive 132. The adhesive 132 can use paste or liquid-type or film-type adhesive materials.

[0047] Further referring to Figure 1A The structure of the interconnect layer 130 is described in more detail. The interconnect layer 130 includes: an organic insulating material 134; a conductive pattern 136 embedded in the organic insulating material 134; and a plurality of pads 140-142 exposed at the top surface 130a of the interconnect layer 130, which can be provided by the organic insulating material 134. The pads 140-142 of the interconnect layer 130 are divided into two types. The first type is the side connection pads 140 for side connection, and the second type is the bonding pads 141 and 142 for chip bonding.

[0048] Note that in the described embodiment, the organic insulating material 134 serves as the insulating material of the interconnect layer 130. The organic material is preferred for the case of using the organic substrate 110 in order to mitigate the mismatch in the coefficient of thermal expansion (CTE) between the interconnect layer 130 and the organic substrate 110, which is commonly used as a packaging substrate. However, the insulating material is not limited to organic materials. In other embodiments, an inorganic insulating material can also be used as the insulating material.

[0049] In the described embodiment, as representative of the first flip chip region 110b-1, the interconnect layer 130 has edges E1 and E2 disposed on the organic substrate 110. Edge E1 is near the set of conductive pads 114-1, and edge E2 is near the set of conductive pads 114-2. This set of side connection pads 140-1 is located at and exposed at edge E1. Each side connection pad 140-1 is arranged relative to a corresponding one of the conductive pads 114-1 disposed on the organic substrate 110. When the set of conductive pads 114-1 is arranged in a row along one edge of the interconnect layer 130 at a predetermined interval (e.g., pitch width), the set of side connection pads 140-1 is also arranged in a row along edge E1 of the interconnect layer 130 at a predetermined interval (e.g., pitch width) that matches the interval of the conductive pads 114-1. Although not particularly limited, in a specific embodiment, the side connection pads 140-1 and the conductive pads 114-1 have a one-to-one relationship.

[0050] Each side connection pad 140 has a top surface TS exposed at the top surface 130a of the interconnect layer 130 and an edge surface ES exposed at one edge (e.g., E1) of the interconnect layer 130. The top surface TS is parallel to the top surface of the organic substrate 110, and the edge surface ES is perpendicular to the top surface of the organic substrate 110 and faces a corresponding one of the conductive pads 114. In a preferred embodiment, the edge surface ES and / or the top surface TS of each side connection pad 140 has a barrier metal layer. Examples of the barrier metal layer include Au / Pd / Ni stacks and Au / Ni stacks (where the first element (e.g., Au for both cases) is the top in the stack), Au layers, and Pd layers. Note that symbols such as Au, Pd, Ni, etc. represent the main elements contained in each layer of the stack, which may contain small amounts or trace amounts of other elements to form alloys and / or may also contain small amounts or trace amounts of additives due to the manufacturing process. It should also be noted that each of the bonding pads 112 and the conductive pads 114 disposed on the organic substrate 110 may or may not have a similar barrier metal layer.

[0051] As Figure 1A and Figure 1B shown, the interconnect substrate 100 may also include a set of solder joints 119, each solder joint connecting a side connection pad 140 of the interconnect layer 130 to a corresponding one of the conductive pads 114 disposed on the organic substrate 110. Each solder joint 119 contacts the exposed surfaces (top surface TS and edge surface ES) of the side connection pad 140 and the conductive pad 114. It should be noted that in Figure 1BThe top view also depicts solder joints 119-1 and 119-2 formed on conductive pads 114-1, 114-2 and side connection pads 140-1, 140-2. The symbol 'G' represents ground, and the symbol 'P' represents power supply.

[0052] In the described embodiment, the pads 112, 114 and the substrate have respective surfaces (the pad surfaces PS of the conductive pads 114 and the bonding pads 112 and the substrate surface SS around the conductive pads 114 and the bonding pads 112), and surface treatments for enhancing surface roughness are performed on these surfaces. In one or more embodiments, the surface treatment includes sandblasting and / or plasma treatment. Thus, the conductive pad 114 has a pad surface PS that is exposed from the substrate surface SS and is rougher than the exposed surface of an untreated pad. The bonding pad 112 also has a pad surface PS that is exposed from the substrate surface SS and is rougher than the exposed surface of an untreated pad. In addition, a portion of the substrate surface SS near the conductive pad 114 and the bonding pad 112 is rougher than other portions of the substrate surface.

[0053] It should be noted that the substrate surface SS is defined to include the surface of the organic base substrate 110 as the substrate body and the portion of the solder mask layer 116 formed on the substrate body. The substrate surface SS may at least partially include the upper surface of the solder mask layer 116, the upper surface of the organic base substrate 110 where there is no solder resist, the surface where there is no interconnect layer and no adhesive, and / or the surface of the adhesive 132.

[0054] The substrate surface SS can be provided by the organic materials of the solder mask layer 116, the organic base substrate 110 and / or the adhesive 132, and has low wettability for molten solder. The pad surface PS of each of the conductive pad 114 and the bonding pad 112 has high wettability for molten solder. In the context of the present invention, the term "low wettability" means that the surface has a contact angle greater than 90 degrees (90° < θ ≤ 180°), while the term "high wettability" means that the surface has a contact angle less than 90 degrees (0 < θ < 90°). The contact angle (θ) is the angle at which the liquid-air interface meets the solid-liquid interface, where the liquid is molten solder and the solid is the conductive material of the pads 112, 114 or the organic material of the substrate, and provides a reverse measurement of wettability.

[0055] In a specific embodiment, as long as the thickness of the solder mask layer after surface treatment is kept sufficiently constant, the roughness parameter (Ra) of the portion of the substrate surface SS after applying the surface treatment is greater than 0.4 μm and less than 2 μm, more preferably greater than 0.5 μm and less than 1 μm, where Ra represents the arithmetic mean roughness. In terms of another roughness parameter (Rq), the portion of the substrate surface SS may have a roughness parameter (Rq) greater than 700 nm and less than 4 μm, more preferably greater than 0.8 μm and less than 2 μm, where Rq represents the root mean square roughness. This also applies to the pad surface PS.

[0056] Further note that each of the pads 140, 141, 142 in the interconnect layer 130 may also have a pad surface exposed from the top surface 130a of the interconnect layer 130 and is rougher than the exposed surfaces of other untreated pads for which no surface enhancement treatment has been performed. In addition, the portion of the top surface 130a of the interconnect layer 130 near the pads 140, 141, 142 may be rougher than other portions of the surface of the interconnect layer 130 where no surface roughness enhancement treatment has been applied.

[0057] In the described embodiment, as is representatively described for the first flip-chip region 110b-1, the side connection pads 140-1, the conductive pads 114-1, and correspondingly the solder joints 119-1 are located within the flip-chip region 110b-1. This also applies to the other flip-chip regions 110b-2. However, the positions of the side connections (side connection pads 140, conductive pads 114, and solder joints 119) are not limited. In other embodiments, these side connections are placed at positions away from these flip-chip regions 110b because these side connections are not directly involved in the chip bonding.

[0058] Here, again focusing on the structure of the interconnect layer 130, the bonding pads 141, 142 are exposed from the organic insulating material 134 at the top surface 130a of the interconnect layer 130. The bonding pads 141, 142 of the interconnect layer 130 are used to mount the chips provided thereon together with the bonding pads 112 provided on the organic substrate 110. In the described embodiment, the bonding pads 141, 142 of the interconnect layer 130 are functionally divided into two types. The first type is the first bonding pad 141 for power or ground, and the second type is the second bonding pad 142 for signal transmission between chips.

[0059] Each first bonding pad 141 for power or ground is connected to the corresponding side connection pad 140 through a wiring (which is part of the conductive pattern 136) embedded in the organic insulating material 134, and the side connection pad 140 is further connected to the power line or ground line of the organic substrate 110 through the solder joint 119.

[0060] The bonding pads 141 and 142 of the interconnect layer 130 are also divided into multiple groups in terms of connection groups. One group of bonding pads (hereinafter referred to as the first group) 141-1 and 142-1 are located at the first flip-chip region 110b-1, and the other group of bonding pads (hereinafter referred to as the second group) 141-2 and 142-2 are located at the second flip-chip region 110b-2. Although not shown in Figure 1A , one of the bonding pads 142-1 in the first group is electrically connected to the corresponding bonding pad 142-2 in the second group through a wiring or trace (which is also part of the conductive pattern 136) embedded in the organic insulating material 134. Note that the conductive pattern 136 may include multiple conductive layers with one or more interlayers of organic insulating material, where parts of adjacent conductive layers are connected through conductive vias formed through the interlayers. The conductive pattern 136 also includes multiple circuit paths isolated by the organic insulating material.

[0061] In Figure 1A , it is described that the bonding pad 141-1 is connected to the side connection pad 140-1 located within the same flip-chip region 110b-1 and is not connected to the other side connection pad 140-2 located within a different flip-chip region 110b-2. However, since power and ground lines can be shared among multiple chips, the power or ground line for the first chip can be connected to the same line for the second chip.

[0062] To simplify the description of the implementation, Figure 1B shows four bonding pads 141 and 142, two solder heads 119 (two side connection pads 140 and two conductive pads 114), and two bonding pads 112 for the organic substrate 110 of each chip. However, the number of bonding pads, the number of solder joints (and thus the number of side connection pads and conductive pads), and the number of bonding pads for the organic substrate 110 of each chip are not limited and may depend on the specifications of the chip. The number of flip-chip regions is also not limited to two.

[0063] As described later, the first group of bonding pads 141-1 and 142-1 of the interconnect layer 130 and the first group of bonding pads 112-1 of the organic substrate 110 are formed into a two-dimensional array and are configured to receive the terminal bumps of the first chip. The same applies to other chips.

[0064] In the described embodiment, the interconnect layer 130 shown in FIG. 1 can be attached to the organic substrate 110 by using a novel interconnect layer carrier structure. Hereinafter, referring to Figure 2 , the interconnect layer carrier structure 120 for transferring the interconnect layer to a target substrate according to an exemplary embodiment of the present invention is described.

[0065] Figure 2 shows a schematic diagram of an interconnect layer carrier structure that can be used to transfer the interconnect layer 130 onto the organic substrate 110 to fabricate Figure 1A and Figure 1B the interconnect substrate 100 shown. Figure 2 The view shown in is a cross-sectional view of the interconnect layer carrier structure 120.

[0066] As Figure 2 shown, the interconnect layer carrier structure 120 includes a support substrate 122; a release layer 124 formed on the support substrate 122; and an interconnect layer portion 131 formed on the release layer 124. Figure 2 The interconnect layer portion 131 shown in corresponds to the interconnect layer 130 shown in FIG. 1 and is shown with its top and bottom surfaces inverted with respect to the Figure 1A view shown in.

[0067] The support substrate 122 is a rigid and stable substrate for fabricating the interconnect layer portion 131 thereon. The support substrate 122 can suitably be any substrate as long as it provides sufficient rigidity and stability. In one or more embodiments, the support substrate 122 can be an inorganic substrate, including glass, semiconductors such as silicon, ceramics, etc. In a preferred embodiment, the support substrate 122 is a glass substrate because the glass substrate has a transparency and a coefficient of thermal expansion (CTE) (3 - 12 ppm / degree Celsius) closer to that of the organic materials used to construct the interconnect layer portion 131 compared to, for example, a silicon substrate. Examples of such glass substrates can include soda-lime glass, borosilicate glass, fused silica, synthetic quartz glass, to name a few.

[0068] The release layer 124 is a release coating configured to release the interconnect layer portion 131 from the support substrate 122 by appropriate treatment. When the support substrate 122 is transparent, UV (ultraviolet) / IR (infrared) / visible light can be irradiated onto the release layer 124 from the back side of the support substrate 122 to release the interconnect layer portion 131 from the support substrate 122.

[0069] In one or more embodiments, the release layer 124 can be any known photosensitive release layer that allows debonding from the support substrate interface by laser irradiation in the field of wafer bonding / debonding techniques. In a specific embodiment, a photothermal conversion release coating that converts absorbed light energy into heat can be used as the release layer 124. In these specific embodiments, after the interconnect layer portion 131 is fixed to the organic substrate 110, the release layer 124 can be burned, damaged, or decomposed by using laser irradiation to ablate the release layer 124. In other embodiments, the release layer 124 can be a thermally or UV-releasable adhesive layer whose adhesive properties disappear or deteriorate due to thermal or UV radiation. If desired, the residue of the release layer 124 can be cleaned after release. In other embodiments, any known debonding method can be employed, including mechanical peeling methods, thermal slippage methods, and solvent release methods.

[0070] As referenced Figure 1A and Figure 1B described, the interconnect layer portion 131 includes an organic insulating material 134; a plurality of pads 140 - 142 facing the support substrate 122 and embedded in the organic insulating material 134; and the plurality of traces (or wirings) 136a–136d embedded in the organic insulating material 134.

[0071] Although Figure 2 not shown in, in a specific embodiment where a thin film adhesive is used for the adhesive 132 in FIG. 1, the interconnect layer portion 131 can further include an adhesive layer formed on top of the organic insulating material 134 and capable of completely covering the top surface of the organic insulating material 134.

[0072] The plurality of pads 140 - 142 includes side connection pads 140, a first bonding pad 141 for power or ground, and a second bonding pad 142 for signal transmission. As shown in FIG. 1, each side connection pad 140 is configured to be connected to a corresponding conductive pad 114 on the organic substrate 110 to which the interconnect layer portion 131 is transferred through a solder joint 119. The plurality of pads 140 - 142 are divided into multiple groups, including the first pad groups 140 - 1, 141 - 1, 142 - 1 and the second group of pads 140 - 2, 141 - 2, 142 - 2. Each pair of side connection pads 140 - 1 and the corresponding bonding pad 142 - 1 are electrically coupled through a trace 136a. Each pair of bonding pads 142 - 1 and the corresponding bonding pad 142 - 2 are electrically coupled through a trace ( Figure 2 not shown in for the trace connecting the bonding pads 142 - 1, 142 - 2).

[0073] The organic insulating material 134 may be disposed on the release layer 124. In the described embodiment, the top surface of the organic insulating material 134 may be a flat and exposed surface. In other embodiments, the top surface of the organic insulating material 134 may be covered by an adhesive layer. The pads 140-142 may be exposed from the organic insulating material 134 at the bottom surface and in contact with the release layer 124. In the described embodiment, each of the pads 140-142 includes a barrier metal layer 138 formed on the release layer 124. Each of the pads 140-142 may further include a seed metal layer, which may be used to deposit conductive materials (e.g., the barrier metal layer 138 and the pad body) on the bottom surface (corresponding to the top surface TS) of the release layer 124 on the release layer 124 by electroplating. In a preferred embodiment, each side connection pad 140 further includes a barrier metal layer 139 formed at its edge surface ES.

[0074] The organic insulating material 134 may be any of photosensitive insulating resins, such as PI (polyimide), BCB (benzocyclobutene), PBO (polyphenylene benzoxazole), or other photosensitive polymers. Using the organic insulating material alleviates the CTE mismatch between the interconnect layer 130 and the organic substrate 110. The conductive pattern 136 may be made of any of metal materials (e.g., Cu, Al, etc.) and other conductive materials. In a specific embodiment, metallic copper may be used for the conductive pattern 136. The barrier metal layers 138, 139 may be, but are not limited to, a stack of Au / Pd / Ni or a stack of Au / Ni, where the first element (e.g., Au for both cases) is Figure 2 the bottom Au layer or Pd layer in the stack in

[0075] In the described embodiment, the edges E1, E2 of the interconnect layer portion 131 are aligned with the edges GE1, GE2 of the support substrate 122. As Figure 2 shown, the interconnect layer portion 131 is arranged to be manufactured on the support substrate 122 in the form of a strip formed of an organic material and held by the support substrate 122 as a rigid support material. The process of manufacturing the interconnect layer carrier structure 120 will be described later.

[0076] Hereinafter, with reference to Figures 3A - 3C and Figures 4A - 4C , a method of manufacturing the interconnect substrate 100 by using the interconnect layer carrier structure 120 is described. Figures 3A - 3B and Figures 4A - 4C show cross-sectional views of the structures obtained during the manufacturing process of the interconnect substrate 100.

[0077] As Figure 3AAs shown, the manufacturing process of the interconnect substrate 100 may include the steps of providing an organic base substrate 110 and an interconnect layer carrier structure 120. The organic base 110 prepared by this step may include a plurality of bonding pads 112, a set of conductive pads 114, and a solder mask layer 116 disposed on the organic base 110. Note that there is a defined area 110a on the organic base substrate 110 that does not have a solder mask layer.

[0078] As Figure 3A shown, the manufacturing process may further include the step of applying an adhesive 132 to the organic base substrate 110 within the defined area 110a. In the described embodiment, when bonding a chip to a substrate, a paste or liquid type bonding material that can generally be used as an underfill is used for the adhesive 132. By using a paste or liquid adhesive, voids in the adhesive 132 can be prevented. However, in a specific embodiment where a thin film type adhesive material is formed on top of the interconnect layer portion 131, the step of applying the adhesive may be omitted.

[0079] As Figure 3B shown, the manufacturing process may include the following steps: placing the interconnect layer carrier structure 120 on the organic base substrate 110 such that the edges E1, E2 of the interconnect layer portion 131 are positioned adjacent to each set of conductive pads 114, and each side connection pad 140 is arranged relative to a corresponding one of the conductive pads 114 disposed on the organic base substrate 110. The interconnect layer carrier structure 120 may be placed on the organic base substrate 110 in an inverted manner by using a bonder such that the pads 140 - 142 face upward and the exposed surface of the organic insulating material 134 faces downward. The bottom of the organic insulating material 134 is attached to the top surface of the organic base substrate 110 within the defined area 110a.

[0080] Since the bonding pads 141, 142 of the interconnect layer portion 131 and the bonding pads 112 on the organic base substrate 110 are configured to receive the bumps of the chip to be mounted, the interconnect layer carrier structure 120 is accurately positioned at the defined area 110a by using appropriate alignment marks that can be pre - formed on the organic base substrate 110. The manufacturing process may further include the step of curing the adhesive 132 to firmly bond the interconnect layer portion 131 to the organic base substrate 110 after the step of placing the interconnect layer carrier structure 120 on the organic base substrate 110.

[0081] In other embodiments, the application of the adhesive 132 may be performed by capillary or injection flow methods after placing the interconnect layer carrier structure 120.

[0082] As Figure 3CAs shown, the manufacturing process may include the step of releasing the interconnect layer portion 131 from the support substrate 122 by removing the release layer 124. In a particular embodiment, the support substrate 122 has transparency, and the step of releasing from the support substrate 122 may be accomplished by irradiating and ablating the release layer 124 with a laser passing through the support substrate 122 while scanning a laser beam.

[0083] By performing the above steps, the interconnect layer portion 131 is transferred from the interconnect layer carrier structure 120 to the organic substrate 110 at the defined area 110a to obtain the interconnect layer 130 attached to the organic substrate 110. Figure 3C The release step shown leaves the interconnect layer 130 on the organic substrate 110 such that the set of pads 140 - 142 face in a direction opposite to the organic substrate 110.

[0084] As Figure 4A As shown, the manufacturing process may further include the step of cleaning the residue on top of the interconnect layer 130 after the step of removing the release layer 124, and the residue may include the residue of the release layer 124. Cleaning of the residue can be performed by almost any means, including O2 plasma irradiation. In a particular embodiment, the manufacturing process may further include the step of performing an etch on the surface of the pads 140 - 142 after the step of removing the release layer 124, which may include forming a seed metal layer on the pads 140 - 142 to expose the bare surface of the metal stack 138.

[0085] As Figure 4B As shown, the manufacturing process may include the step of applying a surface treatment to the exposed pad surfaces PS of the conductive pads 114 and the bonding pads 112 and a portion of the exposed substrate surface SS around the conductive pads 114 and the bonding pads to increase the surface roughness. Examples of such surface treatments for enhancing surface roughness include sandblasting (sandblasting process) and plasma treatment.

[0086] In a preferred embodiment, sandblasting is used as the surface treatment. Sandblasting can be performed by using a grinding medium with a suitable particle size under appropriate conditions such as the collision speed of the grinding medium, for example. There are many types, such as dry sandblasting and wet sandblasting. Wet sandblasting, which jets a grinding medium and a liquid such as water onto the workpiece, is preferred because wet sandblasting has the ability to use a finer grinding medium than dry sandblasting. Sandblasting is preferred because sandblasting mechanically and physically changes the exposed surface without significantly affecting the chemical surface conditions. In addition, by using an appropriate abrasive grain, the roughness of the exposed surface can be more precisely controlled within a wider control range.

[0087] In a specific embodiment, plasma treatment is used as a surface treatment. The plasma treatment can use argon (Ar) plasma, oxygen (O2) plasma, and mixtures thereof. Plasma treatment using Ar plasma is preferably used because Ar plasma has the ability to prevent oxidation. However, for example, in the case where pads 112 and 114 are protected by a noble metal layer (such as an Au layer formed on top), O2 plasma treatment can also be considered. The plasma treatment can be carried out under appropriate conditions, which can include RF (radio frequency) power, acceleration voltage, gas flow rate, application time, etc., such that sufficient enhancement of surface roughness is obtained.

[0088] Although plasma treatment is generally applied to a target surface to remove organic residues to clean the surface and / or to functionalize the surface in order to chemically change the surface properties, the plasma treatment according to the exemplary embodiments is different from the plasma treatment for cleaning and / or surface functionalization in terms of the target and conditions. Generally, in order to make the target surface rough enough, the duration of the plasma treatment is relatively long. In addition, the plasma treatment for enhancing surface roughness will physically roughen the surface, and the roughening effect lasts for a relatively long time. In contrast, the effectiveness of plasma treatment in terms of cleaning and / or surface functionalization is short because the cleaned surface will be contaminated over time and the surface conditions change over time, so the cleaning / functionalization effect decays over time. In addition, since plasma treatment, especially O2 plasma treatment, can make the resin surface more hydrophilic due to the interaction between active species and surface molecules, it is preferred to leave the exposed surface of the solder mask layer 116 for a period of time after the plasma treatment until the hydrophilicity sufficiently decays.

[0089] Enhancement of surface roughness improves the solder wettability of surfaces with high wettability, while improving the de-wettability of surfaces with low wettability. When the three-phase materials are the same, the wettability of molten solder depends on the surface roughness of the solid component. The wettability is represented by the contact angle in the Wenzel equation as follows:

[0090] cosθ w =r cosθ,

[0091] where, θ w represents the apparent contact angle, θ represents the Young's contact angle, and r represents the roughness ratio (r = 1 for a smooth surface and r > 1 for a rough surface).

[0092] When the surface irregularities are very fine such that air remains at the interface and forms a chemically non-uniform surface, the Cassie equation holds as follows:

[0093] cosθ′ c =f cosθ a+(1 - f)cosθ b ,

[0094] where f represents the area ratio of the contacting liquid phase to the solid phase, θa represents the contact angle of component A having a fractional surface area f, and θb represents the contact angle of component B having the remaining fractional surface area (1 - f). When the liquid contacts air (e.g., θb = 180 degrees), the Cassie equation is as follows:

[0095] cos θ′ c = fcosθ a + 1 - f.

[0096] Therefore, even if the interface between the solid and the liquid includes air, the contact angle θ c ' will increase. When f = 1 and the surface returns to uniformity, Wenzel's equation will hold.

[0097] The application of the surface treatment changes the different wetting characteristics of the exposed surface in the corresponding strengthening direction. The substrate surface SS with low wettability (90 degrees < θ < 180 degrees) becomes more non - wettable (θ w > θ). At the same time, the pad surface PS with high wettability (0 < θ < 90 degrees) becomes more wettable (θ w < θ). The enhancement of the surface roughness improves the solder wettability of the exposed pad surface PS of the pad 114 with high wettability, while improving the de - wettability of the substrate surface SS with low wettability. Therefore, adjacent side - connection bridging during soldering can be prevented, and the reliability of side - connection and chip bonding can be improved even when the spacing width between the side - connection and the bonding is very narrow.

[0098] After the step of releasing the interconnect layer portion 131 from the support substrate 122, a surface treatment for enhancing the surface roughness is performed. In this embodiment, the surfaces of the pads 140, 141, 142 (including the top surface TS (and possibly the edge surface ES) of the side - connection pad 140) and at least a part of the top surface 130a of the interconnect layer 130 near the pads 140, 141, 142 may also be surface - treated.

[0099] As Figure 4CAs shown, the manufacturing process may include the step of forming a set of solder joints 119 to connect the side connection pads 140 of the interconnect layer 130 to the corresponding conductive pads 114 disposed on the organic substrate 110, respectively. A set of pre-solders 118 may also be formed through this step. Each solder joint 119 may be formed by applying solder paste to the side connection pad 140 and the corresponding conductive pad 114 and heating to melt the solder paste to form a mechanical and electrical connection point. The paste may be applied by jet printing, stencil printing, or syringe. In an alternative embodiment, injection melt soldering (IMS) may be employed to form the solder joints 119. The IMS technique is advantageous when a larger volume of solder is preferred.

[0100] In the described embodiment, the step of heating the solder paste 117 to form the set of solder joints 119 is performed before chip mounting. This is suitable for cases where there is a delay until a later chip mounting process. Also, in the case where the subsequent chip mounting process does not use a reflow process, the formation of the solder joints 119 is preferably performed before chip mounting. However, in the case where the subsequent chip mounting process uses a reflow process, the step of heating the solder paste 117 at this stage may be omitted, and the completion of the solder joints 119 may be delayed until the reflow process of the subsequent chip mounting process.

[0101] By Figures 3A to 3C and Figures 4A to 4C The interconnect substrate 100 (including the organic substrate 110, the interconnect layer 130, a set of solder joints 119 formed on the side connection pads 140 of the interconnect layer 130, and the corresponding conductive pads 114 of the organic substrate 110) obtained by the manufacturing process shown in the series can be transferred to a subsequent process, such as a chip mounting process.

[0102] Figure 5 A schematic diagram of an interconnect layer carrier structure for transferring an interconnect layer onto a target substrate according to another embodiment of the present invention is shown. In the embodiment described with reference to Figure 2 the edges E1, E2 of the interconnect layer portion 131 are aligned with the edges GE1, GE2 of the support substrate 122. In contrast, in the specific embodiment shown in Figure 5 the interconnect layer portion 131 is formed within a predetermined area on the support substrate 122 such that the support substrate 122 has a base portion 122a for manufacturing the interconnect layer portion 131 and an extension portion (or eaves) 122b extending to the two edges outside the base portion 122a. The extension portion 122b is the portion of the support substrate 122 that hangs outside the edges E1, E2 of the interconnect layer portion 131 when inverted. In Figure 5In the illustrated embodiment, the edges E1 and E2 of the interconnect layer portion 131 are not aligned with the edges GE1 and GE2 of the support substrate 122. The extension portion 122b of the support substrate 122 has a flat surface that is configured to be substantially parallel to the flat surface of the organic substrate 110 by adjacency when transferring the interconnect layer 130 from the support substrate 122 onto the organic substrate 110.

[0103] In a particular embodiment, the organic substrate 110 has a solder mask layer 116 that has a flat surface for adjacency. When transferring the interconnect layer 130, the flat surface of the extension portion 122b of the support substrate 122 is configured to directly or indirectly abut the flat surface of the solder mask layer 116 of the organic substrate 110.

[0104] In a particular embodiment, the flat surface of the extension portion 122b is provided as the top surface 124a of the release layer 124. However, the release layer 124 need not extend to the region of the extension portion 122b of the support substrate 122. In other embodiments, when the support substrate 122 contacts the solder mask layer 116, the extension portion 122b of the support substrate 122 provides a direct flat surface that is configured to be substantially parallel to the flat surface of the solder mask layer 116.

[0105] Also in a particular embodiment, the solder mask layer 116 has a flat surface for abutment. However, in other embodiments, the height of the top surface of the interconnect layer 130 and the height of the top flat surface of the solder mask layer 116 can be adjusted by using a suitable spacer inserted between the extension portion 122a of the support substrate 122 and the solder mask layer 116 so as to have a suitable height difference.

[0106] In use Figure 5 In a specific embodiment of the interconnect layer carrier structure 120 shown, the step of placing the interconnect layer carrier structure 120 on the Figure 3B organic substrate 110 shown includes a sub-step of flattening the flat surface of the extension portion 122b by adjacency such that the flat surface of the extension portion 122b becomes substantially parallel to the top flat surface of the solder mask layer 116 of the organic substrate 110.

[0107] Hereinafter, with reference to Figures 6A - 6D , a method for manufacturing the organic substrate 110 is described. Figures 6A - 6D A cross-sectional view of a structure obtained during the manufacturing process of the organic substrate 110 is shown.

[0108] As Figure 6AAs shown, the manufacturing process may include the step of preparing an organic substrate 110 including a plurality of bonding pads 112 and a set of conductive pads 114. The bonding pads 112 and the conductive pads 114 may be made of metallic copper and formed by any construction process, including semi-additive process, additive process, subtractive process, etc. Although Figures 6A - 6D The process shown only shows the manufacturing process of the conductive pads 112, 114, but the organic base substrate consists of a core of a composite material such as glass epoxy resin, a general interconnect layer, and an insulating layer.

[0109] As Figure 6B shown, the manufacturing process may include the step of applying a photosensitive solder resist 115 onto the organic base substrate 110 including the area of the bonding pads 112 and the conductive pads 114. Such photosensitive resist is coated by any method, including, for example, spraying, dip coating, curtain coating, lamination, etc.

[0110] As Figure 6C shown, the manufacturing process may include the step of exposing and developing the photosensitive solder resist 115 using a mask 117 to obtain a structure with a patterned solder resist 116 as Figure 6D shown. Figure 6D The patterned solder resist 116 shown in has openings 116b on the bonding pads 112 and cavities 116a exposing the surface of the defined area 110a and the edges of the conductive pads 114 close to the defined area 110a. In Figure 6C the embodiment shown, the mask 117 is a dark field mask and the solder resist is positive. However, in other embodiments, a light field mask and a negative photosensitive resist material may also be employed.

[0111] Hereinafter, with reference to Figures 7A - 7D , an alternative method for manufacturing the organic base substrate 110 is described. Figures 7A - 7D shows a cross-sectional view of a structure obtained in an alternative manufacturing process of the organic base substrate.

[0112] As Figure 7A shown, the manufacturing process of the organic base substrate may include the step of providing an organic base substrate 110 including a plurality of bonding pads 112 and a set of conductive pads 114. As Figure 7B shown, the manufacturing process may include the step of applying a solder resist 115 onto the organic base substrate 110. As Figure 7C shown, the manufacturing process may include the step of processing the solder resist 115 by laser irradiation to obtain a structure with a patterned solder resist 116 as Figure 7D shown. The patterned solder resist 116 has openings 116b on the bonding pads 112 and cavities 116a exposing the defined area 110a and the edges of the conductive pads 114 close to the defined area 110a.

[0113] In the following, reference is made to Figure 8 for a schematic view of the interconnect structure after chip mounting.

[0114] Figure 8 A schematic view of an electronic device 190 is shown, which includes an interconnect substrate 100 as an insert and is the interconnect structure after chip mounting. Figure 8 An enlarged cross-sectional view of the electronic device 190 around the interconnect layer 130 is shown. As Figure 8 shown, there are two chips 150-1 and 150-2 mounted on the interconnect substrate 100. Examples of chips can include a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), an SoC (System on Chip), a memory device such as an HBM (High Bandwidth Memory), etc. The first chip 150-1 and the adjacent second chip 150-2 can be used for mutual signal transmission through the interconnect layer 130 located between the first chip 150-1 and the second chip 150-2. In the described embodiment, the chip 150 is connected to a power line or a ground line of the organic base substrate 110 through a via in the interconnect layer 130, and the power or ground line serves as a signal return current path.

[0115] As Figure 8 shown, the electronic device 190 includes: the above-mentioned interconnect substrate 100; and the first chip 150-1 and the second chip 150-2 mounted on the interconnect substrate 100, with the active surfaces of the first chip 150-1 and the second chip 150-2 facing down. Each chip 150 can be located at a position corresponding to the flip-chip region 110b on the interconnect substrate 100. The gap between the interconnect substrate 100 and the chip 150 can be filled with an underfill 168, and the underfill 168 can be made of epoxy resin or urethane.

[0116] The first set of bonding pads 112-1 and the first sets of bonding pads 141-1, 142-1 are positioned within a first flip-chip region 110b-1 where the first chip 150-1 is mounted. The first chip 150-1 has a set of terminal bumps 151-1, 152-1 that are electrically connected to the first sets of pads 141-1, 142-1 of the interconnect layer 130 through solders 156-1, 157-1. The first chip 150-1 also has a set of other terminals 154-1 that are electrically connected to the first set of bonding pads 112-1 on the organic substrate board 110 through solder 158-1. The terminal bumps 151-1, 152-1, 154-1 can be, but are not limited to, Cu pillar-type bumps. The terminal bump 151-1 can be a power or ground terminal configured to be connected to a power supply or ground wire that can be used as a signal return current path. More specifically, the terminal bump 151 is connected to the bonding pad 141, which is connected to the corresponding side connection pad 140 via wiring embedded in the organic insulating material 134, and the side connection pad 140 is further connected to the power supply line or ground wire of the organic substrate board 110 through the solder joint 119. The same applies to the second flip-chip region 110b-2 and the second chip 150-2.

[0117] Although Figure 8 not shown in the figure, the interconnect substrate 100 on which multiple chips 150 are mounted constitutes an electronic package, which may have bumps formed at the bottom of the interconnect substrate 100 and is further mounted on the motherboard through package interconnection between the bumps of the interconnect substrate 100 and the pads formed on the motherboard. The final assembled product including the interconnect substrate 100, the chips 150, and the motherboard can also be one of the electronic devices and is also the interconnect structure after chip mounting.

[0118] Multiple chips 150 can communicate with each other through the interconnect layer 130, while the chips 150 are connected to the motherboard through the internal structure of the organic substrate board 110. Further according to the described embodiments, the power supply line and ground wire to the chips 150 can be routed through the side connection implemented by the solder joints 119 through the interconnect layer 130. Compared with the case of routing wiring on the organic substrate board, it allows suppressing the voltage drop while avoiding the area of the interconnect layer. Using the interconnect layer to provide a power supply or ground wire serving as a signal return current path is beneficial for high-speed signal transmission.

[0119] The interconnect structure allows a new type of side connection between the conductive pads 114 of the organic substrate board 110 and the side connection pads 140 of the interconnect layer 130. Introducing the new type of side connection improves the flexibility of wiring and the wiring of the interconnect layer 130. In addition, it relaxes the restrictions on the terminal layout of the chips 150 using the interconnect layer 130. This interconnect structure is suitable for heterogeneous integration.

[0120] Although Figure 8Only two chips and one interconnect layer 130 through which the two chips communicate are shown. However, the number of chips in the electronic device, the number of chips in each interconnect layer, and the number of interconnect layers are not limited.

[0121] Reference Figures 9A to 9C , describes the manufacturing process of electronic devices that is subsequently performed after the manufacturing process of the interconnect. Figures 9A to 9C Shows a cross-sectional view of the structure obtained during the manufacturing process of the electronic device 190.

[0122] As Figure 9A shown, the manufacturing process of the electronic device may include the step of mounting a plurality of chips 150 onto the interconnect substrate 100 with their active surfaces facing down. The first chip 150-1 may be located at the positions where the first set of bonding pads 112 of the interconnect layer 130 and the first set of pads 141-1, 141-2 are located. The same applies to the second chip 150-2.

[0123] The chips 150 prepared for this step may include terminal bumps 151, 152, 154, and each terminal bump may be composed of pillars 161, 162, or 164 and solder caps 166, 167, or 168 formed thereon. In the described embodiment, the terminal bumps 151, 152, 154 are Cu pillar bumps. However, in other embodiments, the terminal bumps 151, 152, 154 may be any one of, for example, flip-chip bumps, fine pitch, micro bumps, Cu pillar bumps, Cu pillar bumps with Sn caps (SLID), etc. In the described embodiment, there is no solder on the bonding pads 141, 142 of the interconnect substrate 100 prepared for this step, because each bonding pad 141, 142 has a barrier metal layer 138 on top, which improves wettability. However, applying solder to the bonding pads 141, 142 before chip mounting is not precluded.

[0124] As Figure 9B shown, the manufacturing process may include the following steps: forming solder interconnections 156, 157, 158 between the bonding pads 112 and the bonding pads 141, 142 and the pillars 161, 162, 164 through a solder reflow process.

[0125] By performing Figure 9A and Figure 9B the steps shown, the chip 150 is mounted on the interconnect substrate 100 such that the chip 150 has a terminal bump 151 that is joined to the bonding pad 141 through a solder joint 119 and is electrically connected to a conductive pad 114 provided on the organic base substrate 110 through a side connection pad 140.

[0126] As Figure 9CAs shown, the manufacturing process may include the following steps: dispensing underfill 168 through a capillary flow underfill process to fill the gap between the interconnect substrate 100 and the chip 150, and then curing to fix the first chip 150-1 and the second chip 150-2 to the interconnect substrate 100.

[0127] In the described embodiment, the underfill 168 is described as being applied to the organic base substrate 110 after the organic base substrate 110 has undergone a reflow process. However, in other embodiments, a no-flow underfill may be first dispensed on the interconnect substrate 100. Then, the chip 150 is placed on the interconnect substrate 100 on which the underfill has been dispensed. Finally, the formation of the solder interconnects 156, 157, 158 and the curing of the underfill are performed simultaneously through a reflow process. In the described embodiment, the solder reflow process is used as the bonding process. However, in other embodiments, instead of the solder reflow process, a thermocompression (TC) bonding process may also be contemplated.

[0128] Hereinafter, with reference to a series of Figures 10A - 10F 、 Figures 11A - 11E 、 Figure 12A – Figure 12D 、 Figures 13A - 13E 、 Figure 14A – Figure 14D and Figure 15A – Figure 15D ,a process for manufacturing an interconnect layer carrier structure is described, which can be used to transfer the interconnect layer to an organic base substrate. Figure 10A –10F, Figure 11A –11E, Figure 12A –12D, Figure 13A –13E, Figure 14A –14D and Figure 15A –15D show cross-sectional views of the structures obtained during the manufacturing process of the interconnect layer carrier structure 120.

[0129] As Figure 10A shown, the manufacturing process of the interconnect layer carrier structure 120 may include the step of preparing a support substrate 200. In the described embodiment, the support substrate 200 prepared through this step is a glass wafer or panel, and the following process is described assuming a laser debonding process. However, in the case of a mechanical or thermal debonding process, other substrates such as silicon wafers may be used as the support substrate 200. For example, the thickness of the support substrate 200 may be in the range of several hundred micrometers to several millimeters.

[0130] As Figure 10BAs shown, the manufacturing process may include the step of applying a release layer 202 on a support substrate 200. The release layer 202 can be formed by almost any means, including, for example, spin coating. In one embodiment, for example, the thickness of the release layer 202 can be about or less than 1 micron. After the formation of the release layer 202 is completed, an interconnect layer portion is constructed on the release layer 202 by the steps described below.

[0131] As Figure 10C shown, the manufacturing process may include the step of forming a first seed metal layer 204 on the release layer 202. The first seed metal layer 204 can be formed by almost any means including sputtering. In a particular embodiment, a stack of a titanium layer and a copper layer (Ti / Cu, where Ti is the bottom in the stack) is formed on the release layer 202 by sputtering to form the first seed metal layer 204. In one embodiment, the titanium layer can have a thickness of several tens of nanometers and the copper layer can have a thickness of several hundreds of nanometers. This also applies to other seed layers to be described below.

[0132] As Figure 10D shown, the manufacturing process may include the step of depositing an electroplating resist 206 onto the first seed metal layer 204. In a specific embodiment, the electroplating resist 206 can be made of any of the photosensitive resins. The thickness of the electroplating resist 206 can be in the range of 10 microns to 50 microns. The electroplating resist 206 can be formed by practically any means, including, for example, spin coating. In addition to the liquid-type resist, a film-type resist can also be used. In the case of the film-type resist, the electroplating resist 206 is made by a lamination process. This also applies to other electroplating resists to be described below.

[0133] As Figure 10E shown, the manufacturing process may include the step of making a plurality of openings 206a in the electroplating resist 206. The openings 206a correspond to Figure 2 the pads 140, 141, 142 shown. The openings 206a can be made by practically any means, including, for example, photolithography. In a specific embodiment, the photosensitive resin deposited by spin coating is exposed through a photomask 208 and developed to form the openings 206a in the electroplating resist 206. Note that, in terms of patterning, a specific type of resist or photosensitive resin is used to describe the manufacturing process. For example, Figure 10E shows the case of using a positive-type resist. However, the type of resist or photosensitive resin is not limited to the specific type shown in the figure. Positive-type and negative-type resists or photosensitive resins can also be used. This also applies to other resists and photosensitive resins to be described below.

[0134] As Figure 10FAs shown, the manufacturing process may further include the step of forming a barrier metal layer 210 on the first seed metal layer 204 at the position of the opening 206a of the electroplating resist 206. In a particular embodiment, the barrier metal layer 210 is an Au / Pd / Ni metal stack, which may include a gold layer on the first seed metal layer 204, a palladium layer on the gold layer, and a nickel layer on the palladium layer. When the resulting interconnect layer 130 is transferred onto the organic substrate 110 during the manufacturing process of the interconnect substrate 100, the gold layer becomes the top layer. The barrier metal layer 210 may be formed on the first seed metal layer 204 by virtually any metallization process, which may include, for example, electroplating.

[0135] As Figure 11A shown, the manufacturing process may include the step of depositing a first conductive layer 212 on the barrier metal layer 210. The first conductive layer 212 may be formed by virtually any means, including, for example, electroplating. In a particular embodiment, metallic copper is deposited by electroplating to form the first conductive layer 212. This also applies to the other conductive layers to be described below.

[0136] As Figure 11B shown, the manufacturing process may include the step of removing the electroplating resist 206 from the first seed metal layer 204. As Figure 11C shown, the manufacturing process may include the step of removing the exposed portion of the first seed metal layer 204 from the metal stacks 210, 212.

[0137] By performing Figure 10C –10F and Figure 11A –11C shown in the steps, the conductive material is patterned to form a set of side connection pads 140 and bonding pads 141, 142 formed on the release layer 202.

[0138] As Figure 11D shown, the manufacturing process may include the step of forming a first organic insulating portion 214 on the release layer 202 to embed a set of pads 140, 141, 142 (including the first seed metal layer 204, the barrier metal layer 210, and the first conductive layer 212). In a specific embodiment, the first organic insulating portion 214 is made of any of the photosensitive insulating resins. The thickness of the first organic insulating portion 214 may range from a few micrometers to dozens of micrometers. The first organic insulating portion 214 may be formed by virtually any means, including, for example, spin coating. In addition to the liquid-type resin, a film-type resin may also be used. In the case of the film-type resin, the first organic insulating portion 214 is made by a lamination process. This also applies to the other organic insulating portions to be described below.

[0139] As Figure 11EAs shown, the manufacturing process may include the steps of exposing and developing the first organic insulating portion 214 to have a plurality of via openings 214a at the positions of the pads 140, 141, 142. The via openings 214a can be formed by virtually any means, including, for example, photolithography. In a specific embodiment, a photosensitive insulating resin deposited by spin coating is exposed through a photomask 216 and developed to form the via openings 214a. Figure 11E The case of using a negative resist is shown.

[0140] As Figure 12A shown, the manufacturing process may include the step of forming a second seed metal layer 218 on the top surface of the first organic insulating portion 214 and on the exposed surfaces of the first conductive layer 212 in the via openings 214a.

[0141] As Figure 12B shown, the manufacturing process may include the step of depositing an electroplating resist 220 on the second seed metal layer 218. As Figure 12C shown, the manufacturing process may include the step of patterning an opening pattern 220a in the electroplating resist 220 using a photomask 222. The opening pattern 220a includes a wiring or trace pattern for connecting to the pad 142. The opening pattern 214a can be formed by virtually any means, including, for example, photolithography. Figure 12C The case of using a positive resist is shown.

[0142] As Figure 12D shown, the manufacturing process may include the step of depositing a second conductive layer 224 on the regions of the second seed metal layer 218 that do not have the electroplating resist. As Figure 13A shown, the manufacturing process may include the step of removing the electroplating resist 220 from the second seed metal layer 218. As Figure 13B shown, the manufacturing process may include the step of removing the portions of the second seed metal layer 218 that are exposed from the second conductive layer 224.

[0143] By performing Figure 11E , Figure 12A – Figure 12D and Figure 13A – Figure 13B shown steps, the conductive material is patterned to form a trace for connecting the bonding pad 142 and the corresponding bonding pad.

[0144] As Figure 13C shown, the manufacturing process may include the step of depositing a second organic insulating layer 226 on the first organic insulating portion 214 to embed the second conductive layer 224. As Figure 13DAs shown, the manufacturing process may include the steps of exposing and developing the second organic insulating layer 226 to have a plurality of via openings 226a at the positions of the pads 140 and 141. Since the bonding pad 142 is isolated from the pads 140 and 141, no opening is formed at the position of the pad 142. Figure 13D The case of using a negative resist is shown.

[0145] As Figure 13E shown, the manufacturing process may include the step of forming a third seed metal layer 230 on the top surface of the second organic insulating layer 226 and the exposed surface of the second conductive layer 224 in the via openings 226a.

[0146] As Figure 14A shown, the manufacturing process may include the step of patterning an electroplating resist 232 on the third seed metal layer 230 by using a photomask 234. The electroplating resist 232 has an opening pattern 232a, and the opening pattern 232a includes a wiring or trace pattern for the pads 140 and 141. Figure 14A The case of using a positive resist is shown.

[0147] As Figure 14B shown, the manufacturing process may include the step of depositing a third conductive layer 236 on the area of the third seed metal layer 230 without the electroplating resist. As Figure 14C shown, the manufacturing process may include the step of removing the electroplating resist 232 from the third seed metal layer 230. As Figure 14D shown, the manufacturing process may include the step of removing the portion of the third seed metal layer 230 exposed from the third conductive layer 236.

[0148] By performing Figure 13C –13E and Figure 14A –14D, the conductive material is patterned to form wirings for connecting the side connection pads 140 and the corresponding bonding pads 141.

[0149] As Figure 15A shown, the manufacturing process may include the step of depositing a third organic insulating layer 238 on the second organic insulating layer 226 to embed the third conductive layer 236. As Figure 15B shown, the manufacturing process may include the steps of exposing and developing the third organic insulating layer 238 by using a photomask 240.

[0150] As Figure 15C shown, the manufacturing process may further include the step of cutting the support substrate 200 together with its upper structure (including the release layer 202) by using a cutting blade to obtain Figure 15D shown, the individual structure, which is substantially the same as the Figure 2 shown interconnect layer carrier structure 120. The cutting line (Figure 15C The dashed line (in ) corresponds to an edge E of the interconnect layer carrier structure 120 and the position where it is divided by the metal stack corresponding to the side connection pads 140. The cutting support substrate 200 completes the fabrication of this set of side connection pads 140.

[0151] Since the profile of the interconnect layer portion 131 is defined by the cutting process, the edge of the interconnect layer portion 131 has a straight shape, and a set of side connection pads 140 are formed in a row. Accordingly, a set of conductive pads 114 as counterparts are also formed in a row.

[0152] Note that the manufacturing process may further include the step of forming a barrier metal layer on the edge surface ES of the side connection pads 140 by virtually any metallization process, which may include, for example, electroless plating. In a particular embodiment employing electroless plating, the exposed edge surface ES of the side connection pads 140 is selectively electroplated to form a barrier metal layer on the edge surface ES of the side connection pads 140. The formation of the barrier metal layer is preferably carried out before the interconnect layer portion 131 is attached to the organic substrate, so as to avoid the occurrence of voids due to the pad size difference between the interconnect layer portion 131 and the organic substrate 110. Although there are differences in the composition and additives of the barrier metal layer between the top surface TS and the edge surface ES, in terms of the combination of metal materials, the barrier metal layer on the edge surface ES is preferably the same as the barrier metal layer on the top surface TS, so as to make the diffusion rate of solder elements uniform, which will mitigate the local formation of alloys and stress concentration. For example, when the barrier metal used for the top surface TS is a Ni / Au stack, a Ni / Au stack is preferably employed for the edge surface ES.

[0153] The interconnect layer carrier structure 120 obtained by this process can be passed on to subsequent processes, such as the interconnect substrate fabrication shown in the series of Figures 3A - 3C and Figures 4A - 4C In one embodiment, as shown in Figure 15D , the interconnect layer carrier structure 120 divided by cutting from a glass wafer or panel can be provided to the next in the production chain. The interconnect layer portion 131 is provided in the form of a strip formed of an organic material and held by a support substrate 122 as a rigid backing material.

[0154] The interconnect layer carrier structure 120 obtained through this process may have two conductive layers (in addition to the pad body), and these two conductive layers have an intermediate layer of organic insulating material. However, the number of conductive layers is not limited. By repeatedly performing the following series of steps: (i) depositing an organic insulating layer, (ii) exposing and developing the organic insulating layer, (iii) forming a seed layer, (iv) depositing an electroplating resist, (v) exposing and developing the electroplating resist, (vi) depositing a conductive layer, (vii) removing the electroplating resist, and (viii) removing the seed layer, each conductive layer is stacked in a one-to-one manner with the intermediate layer of the organic insulating material.

[0155] The above manufacturing process of the interconnect layer carrier structure 120 is cost-effective and allows us to increase the number of interconnect layer carrier structures cut from a single wafer or panel.

[0156] Hereinafter, with further reference to Figure 16A –16D, Figure 17A –17C, Figure 18A –18D, Figure 19A –19D, and Figure 20A –20C, as well as Figures 10A - 10F and Figure 11A –11D, alternative processes for manufacturing the interconnect layer carrier structure are described. Figures 10A - 10F , Figures 11A - 11D , Figures 16A - 16D , Figures 17A - 17C , Figures 18A - 18D , Figures 19A - 19D and Figures 20A - 20C show cross-sectional views of the structures obtained during an alternative manufacturing process of the interconnect layer carrier structure 120.

[0157] Since the steps shown in a series of Figures 10A - 10F and Figures 11A - 11D are the same as those in the above exemplary embodiment, hereinafter, the description will start from Figure 16A the steps. By performing Figures 10A - 10F and Figures 11A - 11D the steps, a structure is provided, including: a support substrate 200; a release layer 202 formed on the support substrate 200; a set of pads 140, 141, 142 (including a first seed metal layer 204, a barrier metal layer 210, and a first conductive layer 212) formed on the release layer 202; and a first organic insulating portion 214 formed on the release layer 202 but not yet exposed and developed.

[0158] As Figure 16AAs shown, the manufacturing process may include the following steps: exposing and developing the first organic insulating portion 214 so as to have a plurality of via openings 214a at the positions of the pads 140, 141, 142 and exposing one edge of the side connection pad 140, as Figure 16A shown by the opening space 214b in Figure 16A . A case of using a negative resist is shown.

[0159] As Figure 16B shown, the manufacturing process may include the step of forming a second seed metal layer 218 on the top surface of the first organic insulating portion 214, the exposed surface of the first conductive layer 212 in the via openings 214a and the opening space 214b, and the exposed surface of the release layer 202 in the opening space 214b.

[0160] As Figure 16C shown, the manufacturing process may include the step of depositing an electroplating resist 220 onto the second seed metal layer 218. As Figure 16D shown, the manufacturing process may include the step of patterning an opening pattern 220a into the electroplating resist 220. As Figure 17A shown, the manufacturing process may include the step of depositing a second conductive layer 224 on the region of the second seed metal layer 218 where there is no electroplating resist. As Figure 17B shown, the manufacturing process may include the step of removing the electroplating resist 220 from the second seed metal layer 218. As Figure 17C shown, the manufacturing process may include the step of removing the portion of the second seed metal layer 218 that is exposed from the second conductive layer 224.

[0161] As Figure 18A shown, the manufacturing process may include the step of depositing a second organic insulating layer 226 on the first organic insulating portion 214 to embed the second conductive layer 224. As Figure 18B shown, the manufacturing process may include the following steps: exposing and developing the second organic insulating layer 226 by using a photomask 228 so as to have a plurality of via openings 226a at the position of the pad 140 and exposing one edge of the side connection pad 140, as Figure 18B shown by the opening space 226b in Figure 18B . A case of using a negative resist is shown.

[0162] As Figure 18C shown, the manufacturing process may include the step of forming a third seed metal layer 230 on the top surface of the second organic insulating layer 226, the exposed surface of the second conductive layer 224 in the via openings 226a and the opening space 226b, and the exposed surface of the release layer 202 in the opening space 226b.

[0163] As Figure 18DAs shown, the manufacturing process may include the step of patterning an electroplating resist 232 on a third seed metal layer 230 by using a photomask 234. The electroplating resist 232 has an opening pattern 232a including a wire pattern for pads 140, 141. Figure 18D The case of using a positive resist is shown.

[0164] As Figure 19A shown, the manufacturing process may include the step of depositing a third conductive layer 236 on the region of the third seed metal layer 230 where there is no electroplating resist. As Figure 19B shown, the manufacturing process may include the step of removing the electroplating resist 232 from the third seed metal layer 230. As Figure 19C shown, the manufacturing process may include the step of removing the exposed portion of the third seed metal layer 230 from the third conductive layer 236.

[0165] As Figure 19D shown, the manufacturing process may include the step of depositing a third organic insulating layer 238 on the second organic insulating layer 226 to embed the third conductive layer 236. As Figure 20A shown, the manufacturing process may include the step of exposing and developing the third organic insulating layer 238 by using a photomask 240 to expose the edge of the side connection pad 140.

[0166] The first organic insulating portion 214, the second organic insulating layer 226, and the third organic insulating layer 238 are patterned to form the profile shape of the interconnect layer portion 131, while at least exposing the edge surface ES of each side connection pad 140 from the organic insulating layers 214, 226, 238.

[0167] Note that the manufacturing process may further include the step of forming a barrier metal layer on the edge surface ES of the side connection pad 140 by virtually any metallization process, which may include, for example, electroless plating. Forming the barrier metal layer on the edge surface ES can be performed at any stage after forming the side connection pad 140 and exposing the end face ES of the side connection pad 140. Therefore, the formation of the barrier metal layer can be performed after the subsequent step of cutting the support substrate 200.

[0168] As Figure 20B shown, the manufacturing process may further include the step of cutting the support substrate 200 having a release layer 202 to obtain Figure 20C shown, a separate structure, which is substantially the same as the Figure 5 interconnect layer carrier structure 120 shown. The cutting line is located at a position away from an edge E of the interconnect layer portion 131 and the set of side connection pads 140.

[0169] Since the outline of the interconnect layer portion 131 is defined by lithography, the edges of the interconnect layer portion 131 can have any suitable shape. This alternative manufacturing process is also advantageous for controlling the height of the top surface 130a of the interconnect layer 130 because extensions (or eaves) 122b extending to the two edges outside the substrate portion 122a can be easily fabricated. Even when the density of the interconnects becomes higher and the pitch between the pads becomes narrower, this improves the yield and reliability of the interconnects between the terminal bumps 151, 152, 154 and the bonding pads 141, 142, 112.

[0170] In a specific embodiment, the organic insulating layers 214, 226, 238 are patterned such that the edge E of the interconnect layer portion 131 has a straight shape and the set of side connection pads 140 are formed in a row, and correspondingly the set of corresponding conductive pads 114 are also formed in a row.

[0171] In a preferred embodiment, the organic insulating layers 214, 226, 238 are patterned such that the edge E of the interconnect layer portion 131 has one or more curved or angled shapes to extend the length of the edge E, and the set of side connection pads 140 are formed along the contour of the one or more curved or angled shapes. Correspondingly, the set of conductive pads 114 are also formed along the contour of the one or more curved or angled shapes.

[0172] Reference Figure 21A and 21B , a schematic diagram of the interconnect substrate 100A is described. Figure 21A A top view of the interconnect substrate 100A without solder joints is shown. Figure 21B A top view of the interconnect substrate 100A with solder joints is shown. As Figure 21A and 21B shown, the edge E of the interconnect layer 130 has one or more angled shapes similar to a square wave form. The set of side connection pads 140 are arranged along the contour of the similar square wave form. In addition, correspondingly, the edge of the solder resist layer 116 adjacent to the interconnect layer 130 also has one or more angled shapes such as a square wave form. The set of conductive pads 112 are also arranged along the contour of the similar square wave form. Since the length of the edge E is extended by an amount of curvature compared to the case where the edge E has a straight shape, the density of the side connections can be increased.

[0173] Referring to Figure 22A , a schematic diagram of the interconnect substrate 100B is described. Figure 22A A top view of the interconnect substrate 100B without solder joints is shown. As Figure 22A shown, the edge E of the interconnect layer 130 has one or more angled shapes similar to a square wave form to extend the length of the edge E, as compared with Figure 21A , Figure 21BThe illustrated embodiments are similar. The side connection pads 140 are formed along the contour of the similar square wave form. Correspondingly, the conductive pads 112 are also formed along the contour of the similar square wave form.

[0174] Reference Figure 22B , a schematic diagram of the wiring substrate 100C is described. Figure 22B A top view of the interconnect substrate 100C without solder joints is shown. As Figure 22B shown, the edge E of the interconnect layer 130 has one or more curved shapes. The side connection pads 140 are formed along the contour of these curved shapes. The conductive pads 112 are also formed along the contour of these curved shapes.

[0175] In the wiring substrates 100B and 100C, since the length of the edge E is extended by the amount of bending, it is possible to increase the contact area of each side connection without increasing the density of the side connections.

[0176] The interconnect structure according to one or more embodiments of the present invention allows us to introduce a new type of side connection between the conductive pads 114 of the organic base substrate 110 and the side connection pads 140 of the interconnect layer 130. Introducing the new type of side connection improves the flexibility of the wiring and the wiring of the interconnect layer 130. Therefore, since the wiring can be optimized according to the improved wiring flexibility, the performance of the electronic device using the interconnect structure can be improved. In addition, it relaxes the restrictions on the terminal layout of the chips using the interconnect layer 130.

[0177] The terms used herein are for the purpose of describing particular embodiments only and are not intended to limit the present invention. As used herein, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include the plural forms as well. It will be further understood that when the terms "comprises" and / or "comprising" are used in this specification, they specify the presence of the stated features, steps, layers, elements and / or components, but do not preclude the presence or addition of one or more other features, steps, layers, elements, components and / or combinations thereof.

[0178] All apparatus or steps in the following claims, plus the corresponding structures, materials, acts and equivalents of the functional elements (if any), are intended to include any structure, material or act for performing the stated function in combination with other claimed elements as specifically claimed. The description of one or more aspects of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the form disclosed.

[0179] Without departing from the scope of the described embodiments, many modifications and variations will be apparent to those of ordinary skill in the art. The terms used herein are chosen to best explain the principles of the embodiments, the practical application, or the technical improvements made to the technology found in the marketplace, or to enable those of ordinary skill in the art to understand the embodiments disclosed herein.

[0180] In a preferred embodiment of the invention described herein, an interconnect layer carrier structure is provided, comprising: a support substrate; a release layer formed on the support substrate; and an interconnect layer portion disposed on the release layer and having an edge, the interconnect layer portion comprising an insulating material and a side connection pad group embedded in the insulating material, the side connection pad group being located at the edge of the interconnect layer portion and exposed, and formed at a predetermined interval along the edge of the interconnect layer portion. Each side connection pad preferably has a bottom surface exposed at the bottom surface of the interconnect layer portion and an edge surface exposed at the edge of the interconnect layer portion. The insulating material preferably forms the bottom surface of the interconnect layer portion, and the interconnect layer portion further comprises a first bonding pad group exposed through the insulating material at the bottom surface of the interconnect layer portion for mounting a chip, and each first bonding pad in the bonding pad group is connected to a corresponding one of the side connection pads via a wiring embedded in the insulating material. Each side connection pad can be configured to be connected to a corresponding conductive pad provided on a base substrate by a soldering head for receiving the interconnect layer portion transferred thereto.

[0181] In a preferred embodiment of the present invention described herein, a method for manufacturing an interconnect layer carrier structure is provided, the method comprising: preparing a support substrate; applying a release layer on the support substrate; and constructing an interconnect layer portion on the release layer, the interconnect layer portion having an edge and comprising: an insulating material; and a set of side connection pads embedded in the insulating material, the set of side connection pads being located at and exposed at the edge of the interconnect layer portion and formed at a predetermined interval along the edge of the interconnect layer portion. The constructing of the interconnect layer portion preferably comprises: patterning a conductive material to provide a set of side connection pads on the release layer; and forming an insulating portion on the release layer to embed the set of side connection pads. Constructing the interconnect layer portion may include: forming a first set of bonding pads on the release layer; patterning wiring configured to connect each side connection pad in the set of side connection pads to a corresponding bonding pad in the first set of bonding pads; and forming a second insulating member for embedding the wiring. Constructing the interconnect layer portion may further include: forming a second bonding pad and a third bonding pad on the release layer; patterning a trace for connecting the second bonding pad and the third bonding pad; and forming a third insulating portion for embedding the trace. The method may further include: cutting the support substrate and the structures on the support substrate by patterning the conductive material to complete the interconnect layer portion and the set of side connection pads. The insulating portion may be patterned so as to expose at least an edge surface of each side connection pad from the insulating portion, and the method further includes: cutting the support substrate at a position remote from the set of side connection pads.

Claims

1. An interconnect structure, comprising: A base substrate; A conductive pad group disposed on the base substrate; And An interconnect layer disposed on the base substrate, the interconnect layer having an edge positioned adjacent to the conductive pad group and including a side connection pad group located at the edge of the interconnect layer and exposed, each side connection pad in the side connection pad group being arranged relative to a corresponding conductive pad in the conductive pad group disposed on the base substrate. Wherein at least a portion of the top surface of the base substrate adjacent to the conductive pads and the pad surfaces of each conductive pad have enhanced surface roughness by applying a surface treatment.

2. The interconnect structure according to claim 1, wherein Each side connection pad has a top surface exposed at the top surface of the interconnect layer and an edge surface exposed at the edge of the interconnect layer, the edge surface facing the corresponding conductive pad among the conductive pads.

3. The interconnect structure according to claim 2, wherein, At least one of the edge surface and the top surface of each side connection pad has a barrier metal.

4. The interconnect structure according to claim 1, wherein, The interconnect layer further includes an insulating material forming the top surface of the interconnect layer and a first bonding pad group exposed through the insulating material at the top surface of the interconnect layer, the first bonding pad group being for mounting a chip, and each first bonding pad in the bonding pad group is connected to a corresponding one of the side connection pads via a wiring embedded in the insulating material.

5. The interconnect structure according to claim 4, wherein, The interconnect layer further includes a second bonding pad for mounting the chip and a third bonding pad for mounting another chip, the second bonding pad being connected to the third bonding pad via a trace embedded in the insulating material.

6. The interconnect structure according to claim 1, wherein, The edge of the interconnect layer has one or more curved or angled shapes to extend its length, and the side connection pad group and the conductive pad group are formed along the contour of the one or more curved or angled shapes.

7. The interconnect structure according to claim 1, wherein, Each pair of a side connection pad of the interconnect layer and a corresponding conductive pad disposed on the base substrate is independently used for power or ground.

8. The interconnect structure according to claim 1, wherein, The top surface of the base substrate and the pad surface of each conductive pad have corresponding components treated by a surface treatment for enhancing surface roughness.

9. The interconnect structure according to claim 1, further comprising: A solder joint group, each solder joint connecting a side connection pad of the interconnect layer to a corresponding conductive pad disposed on the substrate.

10. The interconnect structure according to claim 9, further comprising: One or more chips mounted on the substrate, at least one of the chips having a terminal electrically connected to a corresponding one of the conductive pads disposed on the substrate through one of the side connection pads.

11. A method for manufacturing an interconnect structure, the method comprising: Providing a base substrate including a conductive pad group disposed thereon; And Disposing an interconnect layer on the base substrate, the interconnect layer including a side connection pad group located at the edge of the interconnect layer and exposed, such that the edge of the interconnect layer is positioned adjacent to the conductive pad group, and each side connection pad in the side connection pad group is arranged relative to a corresponding conductive pad in the conductive pad group disposed on the base substrate. Apply a surface treatment for enhancing surface roughness to at least a part of the top surface of the base substrate near the conductive pads and the pad surfaces of each of the conductive pads, so as to make at least a part of the top surface of each conductive pad and the pad surfaces rougher.

12. The method according to claim 11, further comprising: Form a set of solder joints to connect the side connection pad set of the interconnect layer and the conductive pad set provided on the base substrate respectively.

13. The method according to claim 12, further comprising: Mount one or more chips on the base substrate such that at least one of the chips has terminals, and the terminals are electrically connected to one of the conductive pads provided on the base substrate through one of the side connection pads.

14. The method according to claim 11, wherein, Providing the interconnect layer includes: Placing an interconnect layer carrier structure in an inverted manner onto the base substrate, the interconnect layer carrier structure including a support substrate, a release layer on the support substrate, and an interconnect layer portion on the release layer; and Releasing the interconnect layer portion from the support substrate by removing the release layer to provide the interconnect layer disposed on the base substrate.

Images