Semiconductor device

Abstract

The semiconductor device includes: a first latch circuit (L1) composed of a first inverter circuit (i1), a second inverter circuit (i2), a third inverter circuit (i3), and a fourth inverter circuit (i4); a first-type well region (Wp1, Wp2); and a second-type well region (Wn1); in a plan view, the distance between the drain (p1) and the drain (p4) is smaller than the distance between the drain (p1) and the drain (p3).

Description

Technical Field

[0001] The present invention relates to a semiconductor device including a latch circuit and a flip-flop circuit. Background Art

[0002] In a semiconductor device, a soft error in a latch circuit (also referred to as a flip-flop circuit) in a logic circuit becomes a problem. A soft error is a temporary error in which the state of a latch flips due to noise entering when a particle beam such as cosmic rays collides with the latch circuit.

[0003] As a circuit with high soft error tolerance, for example, in the latch circuit shown in Patent Document 1, Figure 2 it is composed of four inverter circuits, and the gates of the PMOS transistor and the NMOS transistor of each inverter circuit are input with the same data but connected to different nodes. Even if noise that may cause a soft error enters one of these four nodes, it can be restored by other nodes. However, there is a weakness that if two nodes with the same data among the four nodes are simultaneously affected by a soft error, the state of the latch is likely to flip. In Patent Document 1, by alternately arranging the PMOS transistor and the NMOS transistor to eliminate noise, the above weakness is overcome.

[0004] On the other hand, a flip-flop circuit is one of the most important basic circuits that has a great impact on the chip area, so miniaturization is required. Therefore, according to the configuration shown in Patent Document 1, Figure 12 the N-well in which the PMOS transistor is arranged and the P-well in which the NMOS transistor is arranged must be separated by two or more, respectively, and the layout efficiency deteriorates, so miniaturization cannot be achieved.

[0005] For example, in the configuration shown in Non-Patent Document 1, Figure 7 since all PMOS transistors can be efficiently arranged in one N-well, it is suitable for miniaturization.

[0006] Prior Art Documents

[0007] Patent Documents

[0008] Patent Document 1: Japanese Patent No. 5369771

[0009] Non-Patent Documents

[0010] Non-Patent Document 1: "A Low-Power and Area-Efficient Radiation-Hard Redundant Flip-Flop,DICE ACFF,in a 65nm Thin-BOX FD-SOI", IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL.61, NO.4, AUGUST 2014 Summary of the Invention

[0011] Problems to be Solved by the Invention

[0012] If the PMOS transistors of the conventional latch circuit are arranged in one N-well for miniaturization of the area, two nodes having the same data among the four nodes in the latch circuit are arranged close to each other, so they are likely to be affected by noise simultaneously, and there is a problem of low soft error tolerance.

[0013] The present invention provides a semiconductor device including a latch circuit having high soft error tolerance and formed in a small area.

[0014] Means for Solving the Problems

[0015] A semiconductor device according to one aspect of the present invention includes: a first latch circuit composed of first to fourth inverter circuits; first and second p-well regions; and an n-well region. Each of the first to fourth inverter circuits includes: a p-type MOS transistor; an n-type MOS transistor; and an output node connected to the drain of the p-type MOS transistor and the drain of the n-type MOS transistor. The output node of the first inverter circuit is connected to the gate of the p-type MOS transistor of the second inverter circuit and the gate of the n-type MOS transistor of the fourth inverter circuit. The output node of the second inverter circuit is connected to the gate of the p-type MOS transistor of the third inverter circuit and the gate of the n-type MOS transistor of the first inverter circuit. The output node of the third inverter circuit is connected to the gate of the p-type MOS transistor of the fourth inverter circuit and the gate of the n-type MOS transistor of the second inverter circuit. The output node of the fourth inverter circuit is connected to the gate of the p-type MOS transistor of the first inverter circuit and the gate of the n-type MOS transistor of the third inverter circuit. The drains of the p-type MOS transistors of the first to fourth inverter circuits are respectively disposed in the n-well region. The drains of the n-type MOS transistors of the first and second inverter circuits are respectively disposed in the first p-well region. The drains of the n-type MOS transistors of the third and fourth inverter circuits are respectively disposed in the second p-well region. The n-well region is disposed between the first p-well region and the second p-well region. In a plan view, the distance between the drain of the p-type MOS transistor of the first inverter circuit and the drain of the p-type MOS transistor of the third inverter circuit is greater than the distance between the drain of the p-type MOS transistor of the first inverter circuit and the drain of the p-type MOS transistor of the fourth inverter circuit.

[0016] Advantages of the Invention

[0017] According to the present invention, it is possible to configure a latch circuit of a semiconductor device with high soft error tolerance in a small area. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 FIG. is a plan view showing an example of the planar layout of the semiconductor device according to Embodiment 1.

[0019] Figure 2 FIG. is a circuit diagram showing an example of the circuit of the semiconductor device according to Embodiment 1.

[0020] Figure 3 FIG. is an explanatory diagram of the operating state of the semiconductor device according to Embodiment 1.

[0021] Figure 4 FIG. is a plan view showing an example of the planar layout of the semiconductor device according to Embodiment 2.

[0022] Figure 5 This is a diagram showing a planar layout example of the semiconductor device of Embodiment 3.

[0023] Figure 6 This is a diagram showing a circuit example of the semiconductor device of Embodiment 3.

[0024] Figure 7 This is a diagram showing a planar layout example of the semiconductor device of Embodiment 4.

[0025] Figure 8A This is a diagram showing a circuit example of the semiconductor device of Embodiment 4.

[0026] Figure 8B This is a diagram showing Figure 8A a circuit example of the data input circuit.

[0027] Figure 8C This is a diagram showing Figure 8A a circuit example of the clock input circuit.

[0028] Figure 9 This is a diagram showing a planar layout example of the semiconductor device of Embodiment 5.

[0029] Figure 10 This is a diagram showing a planar layout example of the semiconductor device of Embodiment 6.

[0030] Figure 11 This is a diagram showing a circuit example of the semiconductor device of Embodiment 6.

[0031] Figure 12 This is a diagram showing a circuit example formed in the semiconductor device of Embodiment 1.

[0032] Figure 13 This is a diagram showing the first example of the wiring layout in the wiring layer.

[0033] Figure 14 This is a diagram showing the second example of the wiring layout in the wiring layer.

[0034] Figure 15 This is a diagram showing the third example of the wiring layout in the wiring layer.

[0035] Figure 16 This is a diagram showing the fourth example of the wiring layout in the wiring layer.

[0036] Figure 17 This is a diagram showing the fifth example of the wiring layout in the wiring layer.

[0037] Figure 18 This is a diagram showing the sixth example of the wiring layout in the wiring layer.

[0038] Figure 19This is a diagram showing the seventh example of the wiring layout within a wiring layer.

[0039] Figure 20 This is a diagram showing the eighth example of the wiring layout within a wiring layer.

[0040] Figure 21 This is a diagram showing the first example of the wiring layout between wiring layers.

[0041] Figure 22A This is a diagram showing the second example of the wiring layout between wiring layers.

[0042] Figure 22B This is a diagram showing a modified example of the second example of the wiring layout between wiring layers.

[0043] Figure 23 This is a diagram showing another circuit example formed in the semiconductor device of Embodiment 1.

[0044] Figure 24 This is a diagram showing Figure 23 a circuit diagram of an example of element C in

[0045] Figure 25 This is an explanatory diagram showing a short - circuit example of the latch circuit of the comparative example. Detailed Embodiment

[0046] Hereinafter, the embodiments will be specifically described with reference to the accompanying drawings. In addition, all the embodiments described below represent a preferred specific example of the present invention. The numerical values, shapes, materials, constituent elements, arrangement positions and connection forms of the constituent elements, steps, and the order of steps shown in the following embodiments are examples and are not intended to limit the present invention. In addition, among the constituent elements of the following embodiments, the constituent elements not described in the independent claims representing the implementation forms of one technical solution of the present invention are described as optional constituent elements. The implementation forms of the present invention are not limited to the current independent claims and can also be represented by other independent claims. In addition, each drawing is a schematic diagram and does not necessarily represent strict dimensions.

[0047] (Embodiment 1)

[0048] In the semiconductor device of the present embodiment, in a latch circuit having a redundant structure with four flip - flop circuits, the drain nodes are arranged such that the distance between two drain nodes having different data is smaller than the distance between two drain nodes having the same data. With this arrangement, even if noise caused by alpha rays or neutron beams simultaneously enters two drain nodes having the same data, since the possibility of the noise also entering the drain nodes having different data is higher, that is, the effect of eliminating noise is higher, the soft - error tolerance is improved. In addition, a semiconductor device including a latch circuit or a flip - flop circuit that can be formed in a small area can be configured.

[0049] Figure 1 is a diagram showing a planar layout example of the semiconductor device according to Embodiment 1. In addition, Figure 2 is a diagram showing a circuit example of the semiconductor device according to Embodiment 1.

[0050] The semiconductor device, as Figure 2 shown, includes a first latch circuit L1 composed of first to fourth flip-flop circuits i1 to i4. In addition, the semiconductor device includes a first p-type well region Wp1, a second p-type well region Wp2, and an n-type well region Wn1. The first p-type well region Wp1, the second p-type well region Wp2, and the n-type well region Wn1 are used to form the latch circuit L1.

[0051] The first flip-flop circuit i1 includes a p-type MOS transistor pt1, an n-type MOS transistor nt1, and an output node o1 connected to the drain p1 of the p-type MOS transistor pt1 and the drain of the n-type MOS transistor nt1.

[0052] The second flip-flop circuit i2 includes a p-type MOS transistor pt2, an n-type MOS transistor nt2, and an output node o2 connected to the drain p2 of the p-type MOS transistor pt2 and the drain of the n-type MOS transistor nt2.

[0053] The third flip-flop circuit i3 includes a p-type MOS transistor pt3, an n-type MOS transistor nt3, and an output node o3 connected to the drain p3 of the p-type MOS transistor pt3 and the drain of the n-type MOS transistor nt3.

[0054] The fourth flip-flop circuit i4 includes a p-type MOS transistor pt4, an n-type MOS transistor nt4, and an output node o4 connected to the drain p4 of the p-type MOS transistor pt4 and the drain of the n-type MOS transistor nt4.

[0055] The sources of the p-type MOS transistors of the first to fourth flip-flop circuits i1 to i4 are each connected to a power supply line of potential VDD, and the sources of the n-type MOS transistors are each connected to a GND (ground) line of potential VSS.

[0056] In addition, the first type refers to one of the conductive types of P-type and N-type. The second type refers to the other conductive type of P-type and N-type. In the Figure 1 and Figure 2 example, the first type is P-type and the second type is N-type. Hereinafter, the first type may be expressed as P, and the second type may be expressed as N. In addition, the p-type MOS transistor may be expressed as a PMOS transistor, and the n-type MOS transistor may be expressed as an NMOS transistor.

[0057] As shown Figure 2 The output node o1 of the first flip-flop circuit i1 is connected to the gate g2 of the first-type MOS transistor pt1 of the second flip-flop circuit i2 and the gate of the second-type MOS transistor nt4 of the fourth flip-flop circuit i4.

[0058] The output node o2 of the second flip-flop circuit i2 is connected to the gate g3 of the first-type MOS transistor pt3 of the third flip-flop circuit i3 and the gate of the second-type MOS transistor nt1 of the first flip-flop circuit i1.

[0059] The output node o3 of the third flip-flop circuit i3 is connected to the gate g4 of the first-type MOS transistor pt4 of the fourth flip-flop circuit i4 and the gate of the second-type MOS transistor nt2 of the second flip-flop circuit i2.

[0060] The output node o4 of the fourth flip-flop circuit i4 is connected to the gate g1 of the first-type MOS transistor pt1 of the first flip-flop circuit i1 and the gate of the second-type MOS transistor nt3 of the third flip-flop circuit i3.

[0061] As shown Figure 1 The drains P1 to p4 of the first-type MOS transistors pt1 to pt4 of the first to fourth flip-flop circuits i1 to i4 are respectively disposed in the second-type well region Wn1.

[0062] The drains n1 and n2 of the second-type MOS transistors nt1 and nt2 of the first and second flip-flop circuits i1 and i2 are respectively disposed in the first first-type well region Wp1.

[0063] The drains n3 and n4 of the second-type MOS transistors nt3 and nt4 of the third and fourth flip-flop circuits i3 and i4 are respectively disposed in the second first-type well region Wp2.

[0064] In addition, the second-type well region Wn1 is disposed between the first first-type well region Wp1 and the second first-type well region Wp2.

[0065] In a plan view, the distance d14 between the drain p1 of the first-type MOS transistor pt1 of the first flip-flop circuit i1 and the drain p4 of the first-type MOS transistor pt4 of the fourth flip-flop circuit i4 is smaller than the distance d13 between the drain p1 of the first-type MOS transistor pt1 of the first flip-flop circuit i1 and the drain p3 of the first-type MOS transistor pt3 of the third flip-flop circuit i3. Here, the plan view means observing the main surface of the semiconductor device from the normal direction. For example, Figure 1 is a view obtained by observing the semiconductor device in a plan view.

[0066] In addition, the drain is also referred to as a drain node, which refers to Figure 2 the drain region in such a circuit configuration.

[0067] With such a structure, the distance between the drain node p1 and the drain node p4 with different data is closer than the distance between the drain node p1 and the drain node p3 with the same data, so the effect of eliminating noise becomes higher.

[0068] Next, the effect of improving soft error tolerance will be described.

[0069] Figure 3 It is an explanatory diagram of the operation state of the semiconductor device of Embodiment 1. Figure 3 (a) schematically shows the situation of being affected by noise in the Figure 2 circuit diagram in the initial state where the drain nodes p1 and p3 are at low level and the drain node p4 is at high level. Figure 3 (b) of Figure 1 is an explanatory diagram of the operation state showing the potential state V when the drain nodes p1, p3, and p4 are affected by noise at time t1 within time T from the above initial state. Hereinafter, Figure 2 and Figure 3 will be used to explain the effect.

[0070] Generally, for the drain node of a PMOS transistor, holes generated by a particle beam are collected by the drain node which is a P-type diffusion region, so the potential temporarily rises. In the Figure 2 shown circuit diagram, if, for example, the drain nodes p1 and p3 are simultaneously affected by noise, when the distance between the drain nodes p1 and p3 is relatively close (in the case of d13 < d14), it becomes the potential of the dotted line shown in Figure 3 (b) of Figure 1 , and the latch state flips. However, according to the present invention, as shown in Figure 2 , the distance d14 between the drain node p1 and the drain node p4 with different data is closer than the distance d13 between the drain node p1 and the drain node p3 with the same data. Therefore, in Figure 3 , noise not only enters the drain nodes p1 and p3, but also easily enters the drain node p4, and the effect of canceling noise becomes higher. That is, even if the PMOS transistor of the drain node p4 changes from ON to OFF due to the noise of the drain node p3, since the potential of the drain node p4 rises due to the noise, the ON state of the NMOS transistor of the drain node n3 is maintained, and it functions to return the drain nodes p3 and n3 to the low level. As a result, as shown by the solid line in (b) of

[0071] , there is an effect of suppressing the flip of the latch state.According to this embodiment, by arranging PMOS transistors p1, p2, p3, and p4 in one N-well Wn1, a small area can be achieved, and by arranging the drain nodes p1, p3, and p4 in a noise-canceling manner, a semiconductor device with a latch circuit having high soft error tolerance can be realized.

[0072] As described above, the semiconductor device of Embodiment 1 includes a first latch circuit L1 composed of first to fourth flip-flop circuits i1 to i4, a first p-type well region Wp1, a second p-type well region Wp2, and an n-type well region Wn1; the first to fourth flip-flop circuits i1 to i4 each have a p-type MOS transistor pt1 / pt2 / pt3 / pt4, an n-type MOS transistor nt1 / nt2 / nt3 / nt4, and output nodes o1 / o2 / o3 / o4 connected to the drains of the p-type MOS transistor and the n-type MOS transistor; the output node o1 of the first flip-flop circuit i1 is connected to the gate g2 of the p-type MOS transistor pt1 of the second flip-flop circuit i2 and the gate of the n-type MOS transistor nt4 of the fourth flip-flop circuit i4; the output node o2 of the second flip-flop circuit i2 is connected to the gate g3 of the p-type MOS transistor pt3 of the third flip-flop circuit i3 and the gate of the n-type MOS transistor nt1 of the first flip-flop circuit i1; the output node o3 of the third flip-flop circuit i3 is connected to the gate g4 of the p-type MOS transistor pt4 of the fourth flip-flop circuit i4 and the gate of the n-type MOS transistor nt2 of the second flip-flop circuit i2; the output node o4 of the fourth flip-flop circuit i4 is connected to the gate g1 of the p-type MOS transistor pt1 of the first flip-flop circuit i1 and the gate of the n-type MOS transistor nt3 of the third flip-flop circuit i3; the drains P1 to p4 of the p-type MOS transistors of the first to fourth flip-flop circuits are respectively arranged in the n-type well region Wn1; the drains n1 and n2 of the n-type MOS transistors nt1 and nt2 of the first and second flip-flop circuits i1 and i2 are respectively arranged in the first p-type well region Wp1; the drains n3 and n4 of the n-type MOS transistors nt3 and nt4 of the third and fourth flip-flop circuits i3 and i4 are respectively arranged in the second p-type well region Wp2; the n-type well region Wn1 is arranged between the first p-type well region Wp1 and the second p-type well region Wp2; in a plan view, the distance d14 between the drain p1 of the p-type MOS transistor pt1 of the first flip-flop circuit i1 and the drain p4 of the p-type MOS transistor pt4 of the fourth flip-flop circuit i4 is smaller than the distance d13 between the drain p1 of the p-type MOS transistor pt1 of the first flip-flop circuit i1 and the drain p3 of the p-type MOS transistor pt3 of the third flip-flop circuit i3.

[0073] Thus, a latch circuit that has high soft error tolerance and can be formed in a small area can be realized. Since the distance d14 between the drain node p1 and the drain node p4 having different data is closer than the distance d13 between the drain node p1 and the drain node p3 having the same data, the effect of eliminating noise can be improved. In addition, since the second-type well region Wn1 is disposed between the two well regions Wp1, a small area can be realized.

[0074] Here, the first and second first-type well regions Wp1 and Wp2 may be P-type wells, and the second-type well region Wn1 may be an N-type well.

[0075] Thus, by adopting, for example, Figure 1 such a circuit configuration, the soft error tolerance can be improved.

[0076] (Embodiment 2)

[0077] In Embodiment 2, a circuit configuration example different from that of Embodiment 1 will be described.

[0078] Figure 4 FIG. is a plan view configuration example of the semiconductor device according to Embodiment 2. According to Figure 4 the configuration diagram shown, the semiconductor device of Embodiment 2 realizes the circuit of Embodiment 1 with a different configuration. Figure 4 The reference numerals shown are the same as those in Embodiment 1, but the configurations of the drain nodes p4, p3, n2, and n1 are different.

[0079] In the Figure 1 circuit configuration example shown in Embodiment 1, the circuit elements of the latch circuit L1 are separately disposed in two rectangular regions. In contrast, in the Figure 4 circuit configuration example shown in Embodiment 2, the circuit elements of the latch circuit L1 are efficiently disposed within one rectangular region.

[0080] Similar to Embodiment 1, the distance (d14) between the drain node p1 and the drain node p4 having different data is closer than the distance (d13) between the drain node p1 and the drain node p3 having the same data. Furthermore, according to Figure 4 the configuration, the distance between the drain node p2 and the drain node p3 having different data is closer than the distance between the drain node p2 and the drain node p4 having the same data. Therefore, the effect of eliminating noise is further improved compared to Embodiment 1.

[0081] As described above, regarding the semiconductor device of Embodiment 2, in a plan view, the distance between the drain p2 of the first-type MOS transistor pt1 of the second flip-flop circuit i2 and the drain p4 of the first-type MOS transistor pt4 of the fourth flip-flop circuit i4 is greater than the distance between the drain p2 of the first-type MOS transistor pt2 of the second flip-flop circuit i2 and the drain p3 of the first-type MOS transistor pt3 of the third flip-flop circuit i3, and is also greater than the distance between the drain p3 of the first-type MOS transistor pt3 of the third flip-flop circuit i3 and the drain p4 of the first-type MOS transistor pt4 of the fourth flip-flop circuit i4.

[0082] Thus, by adopting a circuit configuration such as Figure 4 that, the soft error tolerance can be improved, and furthermore, the circuit area can be reduced.

[0083] (Embodiment 3)

[0084] In Embodiment 3, an example in which the latch circuit L1 of Embodiments 1 and 2 includes at least one clocked flip-flop circuit will be described.

[0085] Figure 5 FIG. is a diagram showing a planar layout example of the semiconductor device of Embodiment 3. In addition, Figure 6 FIG. is a diagram showing a circuit example of the semiconductor device of Embodiment 3.

[0086] Figure 6 The latch circuit L1 shown in Figure 3 differs from that in

[0087] that PMOS transistors pc2 and NMOS transistors nc2 are added to the second flip-flop circuit i2, and PMOS transistors pc4 and NMOS transistors nc4 are added to the fourth flip-flop circuit i4. The following description will focus on the differences.

[0088] In a semiconductor device that operates in synchronization with such clock signals CKI and CKIN, since a function to disconnect the connection state of the latch circuit L1 is required when forcibly rewriting the held data of the latch circuit L1, the second flip-flop circuit i2 and the fourth flip-flop circuit i4 that constitute the feedback path of the latch are configured as clocked flip-flop circuits. The latch circuit L1 can be used as an element circuit for constructing a flip-flop circuit capable of writing arbitrary data. The same effects as those of the first embodiment can be obtained in terms of soft error tolerance and area.

[0089] As described above, in the semiconductor device of the third embodiment, at least one of the first and second first to fourth flip-flop circuits i1 to i4 is a clocked flip-flop circuit that takes a clock signal as an input.

[0090] Accordingly, it is possible to configure a latch circuit having a clocked flip-flop circuit with high soft error tolerance and a small area.

[0091] (Embodiment 4)

[0092] In the fourth embodiment, a configuration example of a master-slave type flip-flop circuit including two latch circuits of the third embodiment will be described.

[0093] Figure 7 FIG. is a plan view configuration example of the semiconductor device of the fourth embodiment. Figure 8A FIG. is a circuit example of the semiconductor device of the fourth embodiment. Figure 8B FIG. shows Figure 8A a circuit example of the data input circuit. Figure 8C FIG. shows Figure 8A a circuit example of the clock input circuit.

[0094] In Figure 8A , the flip-flop circuit F1 includes a data input circuit Id, a clock input circuit Ick, a switch circuit S1, a switch circuit S2, a latch circuit L1, a latch circuit L2, and an output circuit O1.

[0095] The data input circuit Id is a flip-flop buffer circuit that receives the data D and outputs the inverted data D.

[0096] The clock input circuit Ick receives the clock input signal CK and generates a non-inverted clock signal CKI and its inverted clock signal CKIN.

[0097] The switch circuit S1 is a transfer circuit that transfers and cuts off the data from the data input circuit Id to the latch circuit L1. The transfer and cut-off (i.e., conduction and non-conduction) states of the switch circuit S1 are controlled by the clock signals CKI and CKIN. In the example of this figure, when the clock signal CKI is at a low level (at this time the clock signal CKIN is at a high level), it becomes the conduction state, and when it is at a high level, it becomes the non-conduction state.

[0098] The switch circuit S2 is a transfer circuit that transfers and cuts off the data from the latch circuit L1 to the latch circuit L2. The switch circuit S2 can have the same structure as the switch circuit S1. However, the clock signal CKI and the clock signal CKIN input to the switch circuit S2 are switched compared with the switch circuit S1.

[0099] The latch circuit L1 has the same structure as the Figure 6 latch circuit L1 with a clocked flip-flop circuit shown.

[0100] The latch circuit L2 has the same structure as the Figure 6 latch circuit L1 with a clocked flip-flop circuit shown. However, the clock signal CKI and the clock signal CKIN input to the latch circuit L2 are switched compared with the Figure 8A latch circuit L1. This is to transfer data sequentially from the main (latch circuit L1) to the sub (latch circuit L2). In addition, the four flip-flop circuits of the latch circuit L2 are referred to as the fifth flip-flop circuit i5 to the eighth flip-flop circuit i8.

[0101] The fifth flip-flop circuit i5 has a first-type MOS transistor pt12, a second-type MOS transistor nt12, and an output node o12 connected to the drain p12 of the first-type MOS transistor pt12 and the drain of the second-type MOS transistor nt12.

[0102] The sixth flip-flop circuit i6 has a first-type MOS transistor pt22, a second-type MOS transistor nt22, and an output node o22 connected to the drain p22 of the first-type MOS transistor pt22 and the drain of the second-type MOS transistor nt22.

[0103] The seventh flip-flop circuit i7 has a first-type MOS transistor pt32, a second-type MOS transistor nt32, and an output node o32 connected to the drain p32 of the first-type MOS transistor pt32 and the drain of the second-type MOS transistor nt32.

[0104] The eighth flip-flop circuit i8 has a first-type MOS transistor pt42, a second-type MOS transistor nt42, and an output node o42 connected to the drain p42 of the first-type MOS transistor pt42 and the drain of the second-type MOS transistor nt42.

[0105] The output node o12 of the fifth flip-flop circuit i5 is connected to the gate g22 of the first-type MOS transistor pt22 of the sixth flip-flop circuit i6 and the gate of the second-type MOS transistor nt42 of the eighth flip-flop circuit i8.

[0106] The output node o22 of the sixth flip-flop circuit i6 is connected to the gate g32 of the first-type MOS transistor pt32 of the seventh flip-flop circuit i7 and the gate of the second-type MOS transistor nt12 of the fifth flip-flop circuit i5.

[0107] The output node o32 of the seventh flip-flop circuit i7 is connected to the gate g42 of the first-type MOS transistor pt42 of the eighth flip-flop circuit i8 and the gate of the second-type MOS transistor nt22 of the sixth flip-flop circuit i6.

[0108] The output node o42 of the eighth flip-flop circuit i8 is connected to the gate g12 of the first-type MOS transistor pt12 of the fifth flip-flop circuit i5 and the gate of the second-type MOS transistor nt32 of the seventh flip-flop circuit i7.

[0109] The drains of the first-type MOS transistors pt12, pt22, pt32, pt42 of the fifth to eighth flip-flop circuits i5 to i8 are respectively disposed in the second-type well region Wn1.

[0110] The drains of the second-type MOS transistors of the fifth and sixth flip-flop circuits are respectively disposed in the first first-type well region Wp1.

[0111] The drains of the second-type MOS transistors of the seventh and eighth flip-flop circuits are respectively disposed in the second first-type well region Wp2.

[0112] As Figure 7 shown, in a plan view, compared with the distance between the drain p12 of the first-type MOS transistor pt12 of the fifth flip-flop circuit i5 and the drain p32 of the first-type MOS transistor pt32 of the seventh flip-flop circuit i7, the distance between the drain p12 of the first-type MOS transistor pt12 of the fifth flip-flop circuit i5 and the drain p42 of the first-type MOS transistor pt42 of the eighth flip-flop circuit i8 is smaller.

[0113] In addition, in the planar view, the drain closest to the drain p11 of the first-type MOS transistor pt11 of the first flip-flop circuit i1 among the drains of the first-type MOS transistors of the first to eighth flip-flop circuits i1 to i8 is included in the seventh flip-flop circuit i7. The drain closest to the drain p21 of the first-type MOS transistor pt21 of the second flip-flop circuit i2 among the drains of the first-type MOS transistors of the first to eighth flip-flop circuits i1 to i8 is included in the eighth flip-flop circuit i8. In other words, the drain p11 is arranged near the drain p32. The drain p21 is arranged near the drain p42.

[0114] The output circuit O1 is a flip-flop buffer circuit for outputting data from the latch circuit.

[0115] In Figure 8B , the data input circuit Id is an inverter circuit including at least a first-type MOS transistor 111. Specifically, the data input circuit Id includes a PMOS transistor 111, an NMOS transistor 112, and an output node connected to the drain 113 of the PMOS transistor 111 and the drain of the NMOS transistor 112.

[0116] In Figure 8C , the clock input circuit Ick includes a two-stage inverter circuit.

[0117] The two-stage inverter circuit includes at least a first-type MOS transistor 101. Specifically, the first-stage inverter circuit includes a PMOS transistor 101, an NMOS transistor 102, and an output node connected to the drain 103 of the PMOS transistor 101 and the drain of the NMOS transistor 102.

[0118] The second-stage inverter circuit includes a PMOS transistor 104, an NMOS transistor 105, and an output node connected to the drain 106 of the PMOS transistor 104 and the drain of the NMOS transistor 105.

[0119] The first-stage output node is connected to the gates of the second-stage PMOS transistor 104 and the NMOS transistor 105. The first-stage output node outputs the clock signal CKIN. In addition, the second-stage output node outputs the clock signal CKI.

[0120] In Figure 7In the circuit configuration example, one of the drains 113 of the first-type MOS transistor 111 of the data input circuit Id and the drain 103 of the first-type MOS transistor 101 of the clock input circuit Ick is arranged and configured in the first direction together with the drain p11 of the first-type MOS transistor pt11 of the first flip-flop circuit i1 and the drain p21 of the first-type MOS transistor pt21 of the second flip-flop circuit i2. In addition, the other of the drains 113 of the first-type MOS transistor 111 of the data input circuit Id and the drain 113 of the first-type MOS transistor 101 of the clock input circuit Ick is arranged and configured in the first direction together with the drain p31 of the first-type MOS transistor pt31 of the third flip-flop circuit i3 and the drain p41 of the first-type MOS transistor pt41 of the fourth flip-flop circuit i4. With this configuration, the data input circuit Id and the clock input circuit Ick can be arranged efficiently as Figure 7 shown, and the circuit area can be made smaller.

[0121] According to Figure 7 the configuration diagram shown and Figures 8A - 8C the circuit diagram shown, the semiconductor device of Embodiment 4 includes a flip-flop circuit F1. The flip-flop circuit F1 uses two latch circuits of Embodiment 3, which are respectively set as latch circuits L1 and L2, and includes a clock input circuit Ick that receives a clock input signal CK and generates an internal clock signal CKI and its inverted signal CKIN, a data input circuit Id that receives a data input signal D, switch circuits S1 and S2, and an output circuit O1.

[0122] As Figure 7 shown, in the latch circuit L1, the drain nodes p11, p21, p31, and p41 of the PMOS transistors pt11, pt21, pt31, and pt41 are arranged in the N-well region Wn1. The drain nodes n11 and n21 of the NMOS transistors nt11 and nt21 are arranged in the P-well region Wp1. The drain nodes n31 and n41 of the NMOS transistors nt31 and nt41 are arranged in the P-well region Wp2. The transistors pt11 and nt31 of the drain nodes p11 and n31 share a gate g11. The transistors pt21 and nt41 of the drain nodes p21 and n41 share a gate g21. The transistors pt31 and nt11 of the drain nodes p31 and n11 share a gate g31. The transistors pt41 and nt21 of the drain nodes p41 and n21 share a gate g41.

[0123] In the latch circuit L2, the drain nodes p12, p22, p32, p42 of the PMOS transistors pt12, pt22, pt32, pt42 are arranged in the N-well region Wn1. The drain nodes n12, n22 of the NMOS transistors nt12, nt22 are arranged in the P-well region Wp1. The drain nodes n32, n42 of the NMOS transistors nt32, nt42 are arranged in the P-well region Wp2. The transistors pt12, nt32 of the drain nodes p12 and n32 share the gate g12. The transistors pt22, nt42 of the drain nodes p22 and n42 share the gate g22. The transistors pt32, nt12 of the drain nodes p32 and n12 share the gate g32. The transistors pt42, nt22 of the drain nodes p42 and n22 share the gate g42. Regarding the configurations of the clock input circuit Ick, the data input circuit Id, the switch circuits S1, S2, and the output circuit O1, a part is omitted in the Figure 7 configuration example.

[0124] As Figure 7 shown, in the latch circuit L1, since the distance between the drain node p11 and the drain node p41 having different data is closer than the distance between the drain node p11 and the drain node p31 having the same data, the effect of eliminating the above noise is improved. Further, in the latch circuit L2, also since the distance between the drain node p12 and the drain node p42 having different data is closer than the distance between the drain node p12 and the drain node p32 having the same data, the effect of eliminating the above noise is further improved. In addition, for example, in the case of configuring as in Figure 7 such a way that the gates gck receiving the internal clock inversion signal CKIN are shared by multiple transistors, the number of wirings in the flip-flop circuit can be reduced, contributing to miniaturization.

[0125] According to the present embodiment, by arranging the PMOS transistors p11, p21, p31, p41, p12, p22, p32, p42 in one N-well Wn1, a small area can be formed, and by arranging the drain nodes p11, p31, p41 and the drain nodes p12, p32, p42 in a noise-eliminating manner, a semiconductor device having a flip-flop circuit with high soft error tolerance can be realized.

[0126] As described above, the semiconductor device of Embodiment 4 includes a second latch circuit L2 composed of fifth to eighth inverter circuits at the subsequent stage of the first latch circuit L1; the fifth to eighth inverter circuits i5 to i8 each have a first-type MOS transistor pt12 / pt22 / pt32 / pt42, a second-type MOS transistor nt12 / nt22 / nt32 / nt42, and output nodes o12 / o22 / o32 / o42 connected to the drains of the first-type MOS transistor and the drains of the second-type MOS transistor; the output node o12 of the fifth inverter circuit i5 is connected to the gate g22 of the first-type MOS transistor pt22 of the sixth inverter circuit i6 and the gate of the second-type MOS transistor nt42 of the eighth inverter circuit i8; the output node o22 of the sixth inverter circuit i6 is connected to the gate g32 of the first-type MOS transistor pt32 of the seventh inverter circuit i7 and the gate of the second-type MOS transistor nt12 of the fifth inverter circuit i5; the output node o32 of the seventh inverter circuit i7 is connected to the gate g42 of the first-type MOS transistor pt42 of the eighth inverter circuit i8 and the gate of the second-type MOS transistor nt22 of the sixth inverter circuit i6; the output node o42 of the eighth inverter circuit i8 is connected to the gate g12 of the first-type MOS transistor pt12 of the fifth inverter circuit i5 and the gate of the second-type MOS transistor nt32 of the seventh inverter circuit i7; the drains of the first-type MOS transistors pt12, pt22, pt32, pt42 of the fifth to eighth inverter circuits i5 to i8 are respectively arranged in the second-type well region Wn1; the drains of the second-type MOS transistors of the fifth and sixth inverter circuits are respectively arranged in the first first-type well region Wp1; the drains of the second-type MOS transistors of the seventh and eighth inverter circuits are respectively arranged in the second first-type well region Wp2; in a plan view, the distance between the drain p12 of the first-type MOS transistor pt12 of the fifth inverter circuit i5 and the drain p42 of the first-type MOS transistor pt42 of the eighth inverter circuit i8 is smaller than the distance between the drain p12 of the first-type MOS transistor pt12 of the fifth inverter circuit i5 and the drain p32 of the first-type MOS transistor pt32 of the seventh inverter circuit i7.

[0127] Accordingly, it is possible to configure the master-slave flip-flop circuit with high soft error tolerance and a small area.

[0128] Here, in a plan view, the drain closest to the drain p11 of the first-type MOS transistor pt11 of the first inverter circuit i1 among the drains of the first-type MOS transistors of the first to eighth inverter circuits i1 to i8 may be included in the seventh inverter circuit i7, and in a plan view, the drain closest to the drain p21 of the first-type MOS transistor pt21 of the second inverter circuit i2 among the drains of the first-type MOS transistors of the first to eighth inverter circuits i1 to i8 may be included in the eighth inverter circuit i8.

[0129] Thus, for example, by adopting a circuit configuration such as Figure 7 the soft error tolerance can be improved.

[0130] Here, it may be that the semiconductor device includes a data input circuit Id and a clock input circuit Ick; the data input circuit Id is an inverter circuit including at least one first-type MOS transistor 111; the clock input circuit Ick includes a two-stage inverter circuit i10, i11; the two-stage inverter circuit includes at least one first-type MOS transistor 101 / 104; one of the drains 113 of the first-type MOS transistor 111 of the data input circuit Id and the drains 103 / 106 of the first-type MOS transistor 101 / 104 of the clock input circuit Ick is arranged and configured in a first direction with the drain p11 of the first-type MOS transistor pt11 of the first flip-flop circuit i1 and the drain p21 of the first-type MOS transistor pt21 of the second flip-flop circuit i2; the other of the drains 113 of the first-type MOS transistor 111 of the data input circuit Id and the drain 103 of the first-type MOS transistor 101 of the clock input circuit Ick is arranged and configured in the first direction with the drain p31 of the first-type MOS transistor pt31 of the third flip-flop circuit i3 and the drain p41 of the first-type MOS transistor pt41 of the fourth flip-flop circuit i4.

[0131] (Embodiment 5)

[0132] In Embodiment 5, a circuit configuration example different from that of Embodiment 4 will be described.

[0133] Figure 9 FIG. is a plan view showing a plan configuration example of the semiconductor device of Embodiment 5. Figure 9 In the shown configuration diagram, the semiconductor device of Embodiment 5 realizes the circuit of Embodiment 4 through other configurations. Figure 9 The reference numeral descriptions shown are the same as those in Embodiment 4, and in addition, the effect of improving the soft error tolerance is also the same. Figure 9 Among them, the configurations of the clock input circuit Ick and the data input circuit Id are different from Figure 7 The latch circuits L1 and L2 are configured to be efficiently included in one rectangular area.

[0134] As Figure 9 shown, in a plan view, the drain closest to the drain p11 of the first-type MOS transistor pt11 of the first flip-flop circuit i1 among the drains of the first-type MOS transistors of the first to eighth flip-flop circuits is included in the seventh flip-flop circuit i7. That is, the drain p11 is arranged as close as possible to the drain p32.

[0135] In a plan view, the drain closest to the drain p21 of the first-type MOS transistor pt21 of the second flip-flop circuit i2 among the drains of the first-type MOS transistors of the first to eighth flip-flop circuits is included in the eighth flip-flop circuit i8. That is, the drain p21 is arranged at a position as close as possible to the drain p42.

[0136] In a plan view, the drain closest to the drain p31 of the first-type MOS transistor pt31 of the third flip-flop circuit i3 among the drains of the first-type MOS transistors of the first to eighth flip-flop circuits is included in the fifth flip-flop circuit i5. That is, the drain p31 is arranged at a position as close as possible to the drain p12.

[0137] In a plan view, the drain closest to the drain p41 of the first-type MOS transistor pt41 of the fourth flip-flop circuit i4 among the drains of the first-type MOS transistors of the first to eighth flip-flop circuits is included in the sixth flip-flop circuit i6. That is, the drain p41 is arranged at a position as close as possible to the drain p22.

[0138] In other words, the latch circuit L1 is divided into two circuit portions and arranged as shown by the dashed line box. The two circuit portions are of substantially the same size. The latch circuit L2 is divided into two circuit portions and arranged as shown by the dotted line box. The two circuit portions are of substantially the same size. The four circuit portions of the latch circuits L1 and L2 are alternately arranged so that they can be efficiently included in one rectangular region (a substantially square region). The alternate arrangement described here refers to an arrangement such as a crosswise arrangement or a checkerboard arrangement, for example.

[0139] In this way, by optimizing the arrangement of the circuit portions, a semiconductor device can be realized that has a state of maintaining improved soft error tolerance and has a flip-flop circuit in a small area.

[0140] As described above, in the semiconductor device of Embodiment 5, in a plan view, the drain closest to the drain p11 of the first-type MOS transistor pt11 of the first flip-flop circuit i1 among the drains of the first-type MOS transistors of the first to eighth flip-flop circuits i1 to i8 is included in the seventh flip-flop circuit i7; in a plan view, the drain closest to the drain p21 of the first-type MOS transistor pt21 of the second flip-flop circuit i2 among the drains of the first-type MOS transistors of the first to eighth flip-flop circuits is included in the eighth flip-flop circuit i8; in a plan view, the drain closest to the drain p31 of the first-type MOS transistor pt31 of the third flip-flop circuit i3 among the drains of the first-type MOS transistors of the first to eighth flip-flop circuits is included in the fifth flip-flop circuit i5; in a plan view, the drain closest to the drain p41 of the first-type MOS transistor pt41 of the fourth flip-flop circuit i4 among the drains of the first-type MOS transistors of the first to eighth flip-flop circuits is included in the sixth flip-flop circuit i6.

[0141] Thus, by adopting a circuit configuration such as Figure 9 that, the soft error tolerance can be improved, and further the circuit area can be reduced.

[0142] (Embodiment 6)

[0143] In Embodiment 6, an example in which the master-slave type flip-flop circuit of Embodiment 4 further has a reset function will be described.

[0144] Figure 10 FIG. is a plan view example of a semiconductor device according to Embodiment 6 of the present invention. In addition, Figure 11 FIG. is a circuit diagram example of a semiconductor device according to Embodiment 6 of the present invention.

[0145] Figure 11 Compared with the Figure 8A circuit diagram example, the differences are that a PMOS transistor pr21 and an NMOS transistor nr21 are added to the second flip-flop circuit i2, a PMOS transistor pr41 and an NMOS transistor nr41 are added to the fourth flip-flop circuit i4, a PMOS transistor pr22 and an NMOS transistor nr22 are added to the sixth flip-flop circuit i6, and a PMOS transistor pr42 and an NMOS transistor nr42 are added to the eighth flip-flop circuit i8. Hereinafter, the description will focus on the differences.

[0146] A reset input signal is supplied to the gates of the added PMOS transistor and NMOS transistor.

[0147] According to Figure 10 the configuration diagram shown and Figure 11 the circuit diagram shown, in the semiconductor device of Embodiment 6, in addition to the semiconductor device of Embodiment 4, transistors for receiving a reset input signal R are added, so that the second, fourth, sixth, and eighth flip-flop circuits i2, i4, i6, and i8 have a reset function constituted by a 2-input NAND. Figure 10 The reference numeral description shown is the same as that in Embodiment 4, and in addition, the effect of improving the soft error tolerance is also the same. In a case where the gates gr for receiving the reset input signal R are shared by a plurality of transistors as in Figure 10 that, the number of wirings in the flip-flop circuit can be reduced, which is helpful for miniaturization, and a semiconductor device having a flip-flop circuit with high soft error tolerance can be realized.

[0148] As described above, in the semiconductor device of Embodiment 6, at least one of the first to eighth flip-flop circuits i1 to i8 is a NAND type flip-flop circuit that takes a reset signal or a set signal as an input.

[0149] Accordingly, in a flip-flop circuit having a reset function (or a set function), soft error tolerance can be improved.

[0150] (Embodiment 7)

[0151] In this embodiment, a semiconductor device that solves the following problems will be described with respect to a circuit having high soft error tolerance.

[0152] First, use Figure 25 to specifically describe this problem.

[0153] Figure 25 FIG. is an explanatory diagram of a short-circuit example of a latch circuit showing a comparative example. Figure 25 The latch circuit shown in (a) of FIG. includes four PMOS transistors and four NMOS transistors. Pairs of serially connected PMOS transistors and NMOS transistors form inverter circuits.

[0154] A normal latch circuit includes two inverter circuits. In contrast, Figure 25 (a) of FIG. includes four inverter circuits. Figure 25 The latch circuit in (a) of FIG. has improved soft error tolerance through a dual redundant structure.

[0155] In Figure 25 (a) of FIG., the four inverter circuits are connected by four wirings w1 to w4. Wirings w1 and w3 are a redundant wiring pair and are independent wirings having the same signal level. Similarly, wirings w2 and w4 are a redundant wiring pair and are independent wirings having the same signal level.

[0156] In this figure, the wirings w1 and w3 of the redundant wiring pair are depicted with thin lines, showing an example of a low level. In addition, the wirings w2 and w4 of the other redundant wiring pair are depicted with thick lines, showing an example of a high level.

[0157] The gates of the PMOS transistors and NMOS transistors of each inverter circuit are input with the same signal level but are connected to different wirings. That is, one of the redundant wiring pairs is connected to the gate of the PMOS transistor. The other of the redundant wiring pairs is connected to the gate of the NMOS transistor. In this way, a loop is formed by the four inverter circuits, so that even if the output of one inverter circuit flips, the correct value can be maintained by the other three inverter circuits. In this way, the latch circuit in this figure has improved soft error tolerance.

[0158] Figure 25 (b) of FIG. shows a case where wirings w1 and w3 are short-circuited as shown by the dashed box sh1. In addition, Figure 25(c) shows a case where the wiring w2 and the wiring w4 are short-circuited as shown by the dotted-line frame sh2. Such a short circuit may occur in the manufacturing process of a semiconductor device including a latch circuit due to the mixing of conductive foreign matter such as metal particles, for example.

[0159] Whether in Figure 25 (b) or in Figure 25 In (c), both redundant wiring pairs are short-circuited. That is, although the wiring pairs that are short-circuited in the dotted-line frame sh1 and the dotted-line frame sh2 are independent wirings that are not connected to each other, they always have the same signal level during the operation of the latch circuit. Figure 25 (b) or in Figure 25 In (c), the latch circuits all operate normally without showing abnormality. However, since the redundancy of the wiring pair is lost due to the short circuit, there is a problem that the soft error tolerance is degraded.

[0160] Furthermore, the short circuits of the dotted-line frames sh1 and sh2 cannot be detected in the inspection stage of the semiconductor device manufacturing process. That is, there is a problem that the degradation of the soft error tolerance caused by the short circuits of the dotted-line frames sh1 and sh2 cannot be detected.

[0161] Therefore, the present invention provides a semiconductor device that reduces the degradation of soft error tolerance caused by a short circuit of a redundant wiring pair.

[0162] In order to solve such a problem, a semiconductor device of a technical solution of the present invention comprises: a first wiring; a second wiring, which is not connected to the above-mentioned first wiring and is redundantly provided to transmit the same signal level as the above-mentioned first wiring; and other wirings, which are wirings different from the above-mentioned first wiring and the above-mentioned second wiring; within the wiring layer, the distance between the above-mentioned first wiring and the above-mentioned second wiring is greater than the distance between the above-mentioned first wiring and the above-mentioned other wirings, and is greater than the distance between the above-mentioned second wiring and the above-mentioned other wirings.

[0163] Thus, the degradation of soft error tolerance caused by the short circuit of the redundant wiring pair can be reduced. This is because, when a foreign object of the same size as the distance between the wirings is mixed, a short circuit between the first wiring or the second wiring and another wiring is more likely to occur than a short circuit between the first wiring and the second wiring. As a result, the occurrence of undetectable short circuits is suppressed, in other words, the occurrence of short circuits of the redundant wiring pair is suppressed.

[0164] When the first wiring or the second wiring is short-circuited with other wiring due to the mixing of foreign matter, the probability of causing abnormal operation is high, so the short circuit can be detected in the inspection stage before factory shipment.

[0165] In this way, it is possible to reduce the degradation of soft error tolerance caused by a short circuit of the redundant wiring pair.

[0166] Hereinafter, embodiments will be specifically described with reference to the drawings.

[0167] [7.1 Circuit Example of Semiconductor Device]

[0168] Figure 12 It is a diagram showing a circuit example formed in the semiconductor device of Embodiment 1.

[0169] The main difference of this diagram from Figure 2 is that the labels of the drains p1 to p4 are omitted and the labels of the wirings w11, w12, w21, and w22 are added. Hereinafter, the description will focus on the differences.

[0170] The first to fourth flip-flop circuits are connected by four wirings w11, w12, w21, and w22. The wiring w11 and the wiring w12 are a redundant wiring pair, and are independent wirings that have the same signal level but are not connected to each other. Similarly, the wiring w21 and the wiring w22 are a redundant wiring pair, and are independent wirings that have the same signal level but are not connected to each other. In addition, each wiring constituting the redundant wiring pair refers to a series of conductors that includes not only the metal wiring part in the wiring layer, but also the via contact part between the wiring layers, the gates, sources, and drains of the transistors, and the terminal electrodes of the circuit elements. Hereinafter, the via contact part may be simply referred to as a via.

[0171] The wiring w11 connects the output node o1 of the first flip-flop circuit i1 to the gate g2 of the first-type MOS transistor pt2 of the second flip-flop circuit i2 and the gate of the second-type MOS transistor nt4 of the fourth flip-flop circuit i4.

[0172] The wiring w21 connects the output node o2 of the second flip-flop circuit i2 to the gate g3 of the first-type MOS transistor pt3 of the third flip-flop circuit i3 and the gate of the second-type MOS transistor nt1 of the first flip-flop circuit i1.

[0173] The wiring w12 connects the output node o3 of the third flip-flop circuit i3 to the gate g4 of the first-type MOS transistor pt4 of the fourth flip-flop circuit i4 and the gate of the second-type MOS transistor nt2 of the second flip-flop circuit i2.

[0174] The wiring w22 connects the output node o4 of the fourth flip-flop circuit i4 to the gate g1 of the first-type MOS transistor pt1 of the first flip-flop circuit i1 and the gate of the second-type MOS transistor nt3 of the third flip-flop circuit i3.

[0175] With such connection, a loop is formed by four inverter circuits. Therefore, even if the output of one inverter circuit is flipped due to a soft error, the other three inverter circuits can maintain the correct value. In this way, the latch circuit L1 of the figure improves the soft error tolerance.

[0176] Figure 12 The latch circuit L1 shown constitutes a part of a semiconductor circuit formed on a semiconductor substrate in a semiconductor device. The semiconductor circuit formed on the semiconductor substrate includes a plurality of p-type impurity regions, a plurality of n-type impurity regions, a plurality of wiring layers, a plurality of contacts connecting the wiring layers, and the like.

[0177] As Figure 12 The redundant wiring pairs of the components of the latch circuit L1 are formed in one or more wiring layers. In this embodiment, the redundant wiring pairs are arranged so that short circuits are less likely to occur in the redundant wiring pairs due to the mixing of foreign matter in the manufacturing process of the semiconductor device.

[0178] Next, the wiring layout of redundant wiring pairs in one wiring layer will be described.

[0179] [7.2.1 Example 1 of wiring layout in a wiring layer]

[0180] Figure 13 This is a diagram showing a first example of a wiring layout in a wiring layer of a semiconductor device. Figure 12 FIG. 1 is a diagram showing a semiconductor substrate of a latch circuit L1 viewed from above. Figure 13 This is a diagram schematically showing an enlarged view of a portion of a plurality of wirings formed in one wiring layer. Figure 13 Schematic diagram showing the layout of four wirings 11, 12, 21, and 22.

[0181] The wiring 11 and the wiring 12 represent a redundant wiring pair. Specifically, the wiring 12 is a wiring that is not connected to the wiring 11 and is redundantly provided to transmit the same signal level as the wiring 11. The wiring 11 and the wiring 12 are, for example, Figure 12 The wirings w11 and w12 correspond to each other.

[0182] The wiring 21 is another wiring different from the wiring 11 and the wiring 12. The wiring 22 is also another wiring different from the wiring 11 and the wiring 12.

[0183] In the figure, a represents the distance between wiring 11 and wiring 12. b1 represents the distance between wiring 11 and wiring 21. b2 represents the distance between wiring 12 and wiring 21. b3 represents the distance between wiring 11 and wiring 22. b4 represents the distance between wiring 12 and wiring 22. In addition, these distances are the minimum distances between wirings.

[0184] The layout of these wirings satisfies the following relationships.

[0185] The distance a between wiring 11 and wiring 12 is greater than the distance b1 between wiring 11 and wiring 21.

[0186] The distance a between wiring 11 and wiring 12 is greater than the distance b2 between wiring 12 and wiring 21.

[0187] The distance a between wiring 11 and wiring 12 is greater than the distance b3 between wiring 11 and wiring 22.

[0188] The distance a between wiring 11 and wiring 12 is greater than the distance b4 between wiring 12 and wiring 22.

[0189] This is because, by satisfying this relationship, in the case where foreign matter is mixed in, compared to the short circuit between wiring 11 and wiring 12 which is a redundant wiring pair, a short circuit between wiring 11 or wiring 12 and other wirings (21, 22) is more likely to occur. As a result, the occurrence of undetectable short circuits is suppressed. In other words, the occurrence of short circuits in the redundant wiring pair is suppressed.

[0190] Since a short circuit between wiring 11 or wiring 12 and other wirings (21, 22) is more likely to occur, the short circuit can be detected. Therefore, the degradation of soft error tolerance caused by the short circuit of the redundant wiring pair can be alleviated.

[0191] In Figure 13 , in order to satisfy the above relationship, wiring 22 includes an extension portion e1 extending from a via hole v2 connected to the main body portion of wiring 22. The end portion of the extension portion e1 may be an open end that is not connected within the wiring layer.

[0192] In addition, Figure 13 wiring 21 and wiring 22 of Figure 12 may be, for example, wirings corresponding to wirings w21 and w22 of

[0193] [7.2.2 Second Example of Wiring Layout within Wiring Layer]

[0194] Figure 14 is a diagram showing a second example of the wiring layout within the wiring layer. This diagram is a diagram schematically enlarging a part of a plurality of wirings formed within one wiring layer. In Figure 14 , the layout of wirings 11, 12, and 21 is shown. In the figure, v1 represents a via contact portion connecting wiring 21 to a wiring of another wiring layer. e1 refers to an extension portion of wiring 21.

[0195] The wirings 11 and 12 represent a redundant wiring pair. The wiring 21 is another wiring different from the wirings 11 and 12. The wirings 11 and 12 of the redundant wiring pair have a parallel section configured in parallel within the wiring layer, and sandwich the other wiring 21 throughout the parallel section.

[0196] Figure 14 The wiring layout example of Figure 13 similarly satisfies the following relationship.

[0197] The distance a between the wiring 11 and the wiring 12 is larger than the distance b1 between the wiring 11 and the wiring 21.

[0198] The distance a between the wiring 11 and the wiring 12 is larger than the distance b2 between the wiring 12 and the wiring 21.

[0199] In Figure 14 , the wirings 11 and 12 of the redundant wiring pair are configured to sandwich the other wiring 21 throughout the parallel section where the wirings 11 and 12 are configured in parallel. For this reason, the wiring 21 has an extension part e1. That is, the wiring 21 includes an extension part e1 extending from a via hole v1 connected to the main body part of the wiring 21. The extension part e1 is disposed between the wiring 11 and the wiring 12 within the above-mentioned parallel section. In addition, the end of the extension part e1 may be an open end not connected within the wiring layer.

[0200] According to Figure 14 the wiring layout example, in the case where a foreign object is mixed in, before the wirings 11 and 12 of the redundant wiring pair are short-circuited, it is easy for the wiring 11 or the wiring 12 to be short-circuited with the other wiring 21. In other words, the probability that the short circuit of the redundant wiring pair is replaced by other detectable short circuits is high. Thus, it is possible to mitigate the deterioration of soft error tolerance caused by the short circuit of the redundant wiring pair.

[0201] In addition, Figure 14 the wiring 21 of Figure 12 may be, for example, a wiring corresponding to one of the wirings w21 and w22 of

[0202] [7.2.3 The Third Example of the Wiring Layout within the Wiring Layer]

[0203] Figure 15 is a diagram showing the third example of the wiring layout within the wiring layer. This diagram is a diagram schematically enlarging a part of a plurality of wirings formed within one wiring layer. In Figure 15 , the layouts of the wirings 11, 12, and 21 are shown. The v1 in the figure represents a via contact part connecting the wiring 21 to the wiring of another wiring layer.

[0204] The wirings 11 and 12 represent a redundant wiring pair. The wiring 21 is another wiring different from the wirings 11 and 12. The wirings 11 and 12 of the redundant wiring pair have a parallel section configured in parallel within the wiring layer, and sandwich the other wiring 21 throughout the parallel section.

[0205] Figure 15 The wiring layout example of Figure 13 also satisfies the following relationship in the same way.

[0206] The distance a between the wiring 11 and the wiring 12 is larger than the distance b1 between the wiring 11 and the wiring 21.

[0207] The distance a between the wiring 11 and the wiring 12 is larger than the distance b2 between the wiring 12 and the wiring 21.

[0208] In Figure 15 , the wirings 11 and 12 of the redundant wiring pair are configured to sandwich the other wiring 21 throughout the parallel section where the wirings 11 and 12 are configured in parallel. For this purpose, the wiring 21 has extension parts e1 to e3. That is, the wiring 21 includes the extension parts e1 to e3 extending from the vias v1 connected to the main body part of the wiring 21. The extension parts e1 to e3 are a continuous single wiring, and are configured in the wiring layer so as to bypass the end of the wiring 11. A part of the extension part e3 is configured to be sandwiched by the wirings 11 and 12 throughout the parallel section. In addition, the end of the extension part e3 can be an open end not connected in the wiring layer. In addition, Figure 15 the distances b1 and b2 can be the minimum interval between wirings in the design rules of the semiconductor device, respectively. In addition, the distance a between the wiring 11 and the wiring 12 is larger than the minimum interval between wirings in the design rules.

[0209] According to Figure 15 the wiring layout example, in the case where foreign matter is mixed in, before the wirings 11 and 12 as the redundant wiring pair are short-circuited, it is easy for the wiring 11 or the wiring 12 to be short-circuited with the other wiring 21. In other words, the probability that the short circuit of the redundant wiring pair is replaced by other detectable short circuits is high. Thereby, the deterioration of the soft error tolerance caused by the short circuit of the redundant wiring pair can be alleviated.

[0210] In addition, Figure 15 the wiring 21 of Figure 12 can be, for example, a wiring corresponding to one of the wirings w21 and w22 of

[0211] [Example 4 of the wiring layout within the wiring layer]

[0212] Figure 16This is a diagram showing a fourth example of the wiring layout within a wiring layer. This diagram schematically magnifies a part of multiple wirings formed within one wiring layer. In Figure 16 the layout of wirings 11, 12, 21, and 22 is shown. In the figure, v1 represents a via contact portion that connects wiring 21 to the wiring of another wiring layer.

[0213] Wirings 11 and 12 represent a redundant wiring pair. In addition, wirings 21 and 22 represent a redundant wiring pair. The wirings of wirings 11 and 12 are referred to as the first redundant pair, and the wirings of wirings 21 and 22 are referred to as the second redundant pair. In Figure 16 the four wirings 11, 12, 21, and 22 are arranged and configured in the order of wiring 11 on one side of the first redundant pair, wiring 21 on one side of the second redundant pair, wiring 12 on the other side of the first redundant pair, and wiring 22 on the other side of the second redundant pair. That is, the wirings of the two redundant pairs are alternately arranged, and wirings with the same signal level are not adjacent.

[0214] Figure 16 The example of the wiring layout of Figure 13 also satisfies the following relationship in the same way.

[0215] The distance a between wiring 11 and wiring 12 is greater than the distance b1 between wiring 11 and wiring 21.

[0216] The distance a between wiring 11 and wiring 12 is greater than the distance b2 between wiring 12 and wiring 21.

[0217] Figure 16 The wirings 11, 12, 21, and 22 of

[0218] can each be the main part of the wiring or an extended part. Figure 16 According to the example of the wiring layout of

[0219] in the case where foreign matter is mixed in, before wirings 11 and 12 as a redundant wiring pair are short-circuited, wiring 11 or wiring 12 is likely to be short-circuited with other wiring 21 or wiring 22. In other words, the probability that the short circuit of the redundant wiring pair is replaced by other detectable short circuits is relatively high. Thus, it is possible to reduce the deterioration of soft error tolerance caused by the short circuit of the redundant wiring pair. Figure 16 Figure 12 In addition, it can be that the wirings 11 and 12 of Figure 12 are wirings corresponding to the wirings w11 and w12 of

[0220] Figure 12 [7.2.5 Fifth Example of Wiring Layout within a Wiring Layer]

[0221] Figure 17This is a diagram showing the fifth example of the wiring layout within a wiring layer. This diagram schematically enlarges a part of the multiple wirings formed within one wiring layer. In Figure 17 the layouts of wirings 11, 12, and 21 are shown. In the figure, v1 and v2 represent via contact parts that connect wiring 21 to the wirings of other wiring layers. e1 refers to an extension part of wiring 21.

[0222] Wirings 11 and 12 represent a redundant wiring pair. Wiring 21 is a wiring different from wirings 11 and 12. The redundant wiring pair of wirings 11 and 12 has a parallel section configured in parallel within the wiring layer, and wiring 21 is sandwiched therebetween throughout this parallel section.

[0223] Figure 17 The wiring layout example of Figure 13 similarly satisfies the following relationships.

[0224] The distance a between wiring 11 and wiring 12 is greater than the distance b1 between wiring 11 and wiring 21.

[0225] The distance a between wiring 11 and wiring 12 is greater than the distance b2 between wiring 12 and wiring 21.

[0226] In Figure 17 the redundant wiring pair of wirings 11 and 12 is configured to sandwich wiring 21 throughout the parallel section where wirings 11 and 12 are configured in parallel. For this reason, wiring 21 has an extension part e1. That is, wiring 21 includes an extension part e1 extending from the main body part of wiring 21. This extension part e1 is configured between wiring 11 and wiring 12 within the above-mentioned parallel section. In addition, the end of the extension part e1 can be an open end that is not connected within the wiring layer.

[0227] According to Figure 17 the wiring layout example, in the case of foreign matter intrusion, compared with the short circuit between the redundant wiring pair of wirings 11 and 12, the short circuit between wiring 11 or wiring 12 and other wiring 21 is more likely to occur. In other words, the probability of replacing the short circuit of the redundant wiring pair with other detectable short circuits is high. Thereby, the degradation of soft error tolerance caused by the short circuit of the redundant wiring pair can be mitigated.

[0228] In addition, Figure 17 wiring 21 of Figure 12 can be, for example, a wiring corresponding to one of wirings w21 and w22 of

[0229] [7.2.6 Sixth Example of Wiring Layout within a Wiring Layer]

[0230] Figure 18 This is a diagram showing the sixth example of the wiring layout within a wiring layer. This diagram is the same asFigure 17 In contrast, the main body of the wiring 21 belongs to another wiring layer, and the extension part e1 extends from the main body of the wiring 21 via the through hole v3. Hereinafter, the differences will be mainly described.

[0231] As shown by the dashed line in the figure, the main body of the wiring 21 belongs to another wiring layer different from the wiring layer to which the wirings 11 and 12 belong.

[0232] The extension part e1 extends from the main body of the wiring 21 belonging to another wiring layer via the through hole v3. As a result, the wirings 11 and 12 of the redundant wiring pair have a parallel section arranged in parallel within the wiring layer, and the extension part e1 of the other wiring 21 is sandwiched across this parallel section.

[0233] According to Figure 18 the wiring layout example, similar to Figure 17 it is possible to reduce the degradation of soft error tolerance caused by the short circuit of the redundant wiring pair.

[0234] [7.2.7 The 7th example of the wiring layout within the wiring layer]

[0235] Figure 19 is a diagram showing the 7th example of the wiring layout within the wiring layer. The difference between this diagram and Figure 14 is that a power supply wiring is added. Hereinafter, the differences will be mainly described.

[0236] The wiring 21 is a power supply wiring and has extension parts e1 and e2 extending from the main body of the power supply wiring. The power supply wiring can be, for example, a wiring arranged in the wiring layer so as to surround all or a part of the latch circuit L1, or a shielding wiring formed in another wiring layer.

[0237] According to Figure 19 the wiring layout example, similar to Figure 14 it is possible to reduce the degradation of soft error tolerance caused by the short circuit of the redundant wiring pair.

[0238] [7.2.8 The 8th example of the wiring layout within the wiring layer]

[0239] Figure 20 is a diagram showing the 8th example of the wiring layout within the wiring layer. This diagram is a schematic enlarged view of a part of the multiple wirings formed within one wiring layer. The layouts of the wirings 11, 12, 21, and 22 are shown in Figure 20 . In the figure, v1 represents a via contact part connecting the wiring 21 to a wiring in another wiring layer. v2 represents a via contact part connecting the wiring 22 to a wiring in another wiring layer. e1 represents an extension part of the wiring 21. e2 represents an extension part of the wiring 22.

[0240] The wirings 11 and 12 represent a redundant wiring pair. The wiring 21 is another wiring different from the wirings 11 and 12. The wiring 22 is yet another wiring different from the wirings 11 and 12. The wirings 21 and 22 are not a redundant wiring pair. The wirings 11 and 12 of the redundant wiring pair have a parallel section configured in parallel within the wiring layer, and sandwich the other wiring 21 and the yet other wiring 22 over most of the parallel section. The other wiring 21 and the yet other wiring 22 are arranged on the same straight line with a spacing d1 therebetween.

[0241] Figure 20 The wiring layout example of Figure 13 similarly satisfies the following relationship.

[0242] The distance a between the wiring 11 and the wiring 12 is greater than the distance b1 between the wiring 11 and the wiring 21 or the wiring 22.

[0243] The distance a between the wiring 11 and the wiring 12 is greater than the distance b2 between the wiring 12 and the wiring 21 or the wiring 22.

[0244] Furthermore, in Figure 20 , the distance a between the wiring 11 and the wiring 12 is greater than the distance d1 between the wiring 21 and the wiring 22. In other words, the distance d1 of the section where the wiring 11 and the wiring 12 are adjacent and parallel (i.e., the section without sandwiching other wirings) is smaller than the distance a between the wiring 11 and the wiring 12.

[0245] In Figure 20 , the wirings 11 and 12 of the redundant wiring pair are configured to sandwich the wiring 21 or the wiring 22 over most of the parallel section where the wiring 11 and the wiring 12 are configured in parallel. For this reason, the wiring 21 has an extension part e1, and the wiring 22 has an extension part e2. That is, the ends of the extension parts e1 and e2 can be open ends not connected within the wiring layer.

[0246] According to Figure 20 the wiring layout example, similar to Figure 14 , it is possible to mitigate the degradation of soft error tolerance caused by a short circuit of the redundant wiring pair.

[0247] In addition, Figure 20 the wiring 21 of

[0248] can be, for example, a power supply line or a ground line. The wiring 22 can also be, for example, a power supply line or a ground line. Figures 13 - 20 shows an example of the configuration layout of a redundant wiring pair within one wiring layer. Hereinafter, the configuration layout of a redundant wiring pair in different wiring layers will be described.

[0249] [7.3.1 First Example of Wiring Layout between Wiring Layers]

[0250] Figure 21 This is a diagram showing the first example of the wiring layout between wiring layers. Diagram (a) of this figure shows the wiring layout obtained by a plan view of a semiconductor substrate on which a latch circuit L1 is formed. Diagram (b) of this figure shows a cross-section taken along line A-A of (a), including three wiring layers M1 to M3. This figure is a diagram in which a part of the wiring formed in the wiring layers M1 to M3 and associated with a redundant wiring pair is schematically enlarged. In Figure 21 the wiring 11 and the wiring 12 representing the redundant wiring pair are shown.

[0251] As Figure 21 shown, the wiring 11 and the wiring 12 of the redundant wiring pair belong to different wiring layers. That is, the wiring 11 belongs to the wiring layer M3, and the wiring 12 belongs to the wiring layers M2 and M1 and includes via contact portions.

[0252] The redundant wiring pairs in different wiring layers are arranged in such a way as to satisfy the following relationship. That is, when the wiring layers of the wiring 11 and the wiring 12 are different, the distance a between the wiring 11 and the wiring 12 is larger than the interlayer distance c between adjacent wiring layers. In this figure, three distances a1, a2, and a3 are described as the distance between the wiring 11 and the wiring 12, but the distance a between the wiring 11 and the wiring 12 is the smallest a1 or a3. The wiring 11 and the wiring 12 are arranged in such a way as to satisfy a > c.

[0253] More specifically, in Figure 21 in the plan view of the semiconductor device, the wiring 11 and the wiring 12 have an overlapping portion and cross each other. The wiring 12 has a first partial wiring 12b corresponding to the overlapping portion, a second partial wiring 12a connected to one end of the first partial wiring 12b, and a third partial wiring 12c connected to the other end of the first partial wiring 12b. The first partial wiring 12b belongs to the wiring layer M1. The second partial wiring 12a and the third partial wiring 12c belong to a wiring layer M2 different from the wiring layer M1 and are connected to the first partial wiring 12b via via contact portions v1 and v2. The wiring 11 belongs to the wiring layer M3, which is farther from the wiring layer M1 than the wiring layer M2. With this configuration layout, it is possible to easily satisfy the above relationship (i.e., a > c). In Figure 21 it is configured such that the distance a2 between the wiring 11 and the wiring 12 in the overlapping portion satisfies twice or more the interlayer distance c.

[0254] According to Figure 21 the configuration layout, it is possible to mitigate the degradation of soft error tolerance caused by the short circuit of the redundant wiring pair. This is because, when foreign matter of a size similar to the interlayer distance c is mixed in, it is not easy for the wiring 11 and the wiring 12 to be short-circuited. Thus, the occurrence of a short circuit in the redundant wiring pair is suppressed.

[0255] In addition, Figure 21As long as the wiring layers M1 to M3 are in this configuration order, any three of the multiple wiring layers may be used. However, the interlayer distance c is not limited to Figure 21 the distance between the wiring layer M2 and the wiring layer M3, which is the minimum distance between two adjacent wiring layers.

[0256] [7.3.2 Second Example of Wiring Layout between Wiring Layers]

[0257] Figure 22A is a diagram showing a second example of the wiring layout between wiring layers. In the plan view (a) of this diagram, the wiring layout obtained by observing the semiconductor substrate on which the latch circuit L1 is formed is shown. The cross-section along line B-B of (a) in this diagram is shown in (b), including two wiring layers M2 and M3. This diagram is a diagram schematically enlarging the part related to the redundant wiring pair among the wirings formed in the wiring layers M2 and M3. In Figure 22A , wirings 11 and 12 representing the redundant wiring pair are shown.

[0258] In the plan view (a) of this diagram, the wiring 12 is arranged to bypass the end of the wiring 11 so that the wirings 11 and 12 do not overlap.

[0259] With this configuration layout, it is possible to easily satisfy the above relationship (i.e., a > c).

[0260] According to Figure 22A the configuration layout, it is possible to reduce the degradation of soft error tolerance caused by the short circuit of the redundant wiring pair. This is because, when foreign matter of a size similar to the interlayer distance c is mixed in, it is less likely that the wirings 11 and 12 will short-circuit. Thus, the occurrence of short circuits in the redundant wiring pair is suppressed.

[0261] [7.3.3 Variant of the Second Example of Wiring Layout between Wiring Layers]

[0262] Figure 22B is a diagram showing a variant of the second example of the wiring layout between wiring layers. The difference between this diagram and Figure 22A is that it has a wiring 31. Hereinafter, the description will focus on the differences. The wiring 31 is arranged near the wiring 11 or the wiring 12 and includes a via contact portion v1 and an extension portion e1. The via contact portion v1 connects the portion of the wiring 31 in another wiring layer M4 to the wiring 31 in the wiring layer M3. The extension portion e1 extends from the via contact portion v1. In addition, the following extension rule may be set. That is, the length e1 from the via v1 to the end of the extension portion e1 is larger than the minimum size of the wiring in the design rules of the semiconductor device. Also, this extension rule may be applied to the extension portions in other diagrams.

[0263] In Figure 22BIn [the figure], the extension e1 of the wiring 31 is configured to be adjacent to one of the wirings of the redundant wiring pair within the same wiring layer and adjacent to the other wiring between different wiring layers. In addition, the distance a is greater than the distance between the wiring 11 and the wiring 31 and greater than the distance between the wiring 12 and the wiring 31.

[0264] According to the wiring design CAD, if it is desired to implement without the wiring 31 Figure 22A , there are cases where there are limitations such that only a minimum amount of wiring must be used between the redundant pairs, and there are cases where layout is difficult. If the wiring 31 is appropriately arranged near the wiring 11 or the wiring 12, the configuration of the redundant wiring pair can be easily designed. As a result, it is possible to easily implement Figure 22B such a layout of the redundant wiring pair.

[0265] [7.4 Other Circuit Examples of the Semiconductor Device]

[0266] Next, other circuit examples having a redundant wiring pair will be described.

[0267] Figure 23 is a diagram showing other circuit examples formed in the semiconductor device of Embodiment 1. The semiconductor device of this diagram shows a structural example of a BISER (Built in Soft Error Resilience) type flip-flop circuit as a circuit having soft error tolerance.

[0268] The flip-flop circuit of this diagram includes a delay circuit DL, an inverter IV, master latches ML0, ML1, a master C element CM, slave latches SL0, SL1, a slave C element CS, a master weak hold circuit WM, and a slave weak hold circuit WS, and has a dual master-slave structure. Figure 23 The redundant wiring pair in [the figure] is the wiring connected to the output Qn of the slave latch SL0 and the wiring connected to the output Qn of the slave latch SL1.

[0269] The delay circuit DL delays the input data D input to the master latch ML0 by the time τ and outputs it to the master latch ML1.

[0270] The inverter IV outputs a clock signal Cn obtained by inverting the clock signal Cp.

[0271] The master latch ML0 synchronizes with the clock signal Cp and the clock signal Cn, latches the input data D, and outputs the data Qp. The output data Qp is a non-inverted output data having the same logic level as the data D.

[0272] The master latch ML1 synchronizes with the clock signal Cp and the clock signal Cn, latches the delayed input data D, and outputs the data Qp. The output data Qp is a non-inverted output data having the same logic level as the data D.

[0273] The main C element CM is a 2-input and 1-output inverter circuit. When the two inputs are at a certain same logic level, it outputs the inverted level of that logic level. When the two inputs are not at a certain same logic level, it becomes high impedance.

[0274] The main weak hold circuit WM is a Weak Keeper circuit that holds the logic level output by the main C element CM. When the output of the main C element CM is high impedance, it outputs the logic level held just before becoming high impedance.

[0275] The sub-latch SL0 is synchronized with the clock signal Cp and the clock signal Cn, latches the input data D, and outputs the data Qn. The output data Qn is the data with the logic level of the inverted data D.

[0276] The sub-latch SL1 is synchronized with the clock signal Cp and the clock signal Cn, latches the input data D, and outputs the data Qn. The output data Qn is the data of the inverted data D.

[0277] The sub-C element CS is a 2-input and 1-output inverter circuit. When the two inputs are at a certain same logic level, it outputs the inverted logic level of that logic level. When the two inputs are not at a certain same logic level, it becomes high impedance. In Figure 24 shows a circuit example of the sub-C element CS. The sub-C element CS in this figure is composed of two PMOS transistors and two NMOS transistors. The two PMOS transistors and the two NMOS transistors are connected in series. In addition, the main C element CM can also be the same as Figure 24 the same.

[0278] The sub-weak hold circuit WS is a Weak Keeper circuit that holds the same logic level as the logic level output by the sub-C element CS. When the output of the sub-C element CS is high impedance, it outputs the logic level held just before becoming high impedance.

[0279] In such a flip-flop circuit, assuming that one of the two sets of master-slave latches is flipped due to a soft error, the output of the main C element CM or the sub-C element CS becomes high impedance, but the correct data can be maintained by the logic level held by the main weak hold circuit WM or the sub-weak hold circuit WS.

[0280] Figure 23 The redundant wiring pairs in the flip-flop circuit of include: the wiring connecting the output terminal of the sub-latch SL0 to one of the two input terminals of the sub-C element CS, and the wiring connecting the output terminal of the sub-latch SL1 to the other of the two input terminals of the sub-C element CS. In other words, the output wiring of the sub-latch SL0 and the output wiring of the sub-latch SL1 are redundant wiring pairs.

[0281] The wiring pair satisfies the relationship of the configuration layout described in Figures 13 - 22B . Thereby, it is possible to reduce the degradation of soft error tolerance caused by the short circuit of the redundant wiring pair in the Figure 23 flip-flop circuit.

[0282] In addition, Figure 23 the output wiring of the master latch ML0 and the output wiring of the master latch ML1 in Figures 13 - 22B can also be processed in the same manner as the redundant wiring pair. That is, the relationship of the configuration layout described in

[0283] can also be satisfied. The input data D of the master latch ML1 is delayed by a time τ compared to the input data D of the master latch ML0. Accordingly, the output data Qp of the master latch ML1 is delayed by a time τ compared to the output data Qp of the master latch ML0. In this specification, it is defined that "the redundant wiring pair is independent wiring that becomes the same signal level but is not connected to each other". The output wiring of the master latch ML0 and the output wiring of the master latch ML1 do not satisfy this definition. However, problems such as the wiring short circuit shown in Figure 25 may occur in the output wiring of the master latch ML0 and the output wiring of the master latch ML1. In addition, except for the delay time τ, it generally conforms to the definition of the redundant wiring pair. Therefore, by satisfying the relationship of the configuration layout described in Figures 13 - 22B , the output wiring of the master latch ML0 and the output wiring of the master latch ML1 can reduce the degradation of soft error tolerance.

[0284] In addition, in the embodiment, as an example of the redundant wiring pair, a duplication example is shown, but a combination of two wirings among multiple wirings of triple or more duplications can also be regarded as a wiring pair respectively. In this case, it is sufficient that the two wirings regarded as the wiring pair satisfy the relationship of the configuration layout described in Figures 13 - 22B .

[0285] As described above, the semiconductor device of the embodiment includes: a first wiring 11; a second wiring 12 that is not connected to the first wiring 11 and is provided to transmit the same signal level as the first wiring 11; and other wirings 21 and 22 that are different from the first wiring 11 and the second wiring 12. In the wiring layer, the distance a between the first wiring 11 and the second wiring 12 is larger than the distances b1 and b3 between the first wiring 11 and the other wirings 21 and 22, and is larger than the distances b2 or b4 between the second wiring 12 and the other wirings 21 or 22.

[0286] Accordingly, it is possible to reduce the degradation of soft error tolerance caused by the short circuit of redundant wiring pairs. This is because, when foreign matter of a size similar to the distance between wirings is mixed in, a short circuit between the first wiring and the second wiring is less likely to occur than a short circuit between the first wiring or the second wiring and other wirings. As a result, the occurrence of undetectable short circuits is suppressed, in other words, the occurrence of short circuits of redundant wiring pairs is suppressed.

[0287] Here, it may be that the first wiring 11 and the second wiring 12 have a parallel section arranged in parallel in the wiring layer, and other wirings 21 and 22 are sandwiched in the parallel section.

[0288] Here, it may be that the other wirings 21 and 22 include extension parts e1 extending from the main body parts of the other wirings 21 and 22 in the wiring layer, and the extension parts e1 are sandwiched between the first wiring 11 and the second wiring 12 in the parallel section in the wiring layer.

[0289] Here, it may be that the other wirings 21 and 22 include extension parts e1 extending from vias connected to the main body parts of the other wirings 21 and 22, and the extension parts e1 are sandwiched between the first wiring 11 and the second wiring 12 in the parallel section in the wiring layer.

[0290] Here, it may be that the other wirings 21 and 22 have extension parts e1 branching and extending from the main body parts of the other wirings 21 and 22 in the wiring layer, and the extension parts e1 are sandwiched between the first wiring 11 and the second wiring 12 in the parallel section in the wiring layer.

[0291] Here, it may be that the ends of the extension parts e1 are open ends not connected in the wiring layer.

[0292] Here, it may be that the extension parts e1 to e3 bypass the end of the first wiring 11 in the wiring layer and are further arranged throughout the parallel section.

[0293] Here, it may further include: a third wiring; and a fourth wiring that is not connected to the first wiring 11 and is provided to transmit the same signal level as the third wiring; and the other wiring 21 or 22 is the third wiring.

[0294] Here, it may be that a part of the first wiring 11 to the fourth wiring is arranged in the order of the first wiring 11, the third wiring, the second wiring 12, and the fourth wiring in the wiring layer.

[0295] Accordingly, they are arranged in the order of one wiring of the first redundant pair, one wiring of the second redundant pair, the other wiring of the first redundant pair, and the other wiring of the second redundant pair, so it is possible to prevent or reduce the short circuit of the redundant pair.

[0296] Here, it is possible that the through hole connects the extending portion to the main bodies of other wirings 21 and 22 in a wiring layer different from the above-mentioned wiring layer.

[0297] Here, it is possible that the length of the extending portion e1 is larger than the minimum size of the design rule of the semiconductor device.

[0298] Here, it is possible that the first wiring 11 and the second wiring 12 include an interval where they are arranged in parallel in the wiring layer in such a manner as to sandwich other wirings 21 and 22 and still other wirings 21 and 22, and the distance d1 between the other wirings 21 and 22 and the still other wirings 21 and 22 within the interval is smaller than the distance between the first wiring 11 and the second wiring 12.

[0299] Here, the first wiring 11 and the second wiring 12 can be components of a DICE (Dual Interlocked storage Cell) latch circuit.

[0300] Here, the first wiring 11 and the second wiring 12 can be components of a BISER (Built in Soft Error Resiliency) flip-flop circuit.

[0301] In addition, it is possible that the semiconductor device of the embodiment includes: a plurality of wiring layers; a first wiring 11; and a second wiring 12 that is not connected to the first wiring 11 and is provided to transmit the same signal level as the first wiring 11; the first wiring 11 and the second wiring 12 belong to different wiring layers; and the distance a1 between the first wiring 11 and the second wiring 12 is larger than the interlayer distance c between adjacent wiring layers.

[0302] Thereby, it is possible to mitigate the degradation of soft error tolerance caused by the short circuit of the redundant wiring pair. This is because, when foreign matter having a size similar to the distance between wirings is mixed in, it is less likely to occur a short circuit between the first wiring and the second wiring. In other words, the occurrence of the short circuit of the redundant wiring pair is suppressed.

[0303] Here, it is possible that in the plan view of the semiconductor device, the first wiring 11 and the second wiring 12 have an overlapping portion, and the distance between the first wiring 11 and the second wiring 12 in the overlapping portion is 2 times or more the interlayer distance c.

[0304] Here, it may be that in a plan view of the semiconductor device, the first wiring 11 and the second wiring 12 cross at an overlapping portion; the second wiring 12 has: a first partial wiring 12b corresponding to the overlapping portion; a second partial wiring 12a connected to one end of the first partial wiring 12b; and a third partial wiring 12c connected to the other end of the first partial wiring 12b; the first partial wiring 12b belongs to the first wiring layer M1; the second partial wiring 12a and the third partial wiring 12c belong to a second wiring layer M2 different from the first wiring layer M1 and are connected to the first partial wiring 12b via via contact portions v1, v2; the first wiring 11 belongs to a third wiring layer M3 that is farther from the first wiring layer M1 than the second wiring layer M2.

[0305] Here, it may be that the second wiring 12 is arranged so as to bypass the end portion of the first wiring 11 so that the first wiring 11 and the second wiring 12 do not overlap in a plan view of the semiconductor integrated circuit.

[0306] Here, it may be that there is also provided a third wiring 31 that is opposed to at least one of the first wiring 11 and the second wiring 12 between wiring layers or within a wiring layer; the third wiring 31 has an extension portion e1 extending from a via.

[0307] Here, it may be that the length of the extension portion e1 is larger than the minimum dimension of the design rule of the semiconductor device.

[0308] As described above, multiple embodiments have been illustrated, but it is also possible to combine the constituent elements in these embodiments to obtain a new embodiment. In addition, even if other circuits are used instead of the inverter and the 2-input NAND, as long as the circuit has a function in which the input and output have an inverted relationship, the specific circuit structure is not limited and it can be regarded as an inverter.

[0309] As described above, the semiconductor device of one or more technical solutions has been described based on the embodiments, but the present invention is not limited to this embodiment. As long as it does not deviate from the gist of the present invention, various modified forms conceived by those skilled in the art applied to this embodiment, or forms constructed by combining the constituent elements of different embodiments can also be included within the scope of one or more technical solutions.

[0310] Industrial Applicability

[0311] As described above, since the semiconductor device of the present invention can realize a semiconductor device with high soft error tolerance in a small area, it is useful as a semiconductor integrated circuit or the like mounted in an electronic device such as a vehicle-mounted device that is required to operate stably in a small area.

[0312] Reference Numeral Explanation

[0313] Wn1 N-well region

[0314] Wp1, Wp2 P-well regions

[0315] p1, p2, p3, p4 drain nodes

[0316] p11, p21, p31, p41 drain nodes

[0317] p12, p22, p32, p42 drain nodes

[0318] pt1 to pt4 PMOS transistors

[0319] pt11, pt21, pt31, pt41 PMOS transistors

[0320] pt12, pt22, pt32, pt42 PMOS transistors

[0321] 101, 104, 111 PMOS transistors

[0322] n11, n21, n31, n41 drain nodes

[0323] n12, n22, n32, n42 drain nodes

[0324] nt1 to nt4 NMOS transistors

[0325] nt11, nt21, nt31, nt41 NMOS transistors

[0326] nt12, nt22, nt32, nt42 NMOS transistors

[0327] 102, 105, 112 NMOS transistors

[0328] g1, g2, g3, g4 gates

[0329] g11, g21, g31, g41 gates

[0330] g12, g22, g32, g42 gates

[0331] gck, gr common gates

[0332] i1 to i8 the 1st to the 8th flip circuits

[0333] CK clock input signal

[0334] CKI, CKIN clock signals

[0335] D data input signal

[0336] S1, S2 switch circuits

[0337] Q output signal

[0338] R reset input signal

[0339] Id data input circuit

[0340] Ick clock input circuit

[0341] O1 output circuit

[0342] L1, L2 latch circuit

[0343] F1 flip-flop circuit

Claims

1. A semiconductor device, characterized in that, it includes: A first latch circuit, composed of first to fourth inverter circuits; First and second first-type well regions; and A second-type well region; The above-mentioned first to fourth inverter circuits respectively have: A first-type MOS transistor; A second-type MOS transistor; And An output node, connected to the drain of the above-mentioned first-type MOS transistor and the drain of the above-mentioned second-type MOS transistor; The output node of the above-mentioned first inverter circuit is connected to the gate of the first-type MOS transistor of the above-mentioned second inverter circuit and the gate of the second-type MOS transistor of the above-mentioned fourth inverter circuit; The output node of the above-mentioned second inverter circuit is connected to the gate of the first-type MOS transistor of the above-mentioned third inverter circuit and the gate of the second-type MOS transistor of the above-mentioned first inverter circuit; The output node of the above-mentioned third inverter circuit is connected to the gate of the first-type MOS transistor of the above-mentioned fourth inverter circuit and the gate of the second-type MOS transistor of the above-mentioned second inverter circuit; The output node of the above-mentioned fourth inverter circuit is connected to the gate of the first-type MOS transistor of the above-mentioned first inverter circuit and the gate of the second-type MOS transistor of the above-mentioned third inverter circuit; The drains of the first-type MOS transistors of the above-mentioned first to fourth inverter circuits are respectively arranged in the above-mentioned second-type well region; The drains of the second-type MOS transistors of the above-mentioned first and second inverter circuits are respectively arranged in the above-mentioned first first-type well region; The drains of the second-type MOS transistors of the above-mentioned third and fourth inverter circuits are respectively arranged in the second first-type well region; The above-mentioned second-type well region is arranged between the above-mentioned first first-type well region and the above-mentioned second first-type well region; In a plan view, the distance between the drain of the first-type MOS transistor of the above-mentioned first inverter circuit and the drain of the first-type MOS transistor of the above-mentioned third inverter circuit is greater than the distance between the drain of the first-type MOS transistor of the above-mentioned first inverter circuit and the drain of the first-type MOS transistor of the above-mentioned fourth inverter circuit; The above-mentioned semiconductor device has a second latch circuit composed of fifth to eighth inverter circuits at the subsequent stage of the above-mentioned first latch circuit; The above-mentioned fifth to eighth inverter circuits respectively have: A first-type MOS transistor; A second-type MOS transistor; and An output node, connected to the drain of the above-mentioned first-type MOS transistor and the drain of the above-mentioned second-type MOS transistor; The output node of the above-mentioned fifth inverter circuit is connected to the gate of the first-type MOS transistor of the above-mentioned sixth inverter circuit and the gate of the second-type MOS transistor of the above-mentioned eighth inverter circuit; The output node of the above-mentioned sixth inverter circuit is connected to the gate of the first-type MOS transistor of the above-mentioned seventh inverter circuit and the gate of the second-type MOS transistor of the above-mentioned fifth inverter circuit; The output node of the above-mentioned seventh inverter circuit is connected to the gate of the first-type MOS transistor of the above-mentioned eighth inverter circuit and the gate of the second-type MOS transistor of the above-mentioned sixth inverter circuit; The output node of the above-mentioned eighth inverter circuit is connected to the gate of the first-type MOS transistor of the above-mentioned fifth inverter circuit and the gate of the second-type MOS transistor of the above-mentioned seventh inverter circuit; The drains of the first-type MOS transistors of the fifth to eighth flip circuits are respectively disposed in the second-type well region; The drains of the second-type MOS transistors of the fifth and sixth flip circuits are respectively disposed in the first first-type well region; The drains of the second-type MOS transistors of the seventh and eighth flip circuits are respectively disposed in the second first-type well region; In a plan view, the distance between the drain of the first-type MOS transistor of the fifth flip circuit and the drain of the first-type MOS transistor of the seventh flip circuit is greater than the distance between the drain of the first-type MOS transistor of the fifth flip circuit and the drain of the first-type MOS transistor of the eighth flip circuit; In a plan view, the drain closest to the drain of the first-type MOS transistor of the first flip circuit among the drains of the first-type MOS transistors of the first to eighth flip circuits is included in the seventh flip circuit; In a plan view, the drain closest to the drain of the first-type MOS transistor of the second flip circuit among the drains of the first-type MOS transistors of the first to eighth flip circuits is included in the eighth flip circuit.

2. The semiconductor device according to claim 1, wherein, the first and second first-type well regions are P-type wells; the second-type well region is an N-type well.

3. The semiconductor device according to claim 1 or 2, wherein, In a plan view, the distance between the drain of the first-type MOS transistor of the second flip circuit and the drain of the first-type MOS transistor of the fourth flip circuit is greater than the distance between the drain of the first-type MOS transistor of the second flip circuit and the drain of the first-type MOS transistor of the third flip circuit, and is greater than the distance between the drain of the first-type MOS transistor of the third flip circuit and the drain of the first-type MOS transistor of the fourth flip circuit.

4. The semiconductor device according to claim 1, wherein, In a plan view, the drain closest to the drain of the first-type MOS transistor of the third flip circuit among the drains of the first-type MOS transistors of the first to eighth flip circuits is included in the fifth flip circuit; In a plan view, the drain closest to the drain of the first-type MOS transistor of the fourth flip circuit among the drains of the first-type MOS transistors of the first to eighth flip circuits is included in the sixth flip circuit.

5. The semiconductor device according to claim 1, wherein, in the semiconductor device, at least one of the first to eighth flip circuits is a clocked flip circuit with a clock signal as an input.

6. The semiconductor device according to claim 1, wherein, in the semiconductor device, at least one of the first to eighth flip circuits is a NAND-type flip circuit with a reset signal or a set signal as an input.

7. The semiconductor device according to claim 1, wherein, the semiconductor device includes a data input circuit and a clock input circuit; The above data input circuit is an inverter circuit including at least one first-type MOS transistor; The above clock input circuit includes two-stage inverter circuits; The above two-stage inverter circuits include at least one first-type MOS transistor; One of the drain of the above first-type MOS transistor of the above data input circuit and the drain of the above first-type MOS transistor of the above clock input circuit is arranged and configured in the first direction with the drain of the first-type MOS transistor of the above first flip-flop circuit and the drain of the above first-type MOS transistor of the second flip-flop circuit; The other of the drain of the above first-type MOS transistor of the above data input circuit and the drain of the above first-type MOS transistor of the above clock input circuit is arranged and configured in the above first direction with the drain of the first-type MOS transistor of the above third flip-flop circuit and the drain of the above first-type MOS transistor of the fourth flip-flop circuit.

Images