A test circuit and test method for mainboard function module

Abstract

This invention relates to the field of circuit technology, specifically to a test circuit and test method for a motherboard functional module. The test circuit includes a motherboard and a test board. A first processor controls a second control switch to turn on, thereby controlling the first control switch to turn on, so as to output the supply voltage from the first power supply terminal to the second power supply terminal, and provide the supply voltage to the load through the supply voltage from the second power supply terminal. The second processor responds to the interrupt prompt information sent by the ADC detection chip, obtains the ADC value read by the ADC detection chip, and determines the input voltage of the first resistor based on the voltage value of the first ADC interface and the output voltage of the first resistor based on the voltage value of the second ADC interface. The voltage, current and power of the load are calculated based on the input voltage and output voltage of the first resistor. This invention can test the power of each load in the motherboard individually.

Description

Technical Field

[0001] The present invention relates to the field of circuit technology, and in particular to a test circuit for a mainboard functional module and a test method thereof. Background Art

[0002] In the existing motherboard test production line, only the input power of the motherboard can be tested, but there is no way to test the functions of each load in the motherboard. For example, if there is a USB device on the motherboard and the USB device is turned on, only the change in the total input power can be tested, and the power of each load in the motherboard cannot be tested separately.

[0003] Therefore, it is necessary to provide a test circuit for a mainboard functional module that can test the power of each load in the mainboard. Summary of the invention

[0004] The purpose of the present invention is to provide a test circuit and a test method for a mainboard functional module to solve one or more technical problems existing in the prior art and at least provide a beneficial choice or create conditions.

[0005] In order to achieve the above object, the present invention provides the following technical solutions:

[0006] In a first aspect, an embodiment of the present invention provides a test circuit for a mainboard functional module, comprising: a mainboard and a test board;

[0007] The mainboard is provided with a first processor, a first control switch, a second control switch, a load, and a mainboard side access point group; the mainboard side access point group includes a first mainboard access point, a second mainboard access point, a third mainboard access point, and a fourth mainboard access point; wherein the input end of the first control switch is connected to the first power supply end, the output end of the first control switch is connected to the second power supply end, the control end of the first control switch is connected to the control end of the second control switch, the first processor is connected to the input end of the second control switch, and the second power supply end is connected to the load; the first mainboard access point is arranged between the first control switch and the first power supply end, the second mainboard access point is arranged between the first control switch and the second power supply end, the third mainboard access point is arranged between the first processor and the second control switch, and the fourth mainboard access point is grounded;

[0008] The test board is provided with a second processor, an ADC detection chip, and a test side access point group; the test side access point group includes a first test access point, a second test access point, a third test access point, and a fourth test access point; wherein the second processor is connected to the ADC detection chip via an I2C interface, the ADC detection chip is connected to the first test access point via a first ADC interface, the ADC detection chip is connected to the second test access point via a second ADC interface, and the third test access point and the fourth test access point are both grounded;

[0009] A first resistor is connected between the first ADC interface and the second ADC interface;

[0010] The first processor is used to control the second control switch to be turned on, thereby controlling the first control switch to be turned on, so as to output the power supply voltage of the first power supply end to the second power supply end, and provide the power supply voltage for the load through the power supply voltage of the second power supply end;

[0011] The second processor is used to respond to the interrupt prompt information sent by the ADC detection chip, and obtain the ADC value read by the ADC detection chip; the ADC value includes: the voltage value of the first ADC interface and the voltage value of the second ADC interface;

[0012] And it is used to determine the input voltage of the first resistor according to the voltage value of the first ADC interface, and determine the output voltage of the first resistor according to the voltage value of the second ADC interface; and calculate the voltage, current and power of the load according to the input voltage and output voltage of the first resistor.

[0013] As a further improvement of the above technical solution, the first control switch is a PMOS transistor, and the second control switch is an NPN transistor;

[0014] The source of the PMOS tube is connected to the first power supply terminal, the drain of the PMOS tube is connected to the second power supply terminal, the gate of the PMOS tube is connected to the collector of the NPN transistor, the processor is connected to the base of the NPN transistor, and the emitter of the NPN transistor is grounded;

[0015] The first mainboard access point is arranged between the source of the PMOS tube and the first power supply terminal, the second mainboard access point is arranged between the drain of the PMOS tube and the second power supply terminal, and the third mainboard access point is arranged between the first processor and the base of the NPN transistor.

[0016] As a further improvement of the above technical solution, the second processor is also connected to a display screen, and the display screen is used to display the voltage, current and power of the load processed by the second processor.

[0017] As a further improvement of the above technical solution, the ADC detection chip adopts a chip model INA226, the VBUS pin of the ADC detection chip is connected to the IN+ pin of the ADC detection chip, and the VBUS pin and IN+ pin of the ADC detection chip are commonly connected to the first test access point; the IN- pin of the ADC detection chip is connected to one end of the first resistor, and the IN+ pin of the ADC detection chip is connected to the other end of the first resistor.

[0018] As a further improvement of the above technical solution, the resistance of the first resistor is 50mR, a second resistor is arranged between the first motherboard access point and the collector of the second control switch, and the resistance of the second resistor is 47KΩ; a third resistor is arranged between the third motherboard access point and the first processor, and the resistance of the third resistor is 1KΩ.

[0019] In a second aspect, an embodiment of the present invention further provides a method for testing a test circuit of a mainboard functional module, which is applied to the test circuit of any mainboard functional module described in the first aspect, and includes:

[0020] Step S100, the first processor controls the second control switch to be turned on, thereby controlling the first control switch to be turned on, so as to output the power supply voltage of the first power supply end to the second power supply end, and provide the power supply voltage for the load through the power supply voltage of the second power supply end;

[0021] Step S200, the second processor responds to the interrupt prompt information sent by the ADC detection chip, and obtains the ADC value read by the ADC detection chip through the I2C interface; the ADC value includes: the voltage value of the first ADC interface and the voltage value of the second ADC interface;

[0022] Step S300, the second processor determines the input voltage of the first resistor according to the voltage value of the first ADC interface, and determines the output voltage of the first resistor according to the voltage value of the second ADC interface; and calculates the voltage, current and power of the load according to the input voltage and output voltage of the first resistor.

[0023] The beneficial effect of the present invention is that the present invention provides a test circuit for a mainboard functional module and a test method thereof, which can individually test the power of each load in the mainboard.

[0024] Other features and advantages of the present invention will be described in the following description, and partly become apparent from the description, or understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained by the structures particularly pointed out in the description, claims and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0026] Figure 1 It is an overall block diagram of a test circuit of a mainboard functional module in an embodiment of the present invention;

[0027] Figure 2 is a schematic diagram of the implementation principle of the test end side in an embodiment of the present invention;

[0028] Figure 3 is a schematic diagram of the implementation principle of the test end side in an embodiment of the present invention;

[0029] Figure 4 It is a flow chart of a testing method of a testing circuit of a mainboard functional module in an embodiment of the present invention. DETAILED DESCRIPTION

[0030] The following will be combined with the embodiments and drawings to clearly and completely describe the concept, specific structure and technical effects of the present invention, so as to fully understand the purpose, scheme and effect of the present invention. It should be noted that the embodiments and features in the embodiments of this application can be combined with each other without conflict.

[0031] In the description of the present invention, if there are words such as "several", it means one or more, "more" means more than two, greater than, less than, exceed, etc. are understood as not including the number, and above, below, within, etc. are understood as including the number.

[0032] In the description of the present invention, unless otherwise clearly defined, terms such as setting, installing, connecting, etc. should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meanings of the above terms in the present invention based on the specific content of the technical solution.

[0033] refer to Figure 1 ,like Figure 1 The figure shows an overall block diagram of a test circuit of a mainboard function module provided by an embodiment of the present invention, wherein the test circuit of the mainboard function module includes a mainboard and a test board;

[0034] The mainboard is provided with a first processor U1, a first control switch Q1, a second control switch Q2, a load F1, and a mainboard side access point group; the mainboard side access point group includes a first mainboard access point T11, a second mainboard access point T12, a third mainboard access point T13, and a fourth mainboard access point T14; wherein the input end of the first control switch Q1 is connected to the first power supply end, the output end of the first control switch Q1 is connected to the second power supply end, the control end of the first control switch Q1 is connected to the control end of the second control switch Q2, the first processor U1 is connected to the input end of the second control switch Q2, and the second power supply end is connected to the load F1; the first mainboard access point T11 is provided between the first control switch Q1 and the first power supply end, the second mainboard access point T12 is provided between the first control switch Q1 and the second power supply end, the third mainboard access point T13 is provided between the first processor U1 and the second control switch Q2, and the fourth mainboard access point T14 is grounded;

[0035] The test board is provided with a second processor U2, an ADC detection chip U3, and a test side access point group; the test side access point group includes a first test access point T21, a second test access point T22, a third test access point T23, and a fourth test access point T24; wherein, the second processor U2 is connected to the ADC detection chip U3 via an I2C interface, the ADC detection chip U3 is connected to the first test access point T21 via a first ADC interface ADC1, the ADC detection chip U3 is connected to the second test access point T22 via a second ADC interface ADC2, and the third test access point T23 and the fourth test access point T24 are both grounded;

[0036] A first resistor R1 is connected between the first ADC interface ADC1 and the second ADC interface ADC2;

[0037] The first processor U1 is used to control the second control switch Q2 to be turned on, thereby controlling the first control switch Q1 to be turned on, so as to output the power supply voltage of the first power supply end to the second power supply end, and provide the power supply voltage for the load F1 through the power supply voltage of the second power supply end;

[0038] The second processor U2 is used to respond to the interrupt prompt information (such as Alert interrupt prompt information) sent by the ADC detection chip U3, and obtain the ADC value read by the ADC detection chip U3; the ADC value includes: the voltage value of the first ADC interface ADC1 and the voltage value of the second ADC interface ADC2;

[0039] And it is used to determine the input voltage of the first resistor R1 according to the voltage value of the first ADC interface ADC1, and determine the output voltage of the first resistor R1 according to the voltage value of the second ADC interface ADC2; the voltage, current and power of the load F1 are calculated according to the input voltage and output voltage of the first resistor R1.

[0040] In the embodiment provided by the present invention, the first processor U1 outputs high and low levels to control the on and off of the second control switch Q2, thereby controlling the on and off of the first control switch Q1, so as to output the power supply voltage of the first power supply end to the second power supply end, and provide the power supply voltage for the load F1 through the power supply voltage of the second power supply end. By calculating the current and power of the first resistor R1, the voltage, current and power of the load F1 can be determined. By adopting the solution of this embodiment, it can be expanded for multiple independent functional modules, thereby realizing independent testing of each functional module on the mainboard.

[0041] For example, assuming that the voltage value of the first ADC interface ADC1 is ADC1, the voltage value of the second ADC interface ADC2 is ADC2, and the resistance value of the first resistor R1 is R1, the current I of the first resistor R1 can be calculated by the formula I=(ADC1-ADC2) / R1, that is, the current flowing through the first resistor R1 can be equivalently obtained. The power P of the load F1 can be calculated by the formula P=I*I*R1.

[0042] refer to Figure 2 As a further improvement of the above technical solution, as a further improvement of the above technical solution, the first control switch Q1 is a PMOS tube, and the second control switch Q2 is an NPN transistor;

[0043] The source S of the PMOS tube is connected to the first power supply terminal, the drain D of the PMOS tube is connected to the second power supply terminal, the gate G of the PMOS tube is connected to the collector of the NPN transistor, the processor is connected to the base of the NPN transistor, and the emitter of the NPN transistor is grounded;

[0044] The first mainboard access point T11 is arranged between the source S of the PMOS tube and the first power supply terminal, the second mainboard access point T12 is arranged between the drain D of the PMOS tube and the second power supply terminal, and the third mainboard access point T13 is arranged between the first processor U1 and the base of the NPN transistor.

[0045] In some embodiments, the MOS switch is a P-channel enhancement type MOS field effect transistor of model WPM2026; the second control switch Q2 is an NPN transistor of model 9014.

[0046] As a further improvement of the above technical solution, the second processor U2 is also connected to a display screen U4, and the display screen U4 is used to display the voltage, current and power of the load F1 processed by the second processor U2.

[0047] refer to Figure 3 As a further improvement of the above technical solution, the ADC detection chip U3 adopts a chip model INA226, the VBUS pin of the ADC detection chip U3 is connected to the IN+ pin of the ADC detection chip U3, and the VBUS pin and IN+ pin of the ADC detection chip U3 are commonly connected to the first test access point T21; the IN- pin of the ADC detection chip U3 is connected to one end of the first resistor R1, and the IN+ pin of the ADC detection chip U3 is connected to the other end of the first resistor R1.

[0048] It should be noted that the INA226 chip used in this embodiment is a shunt / power monitor with an I2C compatible interface or an SMBUS compatible interface. The device monitors the shunt voltage drop and the bus power supply voltage. The programmable calibration value, conversion time and averaging function combined with the internal multiplier can realize direct reading of current values ​​(in amperes) and power values ​​(in watts). The INA226 chip can sense current in the common-mode bus voltage range of 0V to 36V, regardless of the power supply voltage. The device is powered by a single power supply of 2.7V to 5.5V, and the typical power supply current is 330μA. The device is rated for an operating temperature range of –40℃ to 125℃ and has up to 16 programmable addresses on the I2C compatible interface.

[0049] As a further improvement of the above technical solution, the resistance of the first resistor R1 is 50mR, and a second resistor R2 is arranged between the first mainboard access point T11 and the collector of the second control switch Q2, and the resistance of the second resistor R2 is 47KΩ; a third resistor R3 is arranged between the third mainboard access point T13 and the first processor U1, and the resistance of the third resistor R3 is 1KΩ.

[0050] The working principle of the embodiment of the present invention is as follows:

[0051] The power supply voltage VCC_IN of the first power supply terminal is used as the original power supply voltage of the load F1 on the mainboard, and the first control switch Q1 is controlled by the second control switch Q2 to finally control the on or off of the power supply voltage of the load F1. Among them, the first resistor R1 plays a role of current limiting.

[0052] The first processor U1 outputs high and low levels through the GPIO_CTL interface to control the on and off of the second control switch Q2, thereby controlling the on and off of the first control switch Q1, and finally outputting the power supply voltage VCC_IN of the first power supply end to the second power supply end, and providing the final power supply voltage for the load F1 through the power supply voltage VCC_IN_F of the second power supply end.

[0053] When the first processor U1 outputs a high level through GPIO_CTL, VCC_IN_F=VCC_IN; when the first processor U1 outputs a low level through GPIO_CTL, VCC_IN_F=FLOAT, that is, floating.

[0054] The mainboard-side access point group and the test-side access point group provided in this embodiment use a pin design, and the first test access point T21, the second test access point T22, the third test access point T23, and the fourth test access point T24 on the test board correspond to the first mainboard access point T11, the second mainboard access point T12, the third mainboard access point T13, and the fourth mainboard access point T14 on the mainboard, respectively.

[0055] When the test board is connected, the third test access point T23, the fourth test access point T24, the third mainboard access point T13 and the fourth mainboard access point T14 are short-circuited. At this time, the second control switch Q2 is not controlled by GPIO_CTL, so the first control switch Q1 is turned off. The current of the load F1 flows from the first resistor R1 on the test board.

[0056] By testing the voltage value of the first ADC interface ADC1, the input voltage of the first resistor R1 is determined. By testing the voltage value of the second ADC interface ADC2, the output voltage of the first resistor R1 is determined, and the voltage of the load F1 is calculated. By the formula I = (ADC1-ADC2) / R1, the current I of the first resistor R1, that is, the current flowing through the first resistor R1, can be calculated. By the formula P = I*I*R, the power of the load F1 (first resistor R1) can be calculated. The voltage U, current I and power P of the load F1 (first resistor R1) are displayed on the display.

[0057] refer to Figure 3 ,like Figure 3 The flowchart shown is a method for testing a test circuit of a mainboard functional module provided by an embodiment of the present invention, comprising:

[0058] Step S100, the first processor U1 controls the second control switch Q2 to be turned on, thereby controlling the first control switch Q1 to be turned on, so as to output the power supply voltage of the first power supply end to the second power supply end, and provide the power supply voltage for the load F1 through the power supply voltage of the second power supply end;

[0059] Step S200, the second processor U2 responds to the Alert interrupt prompt information sent by the ADC detection chip U3, and obtains the ADC value read by the ADC detection chip U3 through the I2C interface; the ADC value includes: the voltage value of the first ADC interface ADC1 and the voltage value of the second ADC interface ADC2;

[0060] In step S300, the second processor U2 determines the input voltage of the first resistor R1 according to the voltage value of the first ADC interface ADC1, and determines the output voltage of the first resistor R1 according to the voltage value of the second ADC interface ADC2; and calculates the voltage, current and power of the load F1 according to the input voltage and output voltage of the first resistor R1.

[0061] The specific implementation principle of the embodiment of the present invention is as follows:

[0062] This embodiment uses the Ti chip INA226 as the ADC detection chip U3 and uses the STM32 single-chip microcomputer as the second processor U2.

[0063] The first test access point T21T21, the second test access point T22T22, the third test access point T23T23, and the fourth test access point T24T24 on the test board are respectively connected to the first mainboard access point T11T11, the second mainboard access point T12T12, the third mainboard access point T13T13, and the fourth mainboard access point T14T14 on the main board.

[0064] As shown in Table 1 below, the register of the ADC detection chip is set according to Table 1, and the resistance value of the first resistor R1 is set to R1=50mR. When the current flowing through the first resistor R1 is 2A and the power supply voltage VCC_IN of the first power supply end is 5V, the power of the first resistor R1 is equal to 10W, that is, the power of the load F1 is 10W.

[0065] Table 1:

[0066]

[0067] As shown in Table 2 below, the register of the ADC detection chip is set according to Table 2, and the resistance value of the first resistor is set to R1=50mR. When the current flowing through the first resistor is 2A and the power supply voltage VCC_IN of the first power supply end is 3.3V, the power of the first resistor is equal to 10W, that is, the power of the load F1 is 10W.

[0068] Table 2:

[0069]

[0070] It can be seen that the embodiment provided by the present invention only needs to set the internal register of the INA226 chip, and by reading the ADC value on the INA226, the current and power flowing through the first resistor R1 can be calculated, so that the power of each load F1 in the test mainboard can be quickly determined.

[0071] Although the description of the present invention has been quite detailed and specifically describes several described embodiments, it is not intended to be limited to any of these details or embodiments or any particular embodiment, but should be regarded as providing a broad possible interpretation of these claims by reference to the appended claims, taking into account the prior art, so as to effectively cover the intended scope of the present invention. In addition, the above description of the present invention is based on the embodiments foreseeable by the inventor, and its purpose is to provide a useful description, and those non-substantial changes to the present invention that have not yet been foreseen may still represent equivalent changes to the present invention.

Claims

1. A test circuit for a mainboard functional module, characterized in that: include: Main board and test board; The mainboard is provided with a first processor, a first control switch, a second control switch, a load, and a mainboard side access point group; The mainboard side access point group includes a first mainboard access point, a second mainboard access point, a third mainboard access point, and a fourth mainboard access point; wherein the input end of the first control switch is connected to the first power supply end, the output end of the first control switch is connected to the second power supply end, the control end of the first control switch is connected to the control end of the second control switch, the first processor is connected to the input end of the second control switch, and the second power supply end is connected to the load; the first mainboard access point is arranged between the first control switch and the first power supply end, the second mainboard access point is arranged between the first control switch and the second power supply end, the third mainboard access point is arranged between the first processor and the second control switch, and the fourth mainboard access point is grounded; The test board is provided with a second processor, an ADC detection chip, and a test side access point group; the test side access point group includes a first test access point, a second test access point, a third test access point, and a fourth test access point; wherein the second processor is connected to the ADC detection chip via an I2C interface, the ADC detection chip is connected to the first test access point via a first ADC interface, the ADC detection chip is connected to the second test access point via a second ADC interface, and the third test access point and the fourth test access point are both grounded; A first resistor is connected between the first ADC interface and the second ADC interface; The first processor is used to control the second control switch to be turned on, thereby controlling the first control switch to be turned on, so as to output the power supply voltage of the first power supply end to the second power supply end, and provide the power supply voltage for the load through the power supply voltage of the second power supply end; The second processor is used to respond to the interrupt prompt information sent by the ADC detection chip, and obtain the ADC value read by the ADC detection chip; the ADC value includes: the voltage value of the first ADC interface and the voltage value of the second ADC interface; And it is used to determine the input voltage of the first resistor according to the voltage value of the first ADC interface, and determine the output voltage of the first resistor according to the voltage value of the second ADC interface; and calculate the voltage, current and power of the load according to the input voltage and output voltage of the first resistor.

2. A test circuit for a mainboard functional module according to claim 1, characterized in that: The first control switch is a PMOS transistor, and the second control switch is an NPN transistor; The source of the PMOS tube is connected to the first power supply terminal, the drain of the PMOS tube is connected to the second power supply terminal, the gate of the PMOS tube is connected to the collector of the NPN transistor, the processor is connected to the base of the NPN transistor, and the emitter of the NPN transistor is grounded; The first mainboard access point is arranged between the source of the PMOS tube and the first power supply terminal, the second mainboard access point is arranged between the drain of the PMOS tube and the second power supply terminal, and the third mainboard access point is arranged between the first processor and the base of the NPN transistor.

3. A test circuit for a mainboard functional module according to claim 2, characterized in that: The second processor is also connected to a display screen, and the display screen is used to display the voltage, current and power of the load processed by the second processor.

4. A test circuit for a mainboard functional module according to claim 2, characterized in that: The ADC detection chip adopts a chip model INA226, the VBUS pin of the ADC detection chip is connected to the IN+ pin of the ADC detection chip, and the VBUS pin and IN+ pin of the ADC detection chip are commonly connected to the first test access point; the IN- pin of the ADC detection chip is connected to one end of the first resistor, and the IN+ pin of the ADC detection chip is connected to the other end of the first resistor.

5. A test circuit for a mainboard functional module according to claim 2, characterized in that: The resistance value of the first resistor is 50mR, a second resistor is arranged between the first motherboard access point and the collector of the second control switch, and the resistance value of the second resistor is 47KΩ; a third resistor is arranged between the third motherboard access point and the first processor, and the resistance value of the third resistor is 1KΩ.

6. A method for testing a test circuit of a mainboard functional module, applied to the test circuit of the mainboard functional module according to any one of claims 1 to 5, characterized in that: include: Step S100, the first processor controls the second control switch to be turned on, thereby controlling the first control switch to be turned on, so as to output the power supply voltage of the first power supply end to the second power supply end, and provide the power supply voltage for the load through the power supply voltage of the second power supply end; Step S200, the second processor responds to the interrupt prompt information sent by the ADC detection chip, and obtains the ADC value read by the ADC detection chip through the I2C interface; the ADC value includes: the voltage value of the first ADC interface and the voltage value of the second ADC interface; Step S300, the second processor determines the input voltage of the first resistor according to the voltage value of the first ADC interface, and determines the output voltage of the first resistor according to the voltage value of the second ADC interface; and calculates the voltage, current and power of the load according to the input voltage and output voltage of the first resistor.

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