A high-safety 28V / open discrete output circuit

Abstract

The present invention discloses a high-safety 28V / open discrete output circuit, comprising: a CPU, an FPGA, a bus driver 1, a bus driver 2, a driver 1, a driver 2 and an output subcircuit; the above devices form a first-level control link in which the CPU provides a first control signal to the driver 1, and a second-level control link in which the FPGA provides a second control signal to the driver 2; the output end of the driver 1 is connected to the power supply input end of the driver 2, so that the first-level control link and the second-level control link form a two-level series control link, and the 28V power supply is transmitted to the driver 2 in the second-level control link via the driver 1 in the first-level control link, and the output end of the driver 2 is connected to the output subcircuit. The technical solution of the present invention solves the problem that the output circuit used in the existing model is difficult to meet the safety requirements of the electromechanical system for electromechanical calculations.

Description

Technical Field

[0001] The present invention relates to the field of circuit technology, but is not limited to it, and in particular to a high-safety 28V / open discrete quantity output circuit. Background Art

[0002] The aircraft's electromechanical system is a general term for the subsystems that perform flight support functions in the aircraft. It is a necessary and basic condition for ensuring the performance of various aircraft functions. Its reliability and technological advancement directly affect the overall performance of the aircraft. In addition, it has an important impact on the safety of the aircraft.

[0003] The electromechanical system involves interfaces such as landing gear control, brake control, and squib control. If these interfaces output 28V by mistake during control, it may cause serious flight accidents. Therefore, very high safety index requirements are usually imposed on the interfaces of the electromechanical system; for example, the failure probability of the product's 28V / open output interface outputting 28V by mistake, resulting in an accidental landing gear retraction signal, is required to be less than 1*10 -7 / Flight hours. The output circuit used in previous models can no longer meet the safety requirements of electromechanical systems. Summary of the invention

[0004] The purpose of the embodiment of the present invention is: the embodiment of the present invention provides a high-safety 28V / open discrete output circuit to solve the problem that the output circuit used in the existing model is difficult to meet the safety requirements of the electromechanical system for electromechanical computing. The high-safety 28V / open discrete output circuit provided by the embodiment of the present invention helps to improve the safety of the onboard computer.

[0005] The technical solution of the embodiment of the present invention is as follows: The embodiment of the present invention provides a high-safety 28V / open discrete quantity output circuit, comprising: a processor CPU, a programmable device FPGA, a bus driver 1, a bus driver 2, a driver 1, a driver 2, and an output sub-circuit;

[0006] The CPU, bus driver 1 and driver 1 connected in sequence form a first-level control link, which is used for the CPU to provide a first control signal to the driver 1;

[0007] The CPU, FPGA, bus driver 2 and driver 2 are connected in sequence to form a second level control link, which is used for the FPGA to provide a second control signal to the driver 2;

[0008] The output end of the driver 1 is connected to the power supply input end of the driver 2, so that the first-level control link and the second-level control link form a two-level series control link, and the 28V power supply is transmitted to the driver 2 in the second-level control link through the driver 1 in the first-level control link, and the output end of the driver 2 is connected to the output sub-circuit.

[0009] Optionally, in the high-safety 28V / open discrete output circuit described above,

[0010] The high-safety 28V / open discrete quantity output circuit is used to control the output subcircuit to output 28V or open circuit according to the control instruction when the driver 2 receives the second control signal from the FPGA after the driver 1 receives the first control signal from the CPU and supplies power to the driver 2.

[0011] Optionally, in the high-safety 28V / open discrete output circuit described above, in the first-level control link,

[0012] The CPU is connected to the input IO terminal of the bus driver 1 through the GPIO interface, and the output IO terminal of the bus driver 1 is connected to the control terminal of the driver 1, so as to send a first control signal from the CPU to the driver 1.

[0013] Optionally, in the high-safety 28V / open discrete output circuit described above, in the second-level control link,

[0014] The CPU is connected to the IO terminal of the FPGA through a local bus, so that the CPU accesses the FPGA through the local bus, the output IO terminal of the FPGA is connected to the input IO terminal of the bus driver 2, and the output IO terminal of the bus driver 2 is connected to the control terminal of the driver 2, which is used for the FPGA to send a second control signal to the driver 2.

[0015] Optionally, in the high-safety 28V / open discrete output circuit described above,

[0016] The driver 1 and the driver 2 use driver devices of different types, so that the first-level control link and the second-level control link form a two-level serial heterogeneous control link.

[0017] Optionally, in the high-safety 28V / open discrete output circuit described above,

[0018] The driver 1 and driver 2 use different control levels. The driver 1 enables output when the control IO is high, and the controller 2 enables output when the control IO is low, so as to avoid circuit erroneous output caused by outputting a fixed high level when the bus driver fails.

[0019] Optionally, in the high-safety 28V / open discrete output circuit described above,

[0020] The first-level control link and the second-level control link use the same CPU.

[0021] Optionally, in the high-safety 28V / open discrete output circuit described above,

[0022] The first-level control link and the second-level control link use different CPUs to avoid circuit erroneous output caused by a single point failure of a single CPU.

[0023] The beneficial effects of the embodiments of the present invention are:

[0024] The embodiment of the present invention provides a high-safety 28V / open discrete quantity output circuit. The discrete quantity output circuit adopts a CPU and an FPGA to perform two-stage series control, which can ensure that when any device in the discrete quantity output circuit fails, 28V open cannot be output. Only when two or more devices fail, the discrete quantity output circuit may erroneously output 28V. Therefore, the failure probability of the discrete quantity output circuit erroneously outputting 28V can be reduced to 1*10 -12 / flight hours. In the technical solution of the embodiment of the present invention, due to the addition of a first-stage series control, the basic reliability of the output circuit will be reduced; however, after quantitative analysis, the failure probability of the 28V / open interface failing to output 28V failure mode can still be maintained at 10 -6 / flight hour, the failure probability of this kind of fault has not increased significantly, which can meet the use requirements of the electromechanical system. In addition, the discrete output circuit used in the embodiment of the present invention can significantly enhance the safety of the system, and is particularly suitable for the field of airborne computers involving safety-critical system control. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The accompanying drawings are used to provide a further understanding of the technical solution of the present invention and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present invention and do not constitute a limitation on the technical solution of the present invention.

[0026] Figure 1 A schematic structural diagram of a high-safety 28V / open discrete quantity output circuit provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0027] In order to make the purpose, technical solution and advantages of the present invention more clear, the embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other arbitrarily without conflict.

[0028] The above background technology has explained that very high safety index requirements are put forward for the interface of the electromechanical system. The output circuit used in the existing models can hardly meet the safety requirements of the electromechanical system for electromechanical calculations.

[0029] In view of the problems existing in the above-mentioned existing output circuits, the embodiment of the present invention provides a high-safety 28V / open discrete output circuit. The discrete output circuit adopts CPU and FPGA for two-stage series control, which can ensure that when any device in the discrete output circuit fails, it cannot output 28V. Only when two or more devices fail, it is possible for the discrete output circuit to output 28V by mistake. Therefore, the failure probability of the discrete output circuit outputting 28V by mistake can be reduced to 1*10-12 / flight hour. In the technical solution of the embodiment of the present invention, due to the addition of a first-stage series control, the basic reliability of the output circuit will be reduced; however, after quantitative analysis, the failure probability of the 28V / open interface failing to output 28V can still be maintained at 10-6 / flight hour. The failure probability of this type of failure has not been greatly increased, which can meet the use requirements of the electromechanical system.

[0030] The present invention provides the following specific embodiments which can be combined with each other. The same or similar concepts or processes may not be described in detail in some embodiments.

[0031] Figure 1 A schematic diagram of the structure of a high-safety 28V / open discrete quantity output circuit provided in an embodiment of the present invention. The high-safety 28V / open discrete quantity output circuit provided in an embodiment of the present invention, the high-safety 28V / open discrete quantity output circuit provided in an embodiment of the present invention, the main structure includes: a processor CPU, a programmable device FPGA, a bus driver 1, a bus driver 2, a driver 1, a driver 2 and an output sub-circuit.

[0032] like Figure 1 In the structure of the high-safety 28V / open discrete output circuit shown, on the one hand, the CPU, bus driver 1 and driver 1 connected in sequence form a first-level control link in the circuit, which is used for the CPU to provide a first control signal to the driver 1.

[0033] In the first level control link, the CPU is connected to the input IO terminal of the bus driver 1 through its GPIO interface, and the output IO terminal of the bus driver 1 is connected to the control terminal of the driver 1, so that the CPU sends a first control signal to the driver 1.

[0034] On the other hand, the CPU, FPGA, bus driver 2 and driver 2 connected in sequence form a second-level control link in the circuit, which is used for the FPGA to provide a second control signal to the driver 2.

[0035] In the second-level control link, the CPU is connected to the IO terminal of the FPGA (the IO terminal is a bidirectional IO terminal) through its local bus (Local Bus), that is, the CPU can access the FPGA through the Local Bus, the output IO terminal of the FPGA is connected to the input IO terminal of the bus driver 2, and the output IO terminal of the bus driver 2 is connected to the control terminal of the driver 2, thereby realizing the sending of the second control signal from the FPGA to the driver 2.

[0036] like Figure 1 In the high-safety 28V / open discrete output circuit shown, the output end of driver 1 is specifically connected to the power supply input end of driver 2, so that the first-level control link and the second-level control link form a two-level series control link, and the 28V power supply is transmitted to the driver 2 in the second-level control link through the driver 1 in the first-level control link, and the output end of driver 2 is connected to the output sub-circuit.

[0037] The two-stage series control link of the high-safety 28V / open discrete output circuit provided by the above embodiment of the present invention has the following working principle:

[0038] After the driver 1 receives the first control signal from the CPU and supplies power to the driver 2, when the driver 2 receives the second control signal from the FPGA, the output subcircuit is controlled to output 28V or open circuit according to the control instruction.

[0039] It should be noted that, since the driver 1 and the driver 2 in the embodiment of the present invention respectively receive control signals from the CPU and the FPGA, the generation of common mode failure can be avoided.

[0040] In an implementation of the embodiment of the present invention, the driver 1 is powered by 28V, and the 28V output by the driver 1 is connected to the power supply input terminal of the driver 2.

[0041] In an implementation of the embodiment of the present invention, driver 1 and driver 2 select driver devices of different models, so that the first-level control link and the second-level control link form a two-level serial heterogeneous control link.

[0042] In one implementation of the embodiment of the present invention, driver 1 and driver 2 use different control levels. Driver 1 enables output when the control IO is at a high level, and controller 2 enables output when the control IO is at a low level, so as to avoid circuit erroneous output caused by outputting a fixed high level when the bus driver fails.

[0043] It should be noted that if bus driver 1 and bus driver 2 are of the same type and driver 1 and driver 2 use the same control level, the following situation may exist: in a certain fault mode of the bus driver, IO is uncontrolled and often outputs a high level. At this time, drivers 1 and 2 are both turned on, resulting in erroneous output of the circuit.

[0044] In this implementation, if the driver 1 and the driver 2 use different control levels, the above-mentioned erroneous output phenomenon can be avoided.

[0045] Optionally, in the embodiment of the present invention, the CPUs in the first-level control link and the second-level control link may be the same CPU; this circuit structure is conducive to cost saving.

[0046] Optionally, in the embodiment of the present invention, different CPUs may be used in the first-level control link and the second-level control link in the embodiment of the present invention; thus, circuit erroneous output caused by a single point failure of a single CPU can be avoided.

[0047] The embodiment of the present invention provides a high-safety 28V / open discrete quantity output circuit. The discrete quantity output circuit adopts a CPU and an FPGA to perform two-stage series control, which can ensure that when any device in the discrete quantity output circuit fails, 28V open cannot be output. Only when two or more devices fail, the discrete quantity output circuit may erroneously output 28V. Therefore, the failure probability of the discrete quantity output circuit erroneously outputting 28V can be reduced to 1*10 -12 / flight hours. In the technical solution of the embodiment of the present invention, due to the addition of a first-stage series control, the basic reliability of the output circuit will be reduced; however, after quantitative analysis, the failure probability of the 28V / open interface failing to output 28V failure mode can still be maintained at 10 -6 / flight hour, the failure probability of this kind of fault has not increased significantly, which can meet the use requirements of the electromechanical system. In addition, the discrete output circuit used in the embodiment of the present invention can significantly enhance the safety of the system, and is particularly suitable for the field of airborne computers involving safety-critical system control.

[0048] The specific implementation manner of the high-safety 28V / open discrete quantity output circuit provided by the embodiment of the present invention is schematically described below through some specific implementation examples.

[0049] Reference Figure 1 The circuit structure shown, the high-safety 28V / open discrete output circuit provided in this specific embodiment mainly includes: a CPU, an FPGA, a bus driver 1, a bus driver 2, a driver 1, a driver 2 and an output circuit.

[0050] The CPU controls the bus driver 1 through its own GPIO to directly control the driver 1 without going through the FPGA, so the control link has fewer devices, a short path, and high reliability.

[0051] The CPU accesses the FPGA through the Local Bus. When output is required, the software writes data to a fixed address. After receiving the output instruction, the FPGA controls the bus driver 2 through its IO to control the driver 2.

[0052] Driver 1 and driver 2 are both powered by 28V. Driver 1 is directly powered by a 28V power supply and acts as a switch. The 28V output by driver 1 is used as the power supply for driver 2 to achieve a two-stage series control link. Driver 1 and driver 2 can be selected as solid-state relays, electromagnetic relays, or output controllers (TPS2492PW or XC7388BAC). The two drivers are selected from different models. For example, driver 1 is selected as TPS2492PW and driver 2 is selected as XC7388BAC. The two drivers form heterogeneity to avoid common-mode failures causing interface erroneous output.

[0053] In the two-stage series control link of this specific embodiment, adding devices to the interface path will inevitably reduce the basic reliability of the entire output interface. After quantitative analysis, the failure probability of the high-safety 28V / open discrete output circuit provided by this specific embodiment failing to output 28V is in the order of 10 -6 / flight hours, the specific value depends on the selected device. Although the basic reliability of the circuit is slightly reduced by adding series control, the CPU and FPGA control the two drivers respectively, and driver 1 is directly controlled by the CPU's GPIO, and driver 2 is controlled by the FPGA through the Local Bus to receive CPU instructions. The software and hardware implementations of the two control methods are heterogeneous. At the same time, with two-stage series control, the failure of a single device will not cause the interface to always output 28V. Only when two or more devices fail at the same time can the interface always output 28V. Therefore, the failure probability of the interface's fault mode of erroneous output of 28V can be reduced to 10 -12 / flight hours, meeting the requirements of system safety. This high-safety 28V / open discrete output circuit can be used in the control of safety-critical systems such as landing gear retraction and extension, brake solenoid valve control, and electric squib drive in airborne electromechanical systems, and has important application value.

[0054] In the high-safety 28V / open discrete output circuit provided by each embodiment of the present invention, in view of the high-safety design requirements of the onboard computer, the CPU uses GPIO to control the driver 1, and the FPGA uses IO to control the driver 2. The driver 1 is used as a switch to power the driver 2, so as to realize the two-level control of the CPU and the FPGA in series, and prevent the product from outputting incorrectly, so that the failure probability of the interface outputting 28V incorrectly is less than 1*10 -7 / flight hours. The circuit hardware structure is simple and reliable, and has been successfully applied to a certain type of UAV, and is stable and reliable during use.

[0055] Although the embodiments disclosed in the present invention are as above, the contents are only embodiments adopted to facilitate understanding of the present invention and are not intended to limit the present invention. Any technician in the field to which the present invention belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in the present invention, but the patent protection scope of the present invention shall still be subject to the scope defined by the attached claims.

Claims

1. A high-safety 28V / open discrete output circuit, characterized in that: It includes: a processor CPU, a programmable device FPGA, a bus driver 1, a bus driver 2, a driver 1, a driver 2, and an output sub-circuit; The CPU, bus driver 1 and driver 1 connected in sequence form a first-level control link, which is used for the CPU to provide a first control signal to the driver 1; The CPU, FPGA, bus driver 2 and driver 2 are connected in sequence to form a second level control link, which is used for the FPGA to provide a second control signal to the driver 2; The output end of the driver 1 is connected to the power supply input end of the driver 2, so that the first-level control link and the second-level control link form a two-level series control link, and the 28V power supply is transmitted to the driver 2 in the second-level control link through the driver 1 in the first-level control link, and the output end of the driver 2 is connected to the output sub-circuit; Wherein, the high-safety 28V / open discrete quantity output circuit is used to control the output subcircuit to output 28V or open circuit according to the control instruction when the driver 2 receives the second control signal from the FPGA after the driver 1 receives the first control signal from the CPU and supplies power to the driver 2; The driver 1 and driver 2 use different control levels. The driver 1 enables output when the control IO is high, and the controller 2 enables output when the control IO is low, so as to avoid circuit erroneous output caused by outputting a fixed high level when the bus driver fails.

2. According to the high-safety 28V / open discrete output circuit described in claim 1, it is characterized in that: In the first level control link, The CPU is connected to the input IO terminal of the bus driver 1 through the GPIO interface, and the output IO terminal of the bus driver 1 is connected to the control terminal of the driver 1, so as to send a first control signal from the CPU to the driver 1.

3. According to the high-safety 28V / open discrete output circuit described in claim 1, it is characterized in that: In the second level control link, The CPU is connected to the IO terminal of the FPGA through a local bus, so that the CPU accesses the FPGA through the local bus, the output IO terminal of the FPGA is connected to the input IO terminal of the bus driver 2, and the output IO terminal of the bus driver 2 is connected to the control terminal of the driver 2, which is used for the FPGA to send a second control signal to the driver 2.

4. The high-safety 28V / open discrete output circuit according to any one of claims 1 to 3, characterized in that: The driver 1 and the driver 2 use driver devices of different types, so that the first-level control link and the second-level control link form a two-level serial heterogeneous control link.

5. The high-safety 28V / open discrete output circuit according to any one of claims 1 to 3, characterized in that: The first-level control link and the second-level control link use the same CPU.

6. The high-safety 28V / open discrete output circuit according to any one of claims 1 to 3, characterized in that: The first-level control link and the second-level control link use different CPUs to avoid circuit erroneous output caused by a single point failure of a single CPU.

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