Layout method of electric fuse cell array

Abstract

The present invention provides a layout method for an electric fuse unit array, comprising: an electric fuse unit pair structure, which comprises two electric fuse units; the first electric fuse unit comprises a first transistor and a first electric fuse unit; the second electric fuse unit comprises a second transistor and a second electric fuse unit; the first electric fuse unit is connected across the first transistor and the second transistor; the second electric fuse unit is connected across the second transistor and the first transistor. Accordingly, the technical effect that the present invention can achieve is that the layout area can be reduced compared with the prior art while various performances remain unchanged.

Description

Technical Field

[0001] The invention relates to integrated circuit layout technology, and in particular to a layout method for an electric fuse unit array. Background Art

[0002] Based on the principle of electromigration (EM), eFuse realizes on-chip programming function with high reliability by blowing the fuse. As the market's requirements for chip area become higher and higher, the overall area of ​​eFuse, as a dedicated module (IP) for parameter setting inside the chip, has become one of the main design indicators. Inside the eFuse module, the array composed of eFuse units occupies more than half of the entire module area, so reducing the area of ​​the eFuse unit array is one of the main means to improve the competitiveness of the eFuse module.

[0003] When designing the eFuse layout, the array composed of eFuse units accounts for more than half of the overall area. The eFuse unit is composed of a fuse and a selector. In conventional designs, the array area is composed of the area of ​​independent eFuse units, which is the product of the area of ​​a single eFuse unit and the number of units.

[0004] See also Figure 1A As shown, the storage area of ​​the electric fuse in the prior art is composed of an electric fuse unit array, as shown in FIG1 , wherein the storage units in the array appear in the form of a combination of independent electric fuse units. This arrangement is for the convenience of layout design and the combination of different capacities.

[0005] See also Figure 1B As shown, in a layout of an electric fuse layout in the prior art, there is an electric fuse unit 01. The total area of ​​the electric fuse array = the layout area of ​​a single electric fuse unit x the number of rows x the number of columns. Referring to 1C, a unit pair directly spliced ​​from two independent electric fuse units 01 is used as the basic unit form, which can share and save peripheral routing. Figure 1D Shown Figure 1C A schematic diagram of one of the two independent electric fuse units 01 and a transistor path is shown in FIG. Figure 1B In the solid line box, arrows are used to indicate the path. Figure 1E As shown in the figure, taking the electric fuse unit of the 28nm process platform as an example, the area of ​​the NMOS tube and the electric fuse is 14.4μm 2 The combined area of ​​the two units is 28.8 μm 2 .

[0006] The problem with the existing technology is that the above two methods are not optimal in terms of layout area and efficiency. Summary of the invention

[0007] The technical problem to be solved by the present invention is: how to further reduce the layout area and improve the utilization efficiency of the layout area.

[0008] In order to solve the above technical problems, the present invention provides a layout method of an electric fuse unit array, which aims to improve the layout method of the electric fuse unit array and reduce the area of ​​the electric fuse module.

[0009] In order to achieve the above-mentioned object, the present invention provides a layout method of an electric fuse unit array, comprising: an electric fuse unit pair structure, which comprises two electric fuse transistor units;

[0010] The first electrical fuse transistor unit comprises: a first transistor and a first electrical fuse unit;

[0011] The second electrical fuse transistor unit comprises: a second transistor and a second electrical fuse unit;

[0012] The first electrical fuse unit is connected across the first transistor and the second transistor;

[0013] The second electrical fuse unit is connected across the second transistor and the first transistor.

[0014] Preferably, the first electrical fuse unit comprises a first anode pad, a first fuse, and a first cathode pad, and two ends of the first fuse are connected to the first anode pad and the first cathode pad;

[0015] The second electrical fuse unit comprises a second anode pad, a second fuse, and a second cathode pad, and two ends of the second fuse are connected to the second anode pad and the second cathode pad;

[0016] The first anode pad-first fuse-first cathode pad are arranged in parallel with the second cathode pad-second fuse-second anode pad along a first direction,

[0017] In a second direction perpendicular to the first direction, the first anode pad is aligned with the second cathode pad, and the first cathode pad is aligned with the second anode pad.

[0018] Preferably, the first anode pad is located at the second transistor, and the first cathode pad is located at the first transistor;

[0019] A second anode pad is located at the first transistor, and a second cathode pad is located at the second transistor;

[0020] The first transistor and the second transistor are arranged crosswise and symmetrically.

[0021] Preferably, the first transistor and the second transistor are MOS transistors.

[0022] Preferably, the first transistor and the second transistor are NMOS transistors.

[0023] Preferably, the first anode pad and the first cathode pad are in plate shape, the first fuse is in strip shape, and the width of the first anode pad and the first cathode pad is much greater than the width of the first fuse;

[0024] The second anode pad and the second cathode pad are in plate shape, the second fuse is in strip shape, and the width of the second anode pad and the second cathode pad is much greater than the width of the second fuse.

[0025] Preferably, the first anode pad and the second anode pad are formed by using a third metal layer;

[0026] The first fuse and the second fuse are formed by using the second metal layer;

[0027] The first cathode pad and the second cathode pad are formed by using the second metal layer;

[0028] The first anode pad is connected from the third metal layer to the second metal layer of the first fuse through the first connecting hole;

[0029] The second anode pad is connected from the third metal layer to the second metal layer of the second fuse through the second via.

[0030] Preferably, the second metal layer is arranged along the first direction, and the third metal layer is arranged along the second direction;

[0031] The first bit line and the second bit line are respectively formed through a third metal layer;

[0032] The word lines are formed through the second metal layer.

[0033] Preferably, the formed equivalent circuit comprises:

[0034] A first bit line located in the third metal layer is connected to a first anode pad located in the third metal layer, connected to a first fuse located in the second metal layer through a first connecting hole, and then connected to a first cathode pad located in the second metal layer;

[0035] A second bit line located in the third metal layer is connected to a second anode pad located in the third metal layer, connected to a second fuse located in the second metal layer through a second connecting hole, and then connected to a second cathode pad located in the second metal layer;

[0036] A first anode pad is located at the first transistor, and a first cathode pad is located at the second transistor;

[0037] A second anode pad is located at the second transistor, and a second cathode pad is located at the first transistor;

[0038] The first transistor and the second transistor are arranged crosswise and symmetrically;

[0039] The source, drain and gate of the first transistor and the second transistor are connected by the second metal layer;

[0040] The equivalent circuit formed also includes:

[0041] A source or a drain of the first transistor is connected to a first cathode pad, a drain or a source of the first transistor is grounded, and a gate of the first transistor is connected to a word line;

[0042] A source or a drain of the second transistor is connected to the second cathode pad, a drain or a source of the second transistor is grounded, and a gate of the second transistor is connected to the word line.

[0043] Preferably, the electrical fuse unit pair structure provided by the method is arrayed to form an integrated integrated circuit.

[0044] Compared with the prior art, the present invention provides a layout method for an electric fuse unit array, comprising: an electric fuse unit pair structure, which comprises two electric fuse units; the first electric fuse unit comprises a first transistor and a first electric fuse unit; the second electric fuse unit comprises a second transistor and a second electric fuse unit; the first electric fuse unit is connected across the first transistor and the second transistor; the second electric fuse unit is connected across the second transistor and the first transistor. Accordingly, the technical effect that the present invention can achieve is that the layout area can be reduced compared with the prior art while various performances remain unchanged. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1A An integrated circuit layout diagram showing an embodiment of a prior art electrical fuse arrangement.

[0046] Figure 1B An integrated circuit layout diagram showing yet another embodiment of a prior art electrical fuse arrangement.

[0047] Figure 1C Shown Figure 1B The two electrical fuse units used in the integrated circuit layout are used as basic units.

[0048] Figure 1D Shown Figure 1B Schematic diagram of one of the two electric fuse units and the transistor path.

[0049] Figure 1E Shown Figure 1B Schematic diagram of the layout area occupied by an electric fuse and a transistor in the electric fuse unit on the 28nm technology node process platform.

[0050] Figure 2A The diagram shows the arrangement of a pair of electric fuses in an electric fuse unit pair structure provided in the layout method of an electric fuse unit array provided by the present invention.

[0051] Figure 2B An equivalent circuit diagram of the arrangement of the electric fuse unit pair structures provided in the layout method of the electric fuse unit array provided by the present invention is shown.

[0052] Figure 3A The schematic diagram of the arrangement of the electric fuse unit pair structure provided in the layout method of the electric fuse unit array provided by the present invention is shown.

[0053] Figure 3B An equivalent circuit diagram of the arrangement of the electric fuse unit pair structures provided in the layout method of the electric fuse unit array provided by the present invention is shown.

[0054] Figure 3C A schematic diagram of an electric fuse and a transistor path in an electric fuse unit pair structure provided in the layout method of an electric fuse unit array provided by the present invention is shown.

[0055] Figure 3D The diagram shows an equivalent circuit diagram of an electric fuse and a transistor path in an electric fuse unit pair structure provided in the layout method of an electric fuse unit array provided by the present invention.

[0056] Description of Figure Numbers.

[0057] Existing technology:

[0058] 01 Electric fuse unit;

[0059] The present invention:

[0060] 10 Electric fuse unit pair structure

[0061] 11. First electric fuse transistor unit

[0062] 12. Second electric fuse transistor unit

[0063] 13. The First Transistor

[0064] 14. First electrical fuse unit

[0065] 15. Second transistor

[0066] 16 Second electric fuse unit

[0067] 17 First anode pad

[0068] 18 First Fuse

[0069] 19 First cathode pad

[0070] 20 Second anode pad

[0071] 21 Second Fuse

[0072] 22. Second cathode pad

[0073] 23 Third Metal Layer

[0074] 24 Second Metal Layer

[0075] 25 First connecting hole

[0076] 26 Second connecting hole

[0077] 27 First Line

[0078] 28 Second bit line

[0079] 29 Word Line

[0080] 30 Source or drain of the first transistor

[0081] 31 Drain or source of the first transistor

[0082] 32 Land

[0083] 33 Gate of the first transistor

[0084] 34 Source or drain of the second transistor

[0085] 35 Drain or source of the second transistor

[0086] 36 The gate of the second transistor. DETAILED DESCRIPTION

[0087] The specific implementation modes of the present invention are described in detail below with reference to the accompanying drawings.

[0088] See also Figure 2A and 3A As shown, the present invention provides a layout method for an electric fuse unit array, comprising: an electric fuse unit pair structure 10. The electric fuse unit pair structure 10 comprises: two electric fuse transistor units 11 and 12. The first electric fuse transistor unit 11 comprises: a first transistor 13 and a first electric fuse unit 14. The second electric fuse transistor unit 12 comprises: a second transistor 15 and a second electric fuse unit 16. The first electric fuse unit 14 is connected across the first transistor 13 and the second transistor 15. The second electric fuse unit 16 is connected across the second transistor 15 and the first transistor 13.

[0089] The first electrical fuse unit 14 (Link1) includes: a first anode pad 17 (Pad pad), a first fuse 18, and a first cathode pad 19 (Pad pad). Two ends of the first fuse 18 are connected to the first anode pad 17 and the first cathode pad 19.

[0090] The second electrical fuse unit 16 (Link2) includes a second anode pad 20 (Pad pad), a second fuse 21 and a second cathode pad 22 (Pad pad). Two ends of the second fuse 21 are connected to the second anode pad 20 and the second cathode pad 22 .

[0091] The first anode pad 17 - the first fuse 18 - the first cathode pad 19 are arranged parallel to the second cathode pad 22 - the second fuse 21 - the second anode pad 20 along the first direction X. The first direction X is also the length direction of the first fuse 18 and the second fuse 21 .

[0092] In a second direction Y perpendicular to the first direction X, the first anode pad 17 is aligned with the second cathode pad 22 , and the first cathode pad 19 is aligned with the second anode pad 20 .

[0093] The first anode pad 17 is located at the second transistor 15 , and the first cathode pad 19 is located at the first transistor 13 .

[0094] The second anode pad 20 is located at the first transistor 13 , and the second cathode pad 22 is located at the second transistor 15 .

[0095] The first transistor 13 and the second transistor 15 are arranged crosswise and symmetrically.

[0096] The first transistor 13 and the second transistor 15 are MOS transistors.

[0097] The first transistor 13 and the second transistor 15 are NMOS transistors (NMOS1 and NMOS2 respectively), which are used as selection transistors.

[0098] The first anode pad 17 and the first cathode pad 19 are in a plate shape, and the first fuse 18 is in a strip shape. The width of the first anode pad 17 and the first cathode pad 19 is much greater than the width of the first fuse 18 .

[0099] The second anode pad 20 and the second cathode pad 22 are in plate shape, and the second fuse 21 is in strip shape, and the width of the second anode pad 20 and the second cathode pad 22 is much greater than the width of the second fuse 21. Accordingly, under the condition of the same thickness of the metal layer, the cross-sectional area per unit length of the electric fuse is smaller, and the resistance per unit length is larger, so as to be blown.

[0100] The first anode pad 17 and the second anode pad 20 are formed by using a third metal layer 23 (M3).

[0101] The first fuse 18 and the second fuse 21 are formed by using the second metal layer 24 (M2).

[0102] The first cathode pad 19 and the second cathode pad 22 are formed by using the second metal layer 24 (M2).

[0103] The first anode pad 17 is connected from the third metal layer 23 to the second metal layer 24 of the first fuse 18 through a first via 25 (Via).

[0104] The second anode pad 20 is connected from the third metal layer 23 to the second metal layer 24 of the second fuse 21 through a second via 26 (Via).

[0105] The second metal layer 24 is arranged along the first direction X. The third metal layer 23 is arranged along the second direction Y.

[0106] The first bit line 27 ( BL1 ) and the second bit line 28 ( BL2 ) are respectively formed by the third metal layer 23 .

[0107] Word lines 29 (WL) are formed through the second metal layer 24 .

[0108] See also Figure 2B As shown, the equivalent circuit formed includes as described below.

[0109] The first bit line 27 on the third metal layer is connected to the first anode pad 17 on the third metal layer, connected to the first fuse 18 on the second metal layer through the first connecting hole 25, and then connected to the first cathode pad 19 on the second metal layer.

[0110] The second bit line 28 located in the third metal layer is connected to the second anode pad 20 located in the third metal layer, connected to the second fuse 21 located in the second metal layer through the second connecting hole 26, and then connected to the second cathode pad 22 located in the second metal layer.

[0111] The first anode pad 17 is located at the second transistor 15 , and the first cathode pad 19 is located at the first transistor 13 .

[0112] The second anode pad 20 is located at the first transistor 13 , and the second cathode pad 22 is located at the second transistor 15 .

[0113] The first transistor 13 and the second transistor 15 are arranged crosswise and symmetrically.

[0114] The source, drain and gate of the first transistor 13 and the second transistor 15 are connected by the second metal layer 24 .

[0115] See also Figure 3B As shown, the equivalent circuit formed also includes as described below.

[0116] A source or drain 30 of the first transistor is connected to the first cathode pad 19 , a drain or source 31 of the first transistor is connected to a ground 32 (GND), and a gate 33 of the first transistor is connected to the word line 29 .

[0117] A source or drain 34 of the second transistor is connected to the second cathode pad 22 , a drain or source 35 of the second transistor is connected to the ground 32 (GND), and a gate 36 of the second transistor is connected to the word line 29 .

[0118] The electrical fuse unit pair structure provided by the method is arrayed to form an integrated integrated circuit.

[0119] The layout method of the electric fuse cell array can be applied to memory (Memory), has passed the test and verification of the Technology Qualification Vehicle (TQV), and is a more optimized module (IP).

[0120] Figure 3C A schematic diagram of an electric fuse and a transistor path in an electric fuse unit pair structure provided in the layout method of an electric fuse unit array provided by the present invention is shown. Figure 3D The diagram shows an equivalent circuit diagram of an electric fuse and a transistor path in an electric fuse unit pair structure provided in the layout method of an electric fuse unit array provided by the present invention. Figure 3C and Figure 3D The line with an arrow indicates the path, which passes through the first electrical fuse unit 14 and the first transistor 13, and then passes through the first bit line 27, the first anode pad 17, the first fuse 18, the first cathode pad 19, the first transistor 13, the ground formed at the second metal layer 24, the word line 29, etc.

[0121] The above is a specific embodiment of the layout method of the electric fuse unit array provided by the present invention. Figure 1E Compared with the arrangement of the electronic fuse unit array of the second embodiment of the prior art shown in FIG. 1 , the transistor and the electronic fuse unit are arranged independently, but are arranged interactively, so that in the 28nm process platform, the electronic fuse unit array of the present invention can be arranged interactively. Figure 3A The electrical fuse unit pair structure shown in the figure also realizes the ability to store 2 bits of information (corresponding to the prior art Figure 1E The actual layout area is reduced by 25%.

[0122] The above specific embodiments and accompanying drawings are only used to illustrate the technical solutions and technical effects of the present invention, and are not used to limit the present invention. Any person skilled in the art who is familiar with the technology can modify or change the above embodiments within the scope of the claims without violating the technical principles and spirit of the present invention, and all of them belong to the scope of protection of the present invention.

Claims

1. A layout method for an electric fuse cell array, It is characterized in that It comprises: an electric fuse unit pair structure, which comprises, two electric fuse transistor units; The first electrical fuse transistor unit comprises: a first transistor and a first electrical fuse unit; the first electrical fuse unit comprises a first anode pad, a first fuse, and a first cathode pad, and two ends of the first fuse are connected to the first anode pad and the first cathode pad; The second electric fuse transistor unit comprises: a second transistor and a second electric fuse unit; the second electric fuse unit comprises a second anode pad, a second fuse, and a second cathode pad, and two ends of the second fuse are connected to the second anode pad and the second cathode pad; The first electrical fuse unit is connected across the first transistor and the second transistor; A second electrical fuse unit is connected across the second transistor and the first transistor; The first anode pad-first fuse-first cathode pad are arranged in parallel with the second cathode pad-second fuse-second anode pad along a first direction, and in a second direction perpendicular to the first direction, the first anode pad is aligned with the second cathode pad, and the first cathode pad is aligned with the second anode pad; The first anode pad and the second anode pad are formed by the third metal layer; the first fuse and the second fuse are formed by the second metal layer; the first cathode pad and the second cathode pad are formed by the second metal layer; the first anode pad is connected from the third metal layer to the second metal layer of the first fuse through the first connecting hole; the second anode pad is connected from the third metal layer to the second metal layer of the second fuse through the second connecting hole; The second metal layer is arranged along the first direction, and the third metal layer is arranged along the second direction; the first bit line and the second bit line are respectively formed by the third metal layer; and the word line is formed by the second metal layer; The equivalent circuit formed includes: A first bit line located in the third metal layer is connected to a first anode pad located in the third metal layer, connected to a first fuse located in the second metal layer through a first connecting hole, and then connected to a first cathode pad located in the second metal layer; A second bit line located in the third metal layer is connected to a second anode pad located in the third metal layer, connected to a second fuse located in the second metal layer through a second connecting hole, and then connected to a second cathode pad located in the second metal layer; A first anode pad is located at the first transistor, and a first cathode pad is located at the second transistor; A second anode pad is located at the second transistor, and a second cathode pad is located at the first transistor; The first transistor and the second transistor are arranged crosswise and symmetrically; The source, drain and gate of the first transistor and the second transistor are connected by the second metal layer; The equivalent circuit formed also includes: A source or a drain of the first transistor is connected to a first cathode pad, a drain or a source of the first transistor is grounded, and a gate of the first transistor is connected to a word line; A source or a drain of the second transistor is connected to the second cathode pad, a drain or a source of the second transistor is grounded, and a gate of the second transistor is connected to the word line.

2. The layout method of the electric fuse cell array according to claim 1, It is characterized in that A first anode pad is located at the second transistor, and a first cathode pad is located at the first transistor; A second anode pad is located at the first transistor, and a second cathode pad is located at the second transistor; The first transistor and the second transistor are arranged crosswise and symmetrically.

3. The layout method of the electro-fuse cell array according to claim 1, characterized in that, the first transistor and the second transistor are MOS transistors.

4. The layout method of the electro-fuse cell array according to claim 3, characterized in that, the first transistor and the second transistor are NMOS transistors.

5. The layout method of the electro-fuse cell array according to claim 1, characterized in that, the first anode pad and the first cathode pad are plate-shaped, the first fuse is strip-shaped, and the widths of the first anode pad and the first cathode pad are much larger than the width of the first fuse; the second anode pad and the second cathode pad are plate-shaped, the second fuse is strip-shaped, and the widths of the second anode pad and the second cathode pad are much larger than the width of the second fuse.

6. The layout method of the electro-fuse cell array according to claim 1, characterized in that, the electro-fuse cell pair structure array provided by this method forms an overall integrated circuit.

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