Memory system, memory controller, and operating method of memory controller

Abstract

Embodiments of the present disclosure relate to a memory system, a memory controller, and an operating method of a memory controller. The memory system can include a memory and a memory controller configured to: issue a command scheduled in a first scheme to the memory when power consumption of the memory is less than a first threshold, and issue a command scheduled in a second scheme to the memory when the power consumption is not less than the first threshold and less than a second threshold; and stop issuing the command to the memory when the power consumption of the memory is not less than the second threshold.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0131707, filed on October 13, 2020, which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to a memory system including a memory and a memory controller for controlling the memory. Background Technology

[0004] Recently, a great deal of research has been conducted to replace DRAM and flash memory with next-generation memories. One type of these next-generation memories is resistive memory, which uses a material (i.e., a variable resistance material) that can rapidly change its resistance based on an applied bias and thus switch between at least two different resistance states. Representative examples of these memories include phase-change random access memory (PCRAM), resistive random access memory (RRAM), magnetic random access memory (MRAM), and ferroelectric random access memory (FRAM).

[0005] Specifically, resistive memory is configured as a memory cell array with a cross-point array structure. A cross-point array structure refers to a structure in which multiple lower electrodes (e.g., multiple row lines (word lines)) and multiple upper electrodes (e.g., multiple column lines (bit lines)) are formed to intersect each other, wherein memory cells with variable resistive elements and selection elements connected in series are provided at each intersection.

[0006] Power throttling is applied to resistive memory. Power throttling can be implemented in such a way that when the power consumption of the resistive memory exceeds a threshold, the power consumption and temperature of the resistive memory are reduced by preventing the issuance of commands to the resistive memory. Summary of the Invention

[0007] Embodiments of this disclosure can provide a memory system that uses power throttling and does not significantly degrade quality of service (QoS).

[0008] According to an embodiment of this disclosure, a memory system includes a memory and a memory controller, the memory controller being configured to: issue a command to the memory to schedule it using a first scheme when the power consumption of the memory is less than a first threshold; issue a command to the memory to schedule it using a second scheme when the power consumption is not less than the first threshold and is less than a second threshold; and stop issuing commands to the memory when the power consumption of the memory is not less than the second threshold.

[0009] According to embodiments of the present disclosure, a memory controller includes: a power tracking unit configured to monitor the power consumption of the memory; and a scheduler configured to determine a scheme for scheduling operations to be performed by the memory based on the monitoring results performed by the power tracking unit.

[0010] According to embodiments of this disclosure, a method for operating a memory controller includes: scheduling commands to be issued to a memory based on a performance-oriented scheduling scheme; determining that the power consumption of the memory is not less than a sub-threshold; switching the scheduling scheme to a QoS-oriented scheduling scheme in response to the determination; and scheduling commands to be issued to the memory based on the switched scheduling scheme.

[0011] According to embodiments of this disclosure, a controller operation method includes: scheduling an operation to be executed based on a round-robin (RR) method when the power consumption of the memory is lower than a first threshold, and scheduling the operation to be executed based on a first-come, first-served (FCFS) method when the power consumption is the first threshold or higher; and interrupting to provide the memory with a command according to the scheduled operation when the power consumption is not less than a second threshold greater than the first threshold.

[0012] According to embodiments of this disclosure, the degradation of Quality of Service (QoS) due to the use of power throttling in the memory system can be reduced. Attached Figure Description

[0013] Figure 1 This is a diagram illustrating the configuration of a memory system 100 according to an embodiment of the present disclosure;

[0014] Figure 2 This is a diagram illustrating the scheduling operations of scheduler 115; and

[0015] Figure 3 This is a flowchart illustrating the operation of the memory controller 110. Detailed Implementation

[0016] In the following detailed description of various embodiments of this disclosure with reference to the accompanying drawings, to allow those skilled in the art to readily practice the technical spirit of this disclosure. Well-known components or elements unrelated to the subject matter of this disclosure may be omitted from this specification. Throughout the specification and drawings, the same or substantially the same reference numerals are used to refer to the same or substantially the same elements.

[0017] Figure 1 This is a diagram illustrating the configuration of a memory system 100 according to an embodiment of the present disclosure.

[0018] Reference Figure 1 The memory system 100 may include a memory controller 110 and a memory 150.

[0019] The memory controller 110 can control various operations of the memory 150, such as read and write operations, according to requests from the host. The memory 150 can perform various operations instructed by the memory controller 110. The memory 150 can be one of all types of memory. For example, the memory can be a resistive memory such as phase-change random access memory (PCRAM), resistive random access memory (RRAM), magnetic random access memory (MRAM), and ferroelectric random access memory (FRAM), or the memory can be NAND flash memory or DRAM, instead of resistive memory.

[0020] The memory controller 110 may include a host interface 111, a power tracking unit 113, a scheduler 115, a command generator 117, and a memory interface 119.

[0021] The host interface 111 can be used as an interface between the memory controller 110 and the host. Requests, corresponding addresses, and data from the host can be received through the host interface 111, and the processing results of the requests can be sent to the host. The host interface 111 can be one of the following: PCI-EXPRESS (PCIe), Cache Coherent Interconnect for Accelerators (CCIX), Dual In-line Memory Module (DIMM), or other various types of interfaces.

[0022] The power tracking unit 113 can monitor the power consumption of the memory 150. The power tracking unit 113 can monitor the power consumption of the memory 150 based on commands applied to the memory 150 within a predetermined time window. For example, the power consumption of the memory 150 can be determined based on the type and number of commands applied to the memory 150 during a predetermined time period (e.g., 500 ns).

[0023] Scheduler 115 can schedule operations to be performed by memory 150. For example, when five requests A, B, C, D, and E are received from host HOST via host interface 111, scheduler 115 can schedule the order of requests A, B, C, D, and E, and memory 150 will perform operations according to that order.

[0024] The scheduling scheme (i.e., scheduling algorithm) of the scheduler 115 can be changed based on the monitoring of the power tracking unit 113. When the power consumption of the memory 150 is less than a first threshold as a result of the monitoring performed by the power tracking unit 113, the scheduler 115 can schedule the request using a first scheme. Here, the first scheme or performance-oriented scheme refers to a scheduling scheme that gives greater weight to the performance of the memory system 100, and examples of performance-oriented scheduling schemes may include a round-robin (RR) scheme.

[0025] When the power consumption of memory 150 is greater than or equal to the first threshold, scheduler 115 may schedule the request using a second scheme. The second scheme, or QoS-oriented scheme, refers to a scheduling scheme that emphasizes the quality of service (QoS) of memory system 100, and an example of a QoS-oriented scheduling scheme could be a first-come, first-served (FCFS) scheme.

[0026] When the power consumption of memory 150 is not less than a second threshold, scheduling of requests can be stopped. The second threshold can be a reference value for power throttling of memory 150. In other words, when the power consumption of memory 150 is greater than or equal to the second threshold, the issuance of commands from memory controller 110 to memory 150 is stopped, and scheduling by scheduler 115 can also be stopped. Since stopping the issuance of commands to memory 150 is important in power throttling, even when the power consumption of memory 150 is greater than or equal to the second threshold, only command issuance can be stopped, and scheduling by scheduler 115 can continue. The first threshold can be lower than the second threshold. For example, when the second threshold is a value representing power consumption of 100, the first threshold can be a value representing power consumption of 80 or 90.

[0027] The first scheme is a performance-oriented scheduling scheme that emphasizes the performance of the memory system 100; the second scheme is a QoS-oriented scheduling scheme that emphasizes the quality of service (QoS) of the memory system 100. The first and second schemes can be relative concepts. Compared to the second scheme, the first scheme can be a performance-oriented scheduling scheme that places greater emphasis on performance; and compared to the first scheme, the second scheme can be a QoS-oriented scheduling scheme that places greater emphasis on QoS. For example, the first scheme can be an FCFS-RR scheme in which FCFS and RR are combined, and the second scheme can be an FCFS scheme with lower performance but higher QoS compared to the first scheme.

[0028] Table 1 below summarizes the scheduling scheme of scheduler 115, which switches according to the power consumption of memory 150.

[0029] [Table 1]

[0030] Power consumption Less than the first threshold Not less than the first threshold Not less than the second threshold Scheduling scheme Performance-oriented scheduling QoS-oriented scheduling Stop scheduling

[0031] Command generator 117 can generate commands to be applied to memory 150 according to the order of operations scheduled by scheduler 115.

[0032] The memory interface 119 can be used as an interface between the memory controller 110 and the memory 150. The memory interface 119 can transmit commands generated by the command generator 117 and the addresses corresponding to those commands to the memory 150, and send data to / receive data from the memory 150.

[0033] Figure 2 This is a diagram illustrating the scheduling operations of scheduler 115.

[0034] Figure 2 The "H_REQUEST" value indicates a request sent from the host to the memory controller 110. (See reference...) Figure 2 It can be identified that the request was transmitted from the host in the order of A, B, C, D, E, F, G, H, I, J, and K. Requests A through K can differ in at least one or more of the following: the type of operation to be performed by memory 150 and the address in memory 150 where the operation is to be performed.

[0035] Figure 2 The “SCHEDULER” indicates the processing order of requests scheduled by scheduler 115. “201” indicates the moment when the power consumption of memory 150 becomes a first threshold or higher. Until moment “201” is reached, scheduler 115 can schedule requests using either a first scheme or a performance-oriented scheme. Since scheduler 115 schedules requests using the performance-oriented first scheme, the processing order of requests can differ from the order in which requests are delivered from the host. Referring to the accompanying drawings, requests can be identified as being scheduled for processing in the order of B, D, E, H, F, and G.

[0036] Since the power consumption of memory 150 becomes a first threshold or higher at time "201", scheduler 115 can schedule requests from time "201" using either a second scheme or a QoS-oriented scheme. From "201", longer requests A and C can be scheduled for processing with regard to Quality of Service (QoS). When the power consumption of memory 150 becomes the first threshold or higher, power throttling of memory 150 may begin quickly, and command issuance to memory 150 may cease. Therefore, it may be necessary to switch the scheduling scheme to the second scheme to handle longer requests (e.g., A and C) and prevent severe QoS degradation.

[0037] "203" indicates the moment when the power consumption of memory 150 becomes the second threshold or higher. At moment "203", commands to the memory are stopped being issued, which also stops the scheduler's scheduling.

[0038] Figure 2 The "205" indicates a request that was scheduled even after time "201," under the assumption that scheduler 115 still schedules requests using the first scheme. Referring to "205," it can be identified that requests I and K were scheduled after time "201." In this case, when scheduling stops after time "203," older requests A and C may remain unprocessed for a long time, resulting in a severe degradation of Quality of Service (QoS).

[0039] Figure 3 This is a flowchart illustrating the operation of the memory controller 110.

[0040] Reference Figure 3 The scheduler 115 of the memory controller 110 can schedule requests (301) using either a first scheme or a performance-oriented scheme. The command generator 117 can generate commands based on the requests scheduled by the scheduler 115, and the commands can be applied to the memory 150 via the memory interface 119.

[0041] When the power consumption of memory 150 monitored by power tracking unit 113 is greater than or equal to a first threshold ("Yes" in 303) and less than a second threshold ("No" in 305), the scheduling scheme of scheduler 115 can switch from the first scheme to the second scheme or a QoS-oriented scheme, and scheduling can be performed based on the QoS-oriented scheme (307). Command generator 117 can generate commands based on requests scheduled by scheduler 115, and commands can be applied to memory 150 through memory interface 119.

[0042] When the power consumption of memory 150 monitored by power tracking unit 113 is greater than or equal to the second threshold ("yes" in 305), the scheduling operation of scheduler 115 stops (309), and command generation by command generator 117 and command application to memory 150 by memory interface 119 can be stopped.

[0043] Subsequently, when the power consumption of memory 150 drops below the second threshold, the scheduling operation of scheduler 115 can resume.

[0044] Reference Figure 3 By default, scheduler 115 can schedule requests from the host using either a first scheme or a performance-oriented scheme. When the power consumption of memory 150 becomes a first threshold or higher, and power throttling is likely, requests from the host can be scheduled according to a second QoS-oriented scheme to prevent a significant degradation in QoS. When the power consumption of memory 150 becomes a second threshold or higher, power throttling can be initiated, and the scheduling of commands and the application of commands to memory 150 can be stopped.

[0045] It should be noted that although the technical spirit of this disclosure has been described in conjunction with preferred embodiments, this is for illustrative purposes only and should not be construed as restrictive. Those skilled in the art will understand that various modifications can be made without departing from the technical spirit of this disclosure.

[0046] Although the teachings have been shown and described with reference to specific embodiments, it will be apparent to those skilled in the art, based on this disclosure, that various changes and modifications may be made without departing from the spirit and scope of the disclosure as defined by the appended claims.

Claims

1. A memory system comprising: a memory; and a memory controller issuing commands to the memory scheduled in a first scheme when a power consumption of the memory is less than a first threshold, and issuing commands to the memory scheduled in a second scheme when the power consumption is not less than the first threshold and less than a second threshold, and stopping issuing the commands to the memory when the power consumption of the memory is not less than the second threshold.

2. The memory system of claim 1, wherein the first scheme is a performance oriented scheduling scheme and the second scheme is a quality of service, QoS, oriented scheduling scheme.

3. The memory system of claim 2, wherein the first scheme is a round robin, RR, scheme and the second scheme is a first come first served, FCFS, scheme.

4. The memory system of claim 1, wherein the memory controller comprises: a power tracking unit monitoring the power consumption of the memory; and a scheduler scheduling operations to be performed by the memory selected from one of the first scheme and the second scheme according to a result of the monitoring by the power tracking unit.

5. The memory system of claim 4, wherein the memory controller further comprises: a host interface receiving requests from a host to be scheduled by the scheduler; a command generator generating commands corresponding to the operations scheduled by the scheduler; and a memory interface transferring the commands generated by the command generator to the memory.

6. A memory controller comprising: a power tracking unit monitoring a power consumption of a memory; and a scheduler determining a scheme for scheduling operations to be performed by the memory according to a result of the monitoring by the power tracking unit; wherein when, as a result of the monitoring by the power tracking unit, the power consumption of the memory is less than a sub-threshold, the scheduler determines a performance oriented scheduling scheme as the scheme for scheduling the operations; and when, as a result of the monitoring by the power tracking unit, the power consumption of the memory is not less than a sub-threshold, the scheduler determines a QoS oriented scheduling scheme as the scheme for scheduling the operations, wherein when, as a result of the monitoring by the power tracking unit, the power consumption of the memory is not less than a threshold higher than the sub-threshold, the memory controller stops issuing commands to the memory.

7. The memory controller of claim 6, wherein the performance oriented scheduling scheme is a round robin, RR, scheme and the QoS oriented scheduling scheme is a first come first served, FCFS, scheme.

8. The memory controller of claim 6, further comprising: a host interface receiving requests from a host, operations corresponding to the requests being scheduled by the scheduler; a command generator generating commands corresponding to the operations scheduled by the scheduler; and a memory interface transferring the commands generated by the command generator to the memory.

9. A method for operating a memory controller, the method comprising: ​ ​ scheduling commands to be issued to a memory based on a performance-oriented scheduling scheme; determining that power consumption of the memory is not less than a sub-threshold value; in response to the determination, switching the scheduling scheme to a QoS-oriented scheduling scheme; scheduling the commands to be issued to the memory based on the switched scheduling scheme; determining that the power consumption of the memory is not less than a threshold value higher than the sub-threshold value; and stopping issuing the commands to the memory.

10. The method of claim 9, wherein the performance-oriented scheduling scheme is a round robin (RR) scheme and the QoS-oriented scheduling scheme is a first come first served (FCFS) scheme.

11. A method of operation of a controller, the method of operation comprising: scheduling operations to be performed based on a round robin (RR) scheme when power consumption of a memory is below a first threshold value, and based on a first come first served (FCFS) scheme when the power consumption is the first threshold value or higher; and interrupting providing commands to the memory in accordance with the scheduled operations when the power consumption is not less than a second threshold value, the second threshold value being higher than the first threshold value.

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