A system on chip and a method of manufacturing the same

Abstract

The application provides a system-level chip and a manufacturing method thereof, and realizes a high-resistance substrate through a polysilicon substrate of a substrate board and realizes a low-resistance substrate through a single crystal silicon substrate of the substrate board; then, the high-resistance polysilicon substrate can support the function of a radio frequency chip structure, and the low-resistance single crystal silicon substrate can support the function of a logic control chip structure, so as to realize the compatibility of the logic control chip structure and the radio frequency chip structure in the system-level chip.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically, to a system-on-a-chip and a method for manufacturing the same. Background Technology

[0002] RF (Radio Frequency)-SOI (Silicon on Insulator) technology has firmly established its dominance in the 4G mobile phone RF switch market; RF-SOI technology has become the mainstream technology for RF applications in 4G mobile phone switches, with a market share exceeding 95%. FD-SOI is a fully depleted silicon-on-insulator technology. Compared to traditional bulk silicon or Fin-FET technologies, it offers flexible and adjustable back bias, significantly improving chip performance. It introduces an ultra-thin buried oxide layer as an insulating layer within the bulk silicon, resulting in low power consumption, high speed, radiation resistance, high reliability, and high-performance computing capabilities. Currently, RF-SOI and FD-SOI use substrates with completely different resistivities, making their chip structures incompatible. Summary of the Invention

[0003] In view of this, the present invention provides a system-on-a-chip and its fabrication method, which effectively solves the technical problems existing in the prior art and achieves compatibility between logic control chip structure and radio frequency chip structure in the system-on-a-chip.

[0004] To achieve the above objectives, the technical solution provided by the present invention is as follows:

[0005] A method for fabricating a system-on-a-chip (SoC) includes:

[0006] Provide single-crystal silicon substrates;

[0007] A buried oxide layer is formed on the single-crystal silicon substrate, and the buried oxide layer is divided into a logic region and a radio frequency region.

[0008] A chip structure is formed on the side of the buried oxide layer away from the single crystal silicon substrate. The chip structure includes a logic control chip structure and a first interconnect pad corresponding to the logic region, and a radio frequency chip structure and a second interconnect pad corresponding to the radio frequency region.

[0009] A cutout area is formed by removing the portion of the single-crystal silicon substrate corresponding to the radio frequency region;

[0010] A polycrystalline silicon substrate is formed on the side of the buried oxide layer facing the monocrystalline silicon substrate, located at the hollow area;

[0011] A packaging circuit layer is formed on the side of the monocrystalline silicon substrate and the polycrystalline silicon substrate opposite to the chip structure. The packaging circuit layer is connected to the first interconnect pad and the second interconnect pad through vias.

[0012] Optionally, after forming the chip structure and before forming the cutout area, the method further includes:

[0013] A bonding support substrate is formed on the side of the chip structure opposite to the single-crystal silicon substrate.

[0014] Optionally, the first and second connection pads are tungsten metal pads.

[0015] Accordingly, the present invention also provides a method for manufacturing a system-on-a-chip, comprising:

[0016] Provide polycrystalline silicon substrates;

[0017] A buried oxide layer is formed on the polycrystalline silicon substrate, and the buried oxide layer is divided into a logic region and a radio frequency region.

[0018] A chip structure is formed on the side of the buried oxide layer away from the polysilicon substrate. The chip structure includes a logic control chip structure and a first interconnect pad corresponding to the logic region, and a radio frequency chip structure and a second interconnect pad corresponding to the radio frequency region.

[0019] A portion of the polysilicon substrate corresponding to the logic region is removed to form a cutout area;

[0020] A monocrystalline silicon substrate is formed on the side of the buried oxide layer facing the polycrystalline silicon substrate, located in the hollow area;

[0021] A packaging circuit layer is formed on the side of the monocrystalline silicon substrate and the polycrystalline silicon substrate opposite to the chip structure. The packaging circuit layer is connected to the first interconnect pad and the second interconnect pad through vias.

[0022] Optionally, after forming the chip structure and before forming the cutout area, the method further includes:

[0023] A bonding support substrate is formed on the side of the chip structure opposite to the polycrystalline silicon substrate.

[0024] Optionally, the first and second connection pads are tungsten metal pads.

[0025] Accordingly, the present invention also provides a system-on-a-chip, comprising:

[0026] The substrate is divided into a polycrystalline silicon substrate and a monocrystalline silicon substrate.

[0027] A buried oxide layer located on one side surface of the substrate, the buried oxide layer being divided into a radio frequency region corresponding to the polycrystalline silicon substrate and a logic region corresponding to the monocrystalline silicon substrate;

[0028] A chip structure is formed on the side of the buried oxide layer away from the substrate. The chip structure includes a logic control chip structure and a first interconnect pad corresponding to the logic region, and an RF chip structure and a second interconnect pad corresponding to the RF region.

[0029] Additionally, a packaging circuit layer is located on the side of the substrate opposite to the chip structure, and the packaging circuit layer is connected to the first interconnect pad and the second interconnect pad through vias.

[0030] Optionally, the system-on-a-chip may further include a bonding support substrate located on the side of the chip structure opposite to the substrate.

[0031] Optionally, the first and second connection pads are tungsten metal pads.

[0032] Compared with the prior art, the technical solution provided by the present invention has at least the following advantages:

[0033] This invention provides a system-on-a-chip (SoC) and its fabrication method, comprising: a substrate, the substrate being divided into a polycrystalline silicon substrate and a monocrystalline silicon substrate; a buried oxide layer located on one side surface of the substrate, the buried oxide layer being divided into a radio frequency (RF) region corresponding to the polycrystalline silicon substrate and a logic region corresponding to the monocrystalline silicon substrate; a chip structure formed on the side of the buried oxide layer opposite to the substrate, the chip structure including a logic control chip structure and a first interconnect pad corresponding to the logic region, and an RF chip structure and a second interconnect pad corresponding to the RF region; and a packaging circuit layer located on the side of the substrate opposite to the chip structure, the packaging circuit layer being connected to the first interconnect pad and the second interconnect pad through vias.

[0034] As can be seen from the above, the technical solution provided by the present invention achieves a high resistivity substrate through a polycrystalline silicon substrate and a low resistivity substrate through a monocrystalline silicon substrate; thereby enabling the high resistivity polycrystalline silicon substrate to support the function of the radio frequency chip structure and the low resistivity monocrystalline silicon substrate to support the function of the logic control chip structure, achieving the goal of achieving compatibility between the logic control chip structure and the radio frequency chip structure in a system-on-a-chip. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0036] Figure 1A flowchart illustrating a method for fabricating a system-on-a-chip according to Embodiment 1 of the present invention;

[0037] Figures 2a-2f for Figure 1 A schematic diagram of the corresponding structure for each step in the process;

[0038] Figure 3 This is a flowchart of a method for manufacturing a system-on-a-chip according to Embodiment 2 of the present invention. Detailed Implementation

[0039] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0040] As described in the background section, RF (Radio Frequency)-SOI (Silicon on Insulator) has firmly established itself in the 4G mobile phone RF switch market; RF-SOI technology has become the mainstream technology for RF applications in 4G mobile phone switches, with a market share exceeding 95%. FD-SOI is a fully depleted silicon-on-insulator technology. Compared to traditional bulk silicon or Fin-FET-based technologies, it offers flexible and adjustable back bias, significantly improving chip performance. It introduces an ultra-thin buried oxide layer as an insulating layer within the bulk silicon, resulting in low power consumption, high speed, radiation resistance, high reliability, and high-performance computing capabilities. Currently, RF-SOI and FD-SOI use substrates with completely different resistivities, making their chip structures incompatible.

[0041] Based on this, embodiments of the present invention provide a system-on-a-chip and its fabrication method, effectively solving the technical problems existing in the prior art, and achieving compatibility between logic control chip structure and radio frequency chip structure in the system-on-a-chip.

[0042] To achieve the above objectives, the technical solutions provided by the embodiments of the present invention are as follows, in detail... Figures 1 to 3 The technical solutions provided in the embodiments of the present invention will be described in detail.

[0043] Example 1

[0044] refer to Figure 1 The diagram shows a flowchart of a method for fabricating a system-on-a-chip (SoC) according to Embodiment 1 of the present invention. The method includes:

[0045] S11 provides a single-crystal silicon substrate.

[0046] S12. A buried oxide layer is formed on the single-crystal silicon substrate, and the buried oxide layer is divided into a logic region and a radio frequency region.

[0047] S13. A chip structure is formed on the side of the buried oxide layer away from the single crystal silicon substrate. The chip structure includes a logic control chip structure and a first interconnect pad corresponding to the logic region, and a radio frequency chip structure and a second interconnect pad corresponding to the radio frequency region.

[0048] S14. Remove the portion of the single-crystal silicon substrate corresponding to the radio frequency region to form a cutout area.

[0049] S15. A polycrystalline silicon substrate is formed on the side of the buried oxide layer facing the monocrystalline silicon substrate, located in the hollow area.

[0050] S16. A packaging circuit layer is formed on the side of the monocrystalline silicon substrate and the polycrystalline silicon substrate away from the chip structure. The packaging circuit layer is connected to the first interconnect pad and the second interconnect pad through vias.

[0051] It is understood that the technical solution provided by the embodiments of the present invention realizes a high resistivity substrate through a polycrystalline silicon substrate and a low resistivity substrate through a monocrystalline silicon substrate; thereby enabling the high resistivity polycrystalline silicon substrate to support the function of the radio frequency chip structure and the low resistivity monocrystalline silicon substrate to support the function of the logic control chip structure, achieving the goal of realizing the compatibility of the logic control chip structure and the radio frequency chip structure in the system-on-a-chip.

[0052] Specific combination Figures 2a to 2f The manufacturing method provided in the embodiments of the present invention will be described in more detail below. Figures 2a-2f for Figure 1 The corresponding structural diagrams for each step in the process.

[0053] like Figure 2a As shown, corresponding to step S11, a single-crystal silicon substrate 110 is provided.

[0054] like Figure 2b As shown, corresponding to step S12, a buried oxide layer 120 is formed on the single crystal silicon substrate 110, and the buried oxide layer 120 is divided into a logic region 121 and a radio frequency region 122.

[0055] like Figure 2c As shown, corresponding to step S13, a chip structure is formed on the side of the buried oxide layer 120 away from the single crystal silicon substrate 110. The chip structure includes a logic control chip structure 1311 and a first interconnect pad 1312 corresponding to the logic region 121, and an RF chip structure 1321 and a second interconnect pad 1322 corresponding to the RF region 122.

[0056] like Figure 2d As shown, corresponding to step S14, the portion of the single-crystal silicon substrate 110 corresponding to the radio frequency region 122 is removed to form a hollow area.

[0057] In one embodiment of the present invention, photolithography and etching processes can be used to remove portions of the radio frequency region corresponding to the single-crystal silicon substrate. Specifically, before forming the cutout region, the single-crystal silicon substrate can be thinned to the micrometer level.

[0058] like Figure 2e As shown, corresponding to step S15, a polycrystalline silicon substrate 140 is formed on the side of the buried oxide layer 120 facing the monocrystalline silicon substrate 110, located in the hollow area.

[0059] In one embodiment of the present invention, the resistivity of the polycrystalline silicon substrate provided by the present invention is greater than that of the monocrystalline silicon substrate. Therefore, the polycrystalline silicon substrate can support the performance optimization of the RF chip structure, that is, to realize RF-SOI substrate related technology; the monocrystalline silicon substrate can support the performance optimization of the logic control chip structure, that is, to realize FD-SOI substrate related technology, thereby realizing the compatibility of RF-SOI related technology and FD-SOI related technology.

[0060] like Figure 2f As shown, corresponding to step S16, a packaging circuit layer 150 is formed on the side of the monocrystalline silicon substrate 110 and the polycrystalline silicon substrate 140 away from the chip structure. The packaging circuit layer 150 is connected to the first interconnect pad 1312 and the second interconnect pad 1322 through vias.

[0061] Furthermore, in this embodiment of the invention, after forming the chip structure and before forming the cutout area, the method further includes: forming a bonding support substrate on the side of the chip structure away from the single-crystal silicon substrate.

[0062] Understandably, forming a bonding support substrate on the side of the chip structure away from the single-crystal silicon substrate can provide support for the structure during subsequent fabrication, reducing the chance of fragmentation during the subsequent fabrication process.

[0063] In one embodiment of the present invention, the first interconnect pad and the second interconnect pad provided by the present invention are tungsten metal pads, and the present invention does not impose specific limitations on them.

[0064] Example 2

[0065] Embodiment 2 of the present invention provides a method for fabricating a system-on-a-chip (SoC). (See reference...) Figure 3 The diagram shows a flowchart of a method for fabricating a system-on-a-chip (SoC) according to Embodiment 2 of the present invention. The method includes:

[0066] S21, Provides a polycrystalline silicon substrate.

[0067] S22. A buried oxide layer is formed on the polysilicon substrate, the buried oxide layer being divided into a logic region and a radio frequency region.

[0068] S23. A chip structure is formed on the side of the buried oxide layer away from the polysilicon substrate. The chip structure includes a logic control chip structure and a first interconnect pad corresponding to the logic region, and a radio frequency chip structure and a second interconnect pad corresponding to the radio frequency region.

[0069] S24. Remove the portion of the polysilicon substrate corresponding to the logic region to form a cutout area.

[0070] S25. A monocrystalline silicon substrate is formed on the side of the buried oxide layer facing the polycrystalline silicon substrate, located in the hollow area.

[0071] S26. A packaging circuit layer is formed on the side of the monocrystalline silicon substrate and the polycrystalline silicon substrate away from the chip structure. The packaging circuit layer is connected to the first interconnect pad and the second interconnect pad through vias.

[0072] Furthermore, in this embodiment of the invention, after forming the chip structure and before forming the cutout area, the method further includes: forming a bonding support substrate on the side of the chip structure away from the polysilicon substrate.

[0073] Understandably, forming a bonding support substrate on the side of the chip structure away from the polysilicon substrate can provide support for the structure during subsequent fabrication, reducing the chance of fragmentation during the fabrication process.

[0074] In one embodiment of the present invention, the first interconnect pad and the second interconnect pad provided by the present invention are tungsten metal pads, and the present invention does not impose specific limitations on them.

[0075] Example 3

[0076] Embodiment 3 of the present invention provides a system-on-a-chip, wherein the system-on-a-chip includes:

[0077] The substrate is divided into a polycrystalline silicon substrate and a monocrystalline silicon substrate.

[0078] A buried oxide layer is located on one side surface of the substrate, and the buried oxide layer is divided into a radio frequency region corresponding to the polycrystalline silicon substrate and a logic region corresponding to the monocrystalline silicon substrate.

[0079] A chip structure is formed on the side of the buried oxide layer away from the substrate. The chip structure includes a logic control chip structure and a first interconnect pad corresponding to the logic region, and a radio frequency chip structure and a second interconnect pad corresponding to the radio frequency region.

[0080] Additionally, a packaging circuit layer is located on the side of the substrate opposite to the chip structure, and the packaging circuit layer is connected to the first interconnect pad and the second interconnect pad through vias.

[0081] Furthermore, the system-on-a-chip provided in this embodiment of the invention also includes a bonding support substrate located on the side of the chip structure opposite to the substrate.

[0082] Understandably, forming a bonding support substrate on the side of the chip structure away from the substrate can provide support for the structure during subsequent fabrication, reducing the chance of fragmentation during the fabrication process.

[0083] In one embodiment of the present invention, the first interconnect pad and the second interconnect pad provided by the present invention are tungsten metal pads, and the present invention does not impose specific limitations on them.

[0084] This invention provides a system-on-a-chip (SoC) and its fabrication method, comprising: a substrate divided into a polycrystalline silicon substrate and a monocrystalline silicon substrate; a buried oxide layer located on one side surface of the substrate, the buried oxide layer being divided into a radio frequency (RF) region corresponding to the polycrystalline silicon substrate and a logic region corresponding to the monocrystalline silicon substrate; a chip structure formed on the side of the buried oxide layer opposite to the substrate, the chip structure including a logic control chip structure and a first interconnect pad corresponding to the logic region, and an RF chip structure and a second interconnect pad corresponding to the RF region; and a packaging circuit layer located on the side of the substrate opposite to the chip structure, the packaging circuit layer being connected to the first interconnect pad and the second interconnect pad through vias.

[0085] As can be seen from the above, the technical solution provided by the embodiments of the present invention realizes a high resistivity substrate through a polycrystalline silicon substrate and a low resistivity substrate through a single-crystal silicon substrate; thereby enabling the high-resistivity polycrystalline silicon substrate to support the function of the radio frequency chip structure and the low-resistivity single-crystal silicon substrate to support the function of the logic control chip structure, achieving the goal of achieving compatibility between the logic control chip structure and the radio frequency chip structure in the system-on-a-chip.

[0086] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method of fabricating a system-on-chip, the method comprising: Comprising: ​ providing a single crystal silicon substrate; forming a buried oxide layer on the single crystal silicon substrate, the buried oxide layer being divided into a logic region and a radio frequency region; forming a chip structure on a side of the buried oxide layer facing away from the single crystal silicon substrate, the chip structure including a logic control chip structure and a first connection pad corresponding to the logic region, and a radio frequency chip structure and a second connection pad corresponding to the radio frequency region; removing a portion of the single crystal silicon substrate corresponding to the radio frequency region to form a hollowed-out area; forming a polycrystalline silicon substrate on a side of the buried oxide layer facing the single crystal silicon substrate at the hollowed-out area; forming a packaging circuit layer on a side of the single crystal silicon substrate and the polycrystalline silicon substrate facing away from the chip structure, the packaging circuit layer being connected to the first connection pad and the second connection pad through a via.

2. The method of claim 1, wherein After the chip structure is formed and before the hollowed-out area is formed, further comprising: forming a bonding support substrate on a side of the chip structure facing away from the single crystal silicon substrate.

3. The method of claim 1, wherein The first connection pad and the second connection pad are tungsten metal pads.

4. A method of fabricating a system on chip, the method comprising: Comprising: providing a polycrystalline silicon substrate; forming a buried oxide layer on the polycrystalline silicon substrate, the buried oxide layer being divided into a logic region and a radio frequency region; forming a chip structure on a side of the buried oxide layer facing away from the polycrystalline silicon substrate, the chip structure including a logic control chip structure and a first connection pad corresponding to the logic region, and a radio frequency chip structure and a second connection pad corresponding to the radio frequency region; removing a portion of the polycrystalline silicon substrate corresponding to the logic region to form a hollowed-out area; forming a single crystal silicon substrate on a side of the buried oxide layer facing the polycrystalline silicon substrate at the hollowed-out area; forming a packaging circuit layer on a side of the single crystal silicon substrate and the polycrystalline silicon substrate facing away from the chip structure, the packaging circuit layer being connected to the first connection pad and the second connection pad through a via.

5. The method of claim 4, wherein: After the chip structure is formed and before the hollowed-out area is formed, further comprising: forming a bonding support substrate on a side of the chip structure facing away from the polycrystalline silicon substrate.

6. The method of claim 4, wherein: The first connection pad and the second connection pad are tungsten metal pads.

7. A system on chip, comprising: Comprising: a substrate substrate divided into a polycrystalline silicon substrate and a single crystal silicon substrate; a buried oxide layer on a side surface of the substrate substrate, the buried oxide layer being divided into a radio frequency region corresponding to the polycrystalline silicon substrate and a logic region corresponding to the single crystal silicon substrate; a chip structure on a side of the buried oxide layer facing away from the substrate substrate, the chip structure including a logic control chip structure and a first connection pad corresponding to the logic region, and a radio frequency chip structure and a second connection pad corresponding to the radio frequency region; and a packaging circuit layer on a side of the substrate substrate facing away from the chip structure, the packaging circuit layer being connected to the first connection pad and the second connection pad through a via; wherein the polycrystalline silicon substrate is formed by removing a portion of the single crystal silicon substrate corresponding to the radio frequency region to form a hollowed-out area, and then forming the polycrystalline silicon substrate on the side of the buried oxide layer facing the single crystal silicon substrate at the hollowed-out area.

8. A system on chip, comprising: Comprising: a substrate substrate divided into a polycrystalline silicon substrate and a single crystal silicon substrate; An oxygen burying layer is located on one side surface of the substrate base plate, and the oxygen burying layer is divided into a radio frequency area corresponding to the polysilicon substrate and a logic area corresponding to the single crystal silicon substrate; A chip structure is formed on the side of the oxygen burying layer away from the substrate base plate, and the chip structure includes a logic control chip structure and a first connecting pad corresponding to the logic area, and a radio frequency chip structure and a second connecting pad corresponding to the radio frequency area; In addition, a packaging circuit layer is located on the side of the substrate base plate away from the chip structure, and the packaging circuit layer is connected to the first connecting pad and the second connecting pad through a via hole. The single crystal silicon substrate is formed by removing a part of the polysilicon substrate corresponding to the logic area to form a hollow area, and then forming the single crystal silicon substrate on the side of the oxygen burying layer facing the polysilicon substrate.

9. The system on chip of claim 7 or 8, wherein, The system level chip further includes a bonding support substrate located on the side of the chip structure away from the substrate base plate.

10. The system on chip of claim 7 or 8, wherein, The first connecting pad and the second connecting pad are tungsten metal pads.

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