A power circuit packaging structure and packaging method thereof

Abstract

The present invention discloses a power circuit packaging structure, comprising a plastic package, an IC control chip on the plastic package, a first metal-based island on both sides of the IC control chip, a second metal-based island, and a MOS switch chip connecting the IC control chip and the first metal-based island, wherein a first polyimide layer is arranged on the MOS switch chip, a second polyimide layer is arranged on the IC control chip, a first copper column of the first polyimide layer is arranged on the MOS switch chip, a first copper block which is perpendicular to the first copper column and adheres to the first metal-based island, a first pin extending outward from the first metal-based island, a second copper column and a second copper block which penetrate the first polyimide layer and the second polyimide layer, a third copper column between the second copper columns is arranged on the IC control chip, a third copper block which is perpendicular to the third copper column and adheres to the second metal-based island, and a second pin extending outward is connected to the second metal-based island. The present invention also provides a power circuit packaging method, which greatly reduces power consumption and improves operating frequency.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging, and in particular to a packaging structure of a power supply circuit and a packaging method thereof. Background Art

[0002] Usually, the main components of a power supply circuit include power switches, integrated circuits (ICs), protection devices, and passive devices. Among them, the power switches commonly used are metal oxide semiconductor field effect transistors (MOSFETs) or insulated gate bipolar transistors (IGBTs). ICs can be driver chips or PWM control chips, or a combination of the two. MOSFETs act as switches and are controlled by ICs to complete pulse width modulation of the input power supply, and output the voltage required by the load through passive devices.

[0003] At present, the mainstream packaging method of power circuits is to package MOSFET, IC and passive devices in the same package, and interconnect various devices through metal base islands and metal leads to realize circuit functions. Due to the characteristics of switching power supplies, it is necessary to transmit a large current, and the leads between devices will significantly increase the parasitic resistance and parasitic inductance of the entire power circuit, thereby affecting the current density and switching frequency of the circuit. Summary of the invention

[0004] In view of this, the present invention provides a power circuit packaging structure and a packaging method thereof with low parasitic resistance, low parasitic inductance and improved circuit integration to solve the above-mentioned technical problems, which are specifically implemented by the following technical solutions.

[0005] In a first aspect, the present invention provides a power circuit packaging structure, including a plastic package, an IC control chip located on the plastic package, a first metal-based island located on both sides of the IC control chip, a second metal-based island connected to the IC control chip, and a MOS switch chip connecting the IC control chip and the first metal-based island, wherein a first polyimide layer is arranged on the upper surface of the MOS switch chip, a second polyimide layer is arranged on the lower surface of the IC control chip, a first copper column that penetrates the first polyimide layer and is arranged at intervals is arranged on one side of the MOS switch chip, and a first end of the first copper column that is perpendicular to the first copper column and connected to the first metal-based island is provided. The first copper block is bonded to the surface of the first metal base island, the second end face of the first metal base island extends outward, the other side of the MOS switch chip is provided with second copper pillars respectively penetrating the first polyimide layer and the second polyimide layer and arranged at intervals, and a second copper block is perpendicular to the second copper pillars and located between the first polyimide layer and the second polyimide layer, the IC control chip is provided with a third copper pillar located between the second copper pillars and penetrating the second polyimide layer, and a third copper block is perpendicular to the third copper pillar and bonded to one end of the second metal base island, and the other end of the second metal base island is connected with a second pin extending outward.

[0006] In a second aspect, the present invention further provides a power circuit packaging method, comprising the following steps:

[0007] A polyimide layer is coated on the upper surfaces of the two MOS switch chips, the polyimide at the lead window of the chip is removed to form a first polyimide layer, and copper balls are implanted to grow to form first copper pillars that are arranged at intervals and penetrate the first polyimide layer and a first sub-copper pillar located on the other side of the MOS switch chip, a layer of metal is coated on the first copper pillar and the first sub-copper pillar and excess metal is removed to form a first copper block located on the first copper pillar and a first sub-copper block located on the first sub-copper pillar;

[0008] A second polyimide layer, second sub-copper pillars penetrating the second polyimide layer and arranged at intervals, a third copper pillar located between the second sub-copper pillars, a second sub-copper block perpendicular to the second sub-copper pillars, and a third copper block perpendicular to the third copper pillars are formed on the surface of the IC control chip;

[0009] A metal frame, two first metal-based islands respectively fixedly connected to the metal frame, and a second metal-based island located between the first metal-based islands are used, so that the first copper blocks of the two MOS switch chips are connected to the bottom surfaces of the first metal-based islands through conductive silver glue, the first metal-based islands are connected to the first pins, and the second metal-based islands are connected to the second pins;

[0010] The IC control chip is flipped 180° and connected to the second metal base island through silver glue, the IC control chip is placed between the first metal base islands and the MOS switch chip is symmetrically arranged on both sides of the IC control chip, the first sub-copper block is connected to the second sub-copper block, the third copper block is connected to the second metal base island, the first sub-copper block and the second sub-copper block are thermally bonded to form a second copper block, and the first sub-copper column and the second copper column are thermally bonded to form a second copper column;

[0011] The metal frame is cut and filled with a plastic package to obtain a power circuit packaging structure.

[0012] The present invention provides a power circuit packaging structure and a packaging method thereof, which have the following beneficial effects compared with the prior art:

[0013] A polyimide layer is coated on the upper surfaces of two MOS switch chips, the polyimide at the lead window of the chip is removed to form a first polyimide layer, and a copper ball is implanted to grow to form a first copper column that penetrates the first polyimide layer and is arranged at intervals and a first sub-copper column located on the other side of the MOS switch chip, a layer of metal is covered on the first copper column and the first sub-copper column and excess metal is removed to form a first copper block located on the first copper column and a first sub-copper block located on the first sub-copper column, a second polyimide layer is formed on the surface of an IC control chip, second sub-copper columns that penetrate the second polyimide layer and are arranged at intervals, a third copper column located between the second sub-copper columns, a second sub-copper block that is perpendicular to the second sub-copper column, and a third copper block that is perpendicular to the third copper column are formed, the IC control chip is connected to the two MOS switch chips by thermal bonding, two metal base islands are respectively connected to the two MOS switch chips, and the two MOS switch chips and the IC control chip are precisely and cleverly bonded together within a relatively small size range, so that the entire circuit has extremely low transmission resistance and extremely low parasitic inductance, greatly reduces power consumption and improves operating frequency. At the same time, the volume of the entire package is reduced, making the circuit smaller in size and greatly broadening the application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0015] Figure 1 A flow chart of a power circuit packaging method provided by an embodiment of the present invention;

[0016] Figures 2 to 6A process diagram of a power circuit packaging method provided by an embodiment of the present invention;

[0017] Figure 7 A schematic diagram of the structure of a power circuit packaging structure provided by an embodiment of the present invention.

[0018] The main component symbols are described as follows:

[0019] 10-power circuit packaging structure; 11-plastic package; 12-IC control chip; 13-first metal base island; 14-second metal base island; 15-MOS switch chip; 16-first polyimide layer; 17-second polyimide layer; 18-first copper pillar; 19-first copper block; 20-second copper pillar; 21-first sub-copper pillar; 22-second sub-copper pillar; 23-second copper block; 24-first sub-copper block; 25-second sub-copper block; 26-third copper pillar; 27-third copper block; 28-first pin; 29-second pin; 30-metal frame. DETAILED DESCRIPTION

[0020] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0021] It should be noted that when an element is referred to as being "fixed to" another element, it may be directly on the other element or there may be a central element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. In contrast, when an element is referred to as being "directly on" another element, there is no intermediate element. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are for illustrative purposes only.

[0022] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0023] See also Figure 1 , Figures 2 to 6 The present invention also provides a power circuit packaging method, comprising the following steps:

[0024] S1: coating a polyimide layer on the upper surfaces of the two MOS switch chips 15, removing the polyimide at the lead window of the chip to form a first polyimide layer 16, and implanting copper balls to grow to form first copper pillars 18 that are arranged at intervals and penetrate the first polyimide layer 16 and a first sub-copper pillar 21 located on the other side of the MOS switch chip 15, covering the first copper pillar 18 and the first sub-copper pillar 21 with a layer of metal and removing excess metal to form a first copper block 19 located on the first copper pillar 18 and a first sub-copper block 24 located on the first sub-copper pillar 21;

[0025] See also Figure 2 In this embodiment, the MOS switch chip 15 is a commonly used metal oxide semiconductor field effect transistor. The MOS tube is a semiconductor device in which unipolar carriers participate in conduction. According to the carriers of the conductive channel, it can be divided into N channel and P channel. If the carriers of the conductive channel are electrons, it is an N channel, and if the carriers are holes, it is a P channel. The conductive channel of the MOS tube is formed during the manufacturing process, and can also be formed by connecting an external power supply. When the gate voltage is equal to zero, the channel exists, that is, the depletion type, and the channel is formed only after the external voltage is applied. It is an enhancement type. According to the process of forming the conductive channel, it is divided into a P-channel enhancement MOS tube, a P-channel depletion MOS tube, an N-channel enhancement MOS tube and an N-channel MOS tube. Polyimide is a type of polymer containing an imide ring on the main chain. It is resistant to high temperatures of over 400°C. Polyimide can be used as a photoresist, including negative and positive photoresists. It can be used as a dielectric layer for interlayer insulation in microelectronic devices, or as a buffer layer to reduce stress and improve yield, or as a protective layer to reduce the impact of the environment on the device.

[0026] It should be noted that, firstly, a layer of insulating film layer, i.e., polyimide, is coated on the surface of the two MOS switch chips 15, which has good insulation properties and is conducive to relieving stress, and then the polyimide at the chip lead window is removed to form a groove (not shown), and a copper ball is implanted into the groove and metal growth is performed, and the first copper pillar 18 and the first sub-copper pillar 21 arranged at intervals are formed on the first polyimide layer 16, and the first copper pillar 18 and the first sub-copper pillar 21 are respectively located on both sides of the MOS switch chip 15, and the length of the first sub-copper pillar 21 is the same, but the diameter can be different, which is convenient for subsequent thermal bonding. A layer of copper is covered on the upper surface of the first copper pillar 18 and the first sub-copper pillar 21, and then the excess copper is removed, and the first copper block 19 is a complete piece that completely covers each first copper pillar 18, and there is a spacing between the first sub-copper blocks 24, that is, the first sub-copper block 24 and the first sub-copper pillar 21 are T-shaped, which is convenient for subsequent thermal bonding with the IC control chip 12. The structure of another MOS switch chip 15 is corresponding to it, but the left side is a small first copper block 24, and the right side is a large first copper block 19.

[0027] S2: forming a second polyimide layer 17, second sub-copper pillars 22 penetrating the second polyimide layer 17 and arranged at intervals, third copper pillars 26 located between the second sub-copper pillars 22, second sub-copper blocks 25 perpendicular to the second sub-copper pillars 22, and third copper blocks 27 perpendicular to the third copper pillars 26 on the surface of the IC control chip 12;

[0028] See also Figure 3 In this embodiment, the IC control chip 12 is also subjected to the above-mentioned step S1, and a layer of polyimide is first coated on its surface, and then the excess polyimide is removed to form a second polyimide layer 17. The thickness of the second polyimide layer 17 can be the same as that of the first polyimide layer 16, and both are used as insulating layers. Then, second sub-copper pillars 22 and second sub-copper blocks 25 located on the second sub-copper pillars 22 are made on both sides of the surface of the IC control chip 12. The second sub-copper pillars 22 and the second sub-copper blocks 25 are respectively arranged corresponding to the first sub-copper pillars 21 and the first sub-copper blocks 24, that is, the number and the spacing between each copper pillar or copper block are the same, and a third copper pillar 26 penetrating the second polyimide layer 17 and a third copper block 27 located on the third copper pillar 26 are made between the two second sub-copper pillars 22. The third copper pillar 26 and the second sub-copper pillar 22 are located on the same horizontal line, and the second sub-copper block 25 and the third copper block 27 are also located on the same horizontal line, that is, the corresponding structure on the IC control chip 12 is made for subsequent interconnection.

[0029] S3: using a metal frame 30, two first metal-based islands 13 respectively fixedly connected to the metal frame 30, and a second metal-based island 14 located between the first metal-based islands 13, so that the first copper blocks 19 of the two MOS switch chips 15 are connected to the bottom surfaces of the first metal-based islands 13 through conductive silver glue, the first metal-based islands 13 are connected to the first pins 28, and the second metal-based islands 14 are connected to the second pins 29;

[0030] See also Figure 4In this embodiment, the metal frame 30 is T-shaped, the cross-sectional area of ​​the first metal base island 13 is larger than the cross-sectional area of ​​the first copper block 19, and the cross-sectional area of ​​the second metal base island 14 is larger than the cross-sectional area of ​​the third copper block 27. A suitable metal frame 30 and three metal base islands are used, that is, two first metal base islands 13 are located on both sides of the metal frame 30, and the second metal base island 14 is located between the two first metal base islands 13. The metal frame 30 and the metal base islands are fixed together, so that the two MOS switch chips 15 are connected to the bottom surface of the metal base islands through conductive silver glue. The conductive silver glue combines the conductive particles together to form a conductive path through the bonding effect of the basic resin, so as to realize the conductive connection of the bonded materials, and a suitable curing temperature can be selected for bonding. The bottom surface of the first metal base island 13 is attached to the first copper block 19, and the surface of the first metal base island 13 extending in the horizontal direction is connected to the first pin 28. One end of the second metal base island 14 is connected to the metal frame 30, and the other end is connected to the second pin 29. The two MOS switch chips 15 are symmetrically arranged about the second metal base island 14. The metal frame 30 and the metal base island can improve the packaging efficiency of the power supply circuit and the working reliability of the chip.

[0031] S4: Flip the IC control chip 12 by 180° and connect it to the second metal base island 14 through conductive silver glue, the IC control chip 12 is placed between the first metal base islands 13 and the MOS switch chip 15 is symmetrically arranged on both sides of the IC control chip 12, the first sub-copper block 24 is connected to the second sub-copper block 25, the third copper block 27 is connected to the second metal base island 14, the first sub-copper block 24 and the second sub-copper block 25 are thermally bonded to form a second copper block 23, and the first sub-copper pillar 21 and the second copper pillar 22 are thermally bonded to form a second copper pillar 20;

[0032] See also Figure 5 In this embodiment, the number of the first copper pillar 18 and the second copper pillar 20 are both three, the number of the third copper pillar 26 is one, the thickness of the first copper block 19, the second copper block 23 and the third copper block 27 are the same, the height of the second metal-based island 14 is less than the height of the first metal-based island 13, and the second metal-based island 14, the first copper pillar 18 and the first sub-copper pillar 21 are located on the same horizontal line. The height of the first copper pillar 18 is less than the height of the second copper pillar 20, and the height of the third copper pillar 26 is also less than the height of the second copper pillar 20. The first copper block 19 is respectively bonded to the first polyimide layer 16 and the first metal-based island 13, the second copper block 23 is respectively bonded to the first polyimide layer 16 and the second polyimide layer 17, and the third copper block 27 is respectively bonded to the second polyimide layer 17 and the second metal-based island 14, so that the stability of the packaging structure is improved.

[0033] It should be noted that the IC control chip 12 is first turned 180°, with the surface of the chip with the second copper pillar 22 and the second copper block 25 facing downward, and then connected to the first metal base island 13 and the second metal base island 14 respectively through conductive silver glue, and the two sides of the IC control chip 12 are also connected to the two MOS switch chips 15 at the same time. After that, a thermal bonding process is performed to tightly bond the first copper block 24 of the MOS switch chip 15 and the second copper block 24 on the IC control chip 12 together to form a lower contact resistance. Bonding is a technology that directly combines two homogeneous or heterogeneous semiconductor materials with clean and atomically flat surfaces under certain conditions after surface cleaning and activation treatment, and bonds the wafers together through van der Waals force, molecular force or atomic force, which can reduce the conduction loss of the chip, and the resistance is reduced by more than 80% compared with the resistance of the wire bonding connection used in the traditional packaging.

[0034] S5: cutting the metal frame 30 and filling and sealing the plastic package 11 to obtain the power circuit packaging structure 10 .

[0035] See also Figure 6 In this embodiment, the material of the plastic package 11 is epoxy resin, and a molding machine is used to fill and seal the plastic package 11. The above-mentioned module is cut, that is, the metal frame 30 is cut, and then put into the molding machine for filling and sealing the plastic package 11. Epoxy resin has a good sealing effect and can effectively protect the internal chip. Finally, it becomes a packaged product with a structural appearance, namely, a power circuit packaging structure 10.

[0036] See also Figure 7The present invention provides a power circuit packaging structure 10, comprising a plastic package 11, an IC control chip 12 located on the plastic package 11, a first metal-based island 13 located on both sides of the IC control chip 12, a second metal-based island 14 connected to the IC control chip 12, and a MOS switch chip 15 connecting the IC control chip 12 and the first metal-based island 13, wherein a first polyimide layer 16 is arranged on the upper surface of the MOS switch chip 15, a second polyimide layer 17 is arranged on the lower surface of the IC control chip 12, a first copper column 18 penetrating the first polyimide layer 16 and arranged at intervals is arranged on one side of the MOS switch chip 15, and a first copper column 18 perpendicular to the first copper column 18 and attached to the first end surface of the first metal-based island 13 is provided. The first copper block 19 is combined with the first metal base island 13, the second end surface of the first metal base island 13 extends outwardly, the other side of the MOS switch chip 15 is provided with second copper pillars 20 respectively penetrating the first polyimide layer 16 and the second polyimide layer 17 and arranged at intervals, and a second copper block 23 perpendicular to the second copper pillars 20 and located between the first polyimide layer 16 and the second polyimide layer 17 is provided, the IC control chip 12 is provided with a third copper pillar 26 located between the second copper pillars 20 and penetrating the second polyimide layer 17, and a third copper block 27 perpendicular to the third copper pillars 26 and attached to one end of the second metal base island 14, and the other end of the second metal base island 14 is connected with a second pin 29 extending outwardly.

[0037] In this embodiment, the size of the first copper block 19 is larger than that of the second copper block 23, and the size of the first metal-based island 13 is larger than that of the second metal-based island 14. In the direction parallel to the plastic package body 11, the height of the second metal-based island 14 is smaller than that of the first metal-based island 13, and the first copper block 19, the second copper block 23 and the third copper block 27 are located on the same horizontal line. The structure of the MOS switch chip 15 is symmetrical, the first polyimide layer 16 is located on the upper surface of the MOS switch chip 15, the second polyimide layer 17 is located on the lower surface of the IC control chip 12, the two first metal-based islands 13 are symmetrically arranged about the second metal-based island 14, and the height of the two first metal-based islands 13 is less than the height of the IC control chip 12, the thickness of the first polyimide layer 16 and the second polyimide layer 17 can be the same, and both can play an insulating role to isolate each copper column, the bottom surface of the first metal-based island 13 is bonded to the first copper block 19, the second metal-based island 14 is bonded to the third copper block 27, and the second copper block 23 is respectively bonded to the first polyimide layer 16 and the second polyimide layer 17, which can improve the integration of the chip package, the first pin 28 and the second pin 29 extend outward, eliminating the lead connection, improving the current density and the integration of the chip package, and reducing the manufacturing cost.

[0038] The present invention provides a power circuit packaging structure and a packaging method thereof, wherein a polyimide layer is coated on the upper surfaces of two MOS switch chips 15, the polyimide at the lead window of the chip is removed to form a first polyimide layer 16, and a copper ball is implanted to grow to form a first copper pillar 18 that penetrates the first polyimide layer 16 and is arranged at intervals and a first sub-copper pillar 21 located on the other side of the MOS switch chip 15, a layer of metal is coated on the first copper pillar 18 and the first sub-copper pillar 21 and excess metal is removed to form a first copper block 19 located on the first copper pillar 18 and a first sub-copper block 24 located on the first sub-copper pillar 21, and a second copper ball is formed on the surface of the IC control chip 12. The polyimide layer 17, the second sub-copper pillars 22 that penetrate the second polyimide layer 17 and are arranged at intervals, the third copper pillars 26 located between the second sub-copper pillars 22, the second sub-copper block 25 that is perpendicular to the second sub-copper pillars 22, and the third copper block 27 that is perpendicular to the third copper pillars 26, use thermal bonding to connect the IC control chip 12 with the two MOS switch chips 15, and the two metal base islands are respectively connected to the two MOS switch chips 15. The two MOS switch chips 15 and the IC control chip 12 are precisely and cleverly fitted together within a small size range, so that the entire circuit has extremely low transmission resistance and extremely low parasitic inductance, which greatly reduces power consumption and increases the operating frequency. At the same time, the volume of the entire package is also reduced, so that the circuit has a smaller appearance, and the application scenarios are greatly broadened.

[0039] In all examples shown and described herein, any specific values ​​should be interpreted as merely exemplary and not as limiting, and thus other examples of the exemplary embodiments may have different values.

[0040] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0041] The above-mentioned embodiments only express several implementation methods of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the present invention. It should be pointed out that for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention.

Claims

1. A power circuit packaging structure, characterized in that: The invention comprises a plastic package, an IC control chip located on the plastic package, a first metal-based island located on both sides of the IC control chip, a second metal-based island connected to the IC control chip, and a MOS switch chip connecting the IC control chip and the first metal-based island, wherein a first polyimide layer is arranged on the upper surface of the MOS switch chip, a second polyimide layer is arranged on the lower surface of the IC control chip, a first copper column penetrating the first polyimide layer and arranged at intervals is arranged on one side of the MOS switch chip, and a first copper block perpendicular to the first copper column and attached to the first end surface of the first metal-based island is arranged, and the The second end face of the first metal-based island is provided with a first pin extending outwardly, and the other side of the MOS switch chip is provided with second copper pillars respectively penetrating the first polyimide layer and the second polyimide layer and arranged at intervals, and a second copper block perpendicular to the second copper pillars and located between the first polyimide layer and the second polyimide layer; the IC control chip is provided with a third copper pillar located between the second copper pillars and penetrating the second polyimide layer, and a third copper block perpendicular to the third copper pillar and attached to one end of the second metal-based island; the other end of the second metal-based island is connected with a second pin extending outwardly.

2. The power circuit packaging structure according to claim 1, characterized in that: The size of the first copper block is larger than that of the second copper block, and the size of the first metal-based island is larger than that of the second metal-based island.

3. The power circuit packaging structure according to claim 1, characterized in that: In a direction parallel to the plastic package body, the height of the second metal-based island is smaller than the height of the first metal-based island, and the first copper block, the second copper block and the third copper block are located on the same horizontal line.

4. A power circuit packaging method, characterized in that: The following steps are involved: A polyimide layer is coated on the upper surfaces of the two MOS switch chips, the polyimide at the lead window of the chip is removed to form a first polyimide layer, and copper balls are implanted to grow to form first copper pillars that are arranged at intervals and penetrate the first polyimide layer and a first sub-copper pillar located on the other side of the MOS switch chip, a layer of metal is coated on the first copper pillar and the first sub-copper pillar and excess metal is removed to form a first copper block located on the first copper pillar and a first sub-copper block located on the first sub-copper pillar; A second polyimide layer, second sub-copper pillars penetrating the second polyimide layer and arranged at intervals, a third copper pillar located between the second sub-copper pillars, a second sub-copper block perpendicular to the second sub-copper pillars, and a third copper block perpendicular to the third copper pillars are formed on the surface of the IC control chip; A metal frame, two first metal-based islands respectively fixedly connected to the metal frame, and a second metal-based island located between the first metal-based islands are used, so that the first copper blocks of the two MOS switch chips are connected to the bottom surfaces of the first metal-based islands through conductive silver glue, the first metal-based islands are connected to the first pins, and the second metal-based islands are connected to the second pins; The IC control chip is flipped 180° and connected to the second metal base island through conductive silver glue, the IC control chip is placed between the first metal base islands and the MOS switch chip is symmetrically arranged on both sides of the IC control chip, the first sub-copper block is connected to the second sub-copper block, the third copper block is connected to the second metal base island, the first sub-copper block and the second sub-copper block are thermally bonded to form a second copper block, and the first sub-copper column and the second sub-copper column are thermally bonded to form a second copper column; The metal frame is cut and filled with a plastic package to obtain a power circuit packaging structure.

5. The power circuit packaging method according to claim 4, characterized in that: The material of the plastic sealing body is epoxy resin, and a molding machine is used to fill and seal the plastic sealing body.

6. The power circuit packaging method according to claim 4, characterized in that: The height of the second metal-based island is smaller than that of the first metal-based island, and the second metal-based island, the first copper pillar and the first sub-copper pillar are located on the same horizontal line.

7. The power circuit packaging method according to claim 4, characterized in that: The metal frame is T-shaped, the cross-sectional area of ​​the first metal-based island is larger than the cross-sectional area of ​​the first copper block, and the cross-sectional area of ​​the second metal-based island is larger than the cross-sectional area of ​​the third copper block.

8. The power circuit packaging method according to claim 4, characterized in that: The number of the first copper pillars and the number of the second copper pillars are both three, the number of the third copper pillar is one, and the thickness of the first copper block, the second copper block and the third copper block are the same.

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