Defect Detection Method for Semiconductor Devices and Electronic Equipment

Abstract

The present invention provides a defect detection method for quickly detecting whether there are defects in the metal silicide layer of a semiconductor device, which is applied to the semiconductor field. By replacing the existing TEM detection for detecting defects in the metal silicide layer with YE on-line detection, the problem that the TEM detection method can only detect one point or multiple points of one chip in a wafer at a time, and cannot detect multiple points on multiple chips on the same wafer simultaneously is avoided. Since the YE on-line detection uses a chip-to-chip detection method, and then, the detection images of multiple chips are compared, and the places with differences are determined as abnormal positions. Therefore, the detection method provided by the present invention avoids the problems that the TEM detection requires slicing the wafer to make a wafer sample and then detecting the sample, which causes the sample to be unable to continue the subsequent experiments, is uneconomical, and cannot maintain the single variable of the test.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and particularly to a method for detecting defects of a semiconductor device and an electronic device. Background Art

[0002] As the semiconductor manufacturing process size becomes smaller and smaller, failure analysis becomes increasingly difficult. A very small defect may cause the failure of a device, thereby affecting the operation of the entire chip. For example, when a semiconductor contacts a metal, a barrier layer is often formed to become a non-rectifying contact, that is, an ohmic contact. The contact resistance of an ideal ohmic contact should be very small compared to a semiconductor sample or device, so that when current flows through the sample or device, the voltage drop across the ohmic contact should be much smaller than the voltage drop of the sample or device itself, and such a contact does not affect the current-voltage characteristics of the device. Currently, to form a good ohmic contact, high-concentration impurity doping is added to the semiconductor. By reacting refractory metal cobalt (Co) with silicon, a metal silicide with thermal stability is generated, and the interface between silicon and the refractory metal has a low resistivity, thereby greatly reducing the contact resistance of the connection points of the source, drain, and gate.

[0003] Currently, the traditional method for detecting whether the Co silicide metallization is abnormal is to perform TEM (Transmission Electron Microscope) inspection on a wafer with metal silicide formed. By obtaining a vertical sectional view of the detection point through TEM, it is then determined whether it is abnormal. Since the working principle of TEM detection is to thin the sample to be detected by means of cutting, grinding, ion thinning, etc., and then place it in the TEM observation chamber, and irradiate a point or several points of a chip in the wafer of the sample with an electron beam accelerated by high voltage, magnify the morphology of the sample, project it onto the screen, take a photo, and then analyze it.

[0004] Based on the principle of TEM inspection, the following deficiencies exist in TEM inspection:

[0005] 1. TEM inspection can only detect one or several points on one chip of one wafer at a time, and it cannot obtain the metallization conditions of a large number of positions on one chip in the same wafer simultaneously;

[0006] 2. It cannot detect the metallization conditions of multiple positions with various complexities of patterns in the same chip;

[0007] 3. The feedback time of TEM is long, and it takes at least 1 - 2 days to obtain the detection result;

[0008] 4. TEM inspection requires slicing the wafer or chip, so the experimental wafer or chip cannot continue with subsequent tests, which is not cost-effective and does not maintain the single variable of the experiment. Summary of the Invention

[0009] The object of the present invention is to provide a method for defect detection of semiconductor devices to achieve rapid and multi-point detection of whether there are defects in the metal silicide layers formed on multiple chips in a wafer.

[0010] In a first aspect, to solve the above technical problems, the present invention provides a method for defect detection of semiconductor devices, including the following steps: providing a wafer, the wafer includes multiple chips, and a metal silicide layer is formed on each chip at a corresponding position of its active region.

[0011] Using the YE sampling rate set in the YE on-line inspection machine, sampling the wafer to obtain a defect detection sample.

[0012] Using the YE on-line inspection machine to perform YE on-line defect detection on the defect detection sample, and generating an SEM image and an EDX elemental analysis diagram of the defect detection sample respectively.

[0013] According to the comparison relationship between the SEM image and the reference SEM image, and / or the comparison relationship between the EDX elemental analysis diagram and the reference EDX elemental analysis diagram, determining whether there are defects in the metal silicide layers of each chip in the defect detection sample.

[0014] Further, the material of the metal silicide layer may include one or more of titanium silicide, cobalt silicide, nickel silicide or molybdenum silicide.

[0015] Further, the step of sampling the wafer using the YE sampling rate set in the YE on-line inspection machine to obtain a defect detection sample may include: selecting a preset number of chips from the wafer as a set of chips to be detected, and taking at least one selected area of a chip from the set of chips to be detected as the target detection area of the chip.

[0016] According to the position information of the target detection area of the chip and the preset position relationship between the chips in the set of chips to be detected, determining the position information of the target detection areas of the remaining chips in the set of chips to be detected.

[0017] Taking the chips in the set of chips to be detected and the target detection areas of each chip as the defect detection sample.

[0018] Further, the steps of using the YE on-line inspection tool to perform YE on-line defect inspection on the defect inspection sample may include: using the YE on-line inspection tool to sequentially perform electron scanning on the target inspection area of each chip in the defect inspection sample to obtain an SEM image of the target inspection area of each chip.

[0019] Using the EDX spectrometer in the YE on-line inspection tool, sequentially perform electron scanning on the target inspection area of each chip in the defect inspection sample to obtain an EDX elemental analysis map of the target inspection area of each chip.

[0020] Further, the steps of determining whether there are defects in the metal silicide layer of each chip in the defect inspection sample according to the comparison relationship between the SEM image and the reference SEM image, and / or the comparison relationship between the EDX elemental analysis map and the reference EDX elemental analysis map may include: comparing the SEM image of the target inspection area of each chip with the reference SEM image, and selecting the chips whose SEM images of the target inspection area of all chips are inconsistent with the reference SEM image.

[0021] For each of the selected chips, compare the EDX elemental analysis map of the selected chip with the reference EDX elemental analysis map, and determine the chips with a metal content lower than the preset threshold in the EDX elemental analysis map of the selected chip as the chips with defects in the metal silicide layer.

[0022] Further, the reference SEM image may be an SEM image of a chip without defects in the preset metal silicide layer, or may be an SEM image of a chip in the defect inspection sample.

[0023] Further, the reference EDX elemental analysis map may be an EDX elemental analysis map of a chip without defects in the preset metal silicide layer, or may be an EDX elemental analysis map of a chip in the defect inspection sample.

[0024] Further, the steps of forming a metal silicide layer stacked on the corresponding position of the active region on the chip may include: the chip includes a substrate, and a gate structure is formed on the surface of the substrate.

[0025] Source regions and drain regions are respectively formed in the substrate on both sides of the gate structure.

[0026] A metal layer is formed on the surface of the substrate, and a silicidation reaction is performed on the substrate to form metal silicide layers on the source region, the drain region, and the top surface of the gate structure respectively.

[0027] Further, the substrate may be a silicon substrate.

[0028] In a second aspect, the present invention further provides an electronic device, including a processor, a communication interface, a memory, and a communication bus. Among them, the processor, the communication interface, and the memory complete mutual communication through the communication bus.

[0029] The memory is used to store a computer program.

[0030] The processor is configured to implement the steps of the defect detection method of the semiconductor device as described above when executing the program stored on the memory.

[0031] In a third aspect, an embodiment of the present invention further provides a computer-readable storage medium. The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of any of the above-described defect detection methods of the semiconductor device are implemented.

[0032] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0033] The present invention provides a defect detection method for quickly detecting whether there are defects in the metal silicide layer of a semiconductor device at multiple points. Specifically, in the defect detection method of the semiconductor device provided by the present invention, it replaces the existing TEM detection for detecting defects in the metal silicide layer with YE on-line detection, thereby avoiding the problem that the TEM detection method can only detect one point or multiple points of one chip in a wafer at a time, and cannot detect multiple points on multiple chips on the same wafer simultaneously. And, since the YE on-line detection method introduced by the present invention uses a chip-to-chip detection method, and then, the detection images of multiple chips are compared, and the places with differences are determined as abnormal positions. Therefore, the detection method provided by the present invention avoids the problems that the TEM detection requires slicing the wafer to make a wafer sample and then detecting the sample, which causes the sample to be unable to continue subsequent experiments, is not cost-effective, and cannot maintain a single variable in the test.

[0034] Furthermore, in the defect detection method of the semiconductor device provided by the present invention, it combines YE on-line detection and EDX elemental content comparative analysis, so as to perform quantitative analysis on the SEM images obtained by YE on-line detection through EDX elemental content analysis, and further accurately and quickly determine the metal silicide abnormality problems of multiple points on multiple chips in the wafer. Description of the Drawings

[0035] Figures 1a to 1d Comparison diagram of two SEM graphs of the same graphic area of different wafers under different test conditions provided in an embodiment of the present invention Figure 1a and Figure 1b, and EDX elemental analysis diagrams respectively corresponding to the same graphic areas of different wafers Figure 1c and Figure 1d .

[0036] Figure 2 is a schematic flow chart of a method for detecting defects of a semiconductor device provided in an embodiment of the present invention. Detailed implementation manners

[0037] As described in the background art, currently, the conventional method for detecting whether the Co silicide metallization is abnormal is to perform TEM (Transmission Electron Microscope) inspection on the wafer formed with the metal silicide, and obtain a sliced view in the vertical direction of the detection point through TEM, so as to judge whether it is abnormal. Since the working principle of TEM detection is to thin the sample to be detected by means of cutting, grinding, ion thinning, etc., and then put it into the TEM observation chamber, and irradiate a point or several points of a chip in the wafer of the sample with an electron beam accelerated by high voltage, magnify and project the morphology of the sample onto the screen, take a photo, and then perform analysis.

[0038] Based on the principle of TEM inspection, the following deficiencies exist in TEM inspection:

[0039] 1. TEM inspection can only detect one or several points on one chip of one wafer at a time, and it cannot obtain the metallization conditions of a large number of positions of one chip in the same wafer simultaneously;

[0040] 2. It cannot detect the metallization conditions of multiple positions with various complexities of graphics in the same chip;

[0041] 3. The feedback time of TEM is long, and it takes at least 1 - 2 days to obtain the detection result;

[0042] 4. TEM inspection requires slicing the wafer or chip, so the experimental wafer or chip cannot continue with subsequent experiments, which is not cost-effective, and at the same time, it cannot maintain the single variable of the experiment.

[0043] In view of this problem, the researchers of the present invention found that: when a high-energy electron beam continuously irradiates the surface of the wafer, the high-energy incident electrons bombard the extranuclear electrons of the atoms, generating secondary electrons. The number of extranuclear electrons of different materials is different, and there are great differences in the quantity and density of the generated secondary extranuclear electrons. These signals are received by the corresponding receivers, and through amplification, modulation, etc., corresponding characteristic images are generated, such as SEM images. Therefore, the generated images and the results of elemental analysis are different for different materials and contents.

[0044] Exemplarily, such as Figure 1a and Figure 1bSEM image comparison diagrams of the same graphic area of different wafers under different test conditions, and Figure 1a EDX elemental analysis of the corresponding graphic positions Figure 1c and Figure 1b EDX elemental analysis of the corresponding graphic positions Figure 1d . According to Figure 1a and Figure 1b it can be seen that Figure 1b there are more white spots of different degrees formed on the metal silicide layer on Figure 1a than Figure 1a . Thus, it can be known that Figure 1b the metallization degree of the graphic structure corresponding to Figure 1c is better than that of Figure 1d . According to Figure 1c and Figure 1d it can be seen that Figure 1c the metal content (620) contained in the metal silicide formed on the graphic structure corresponding to Figure 1d is higher than the metal content (310) contained in the metal silicide formed on the graphic structure corresponding to

[0045] . Thus, it can be known that

[0046] the metallization degree of the graphic structure corresponding to

[0047] is better than that of

[0048] . At the same time, the scanning principle adopted by the YE on-line detection method is the chip-to-chip scanning principle, that is, the YE on-line high-energy electron beam can continuously irradiate a point, several points or the entire surface of a chip, so that the SEM images obtained by the YE on-line detection machine can include the morphological states of multiple complex graphics at multiple positions on a chip.

[0046] Therefore, the researchers of the present invention proposed to combine YE on-line detection and EDX elemental content comparative analysis, so as to quantitatively analyze the SEM images obtained by YE on-line detection through EDX elemental content analysis, and further realize the scheme of accurately and quickly determining the abnormal problems of metal silicides at multiple points of multiple chips in a wafer.

[0047] In summary, the present invention provides a method for detecting defects of semiconductor devices to achieve rapid and multi-point detection of whether there are defects in the metal silicide layers formed on multiple chips in a wafer.

[0048] The following further details the method for detecting defects of semiconductor devices proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the drawings are all in a very simplified form and use non-precise scales, only for the purpose of conveniently and clearly assisting in explaining the purpose of the embodiments of the present invention. Many specific details are set forth in the following description in order to fully understand the present invention, but the present invention can also be implemented in other ways different from those described herein, so the present invention is not limited by the specific embodiments disclosed below.

[0049] As shown in this application and the claims, unless the context clearly indicates otherwise, words such as "a", "an", "one", and / or "the" are not specifically singular and may also include the plural. Generally speaking, the terms "comprising" and "including" only indicate the inclusion of the clearly identified steps and elements, and these steps and elements do not constitute an exclusive list. The method or device may also include other steps or elements. When detailing the embodiments of the present invention, for ease of explanation, the cross-sectional views showing the device structure may be enlarged locally out of the general scale, and the schematic diagrams are only examples and should not limit the scope of protection of the present invention herein. In addition, in actual production, three-dimensional spatial dimensions including length, width, and depth should be included.

[0050] Specifically refer to Figure 2 , Figure 2 is a schematic flow chart of a method for detecting defects of a semiconductor device provided by an embodiment of the present invention. Specifically, the method for detecting defects of the semiconductor device at least includes the following steps:

[0051] Step S100, provide a wafer, the wafer includes a plurality of chips, and a metal silicide layer is formed on each of the chips at a corresponding position on its active region.

[0052] In this embodiment, a wafer (wafer) can be provided first, where the wafer may include a plurality of chips, for example, 20 chips, and the same pattern is formed on all the chips on the wafer. Exemplarily, a metal silicide layer is formed on each of the chips in the embodiments of the present invention at a corresponding position on its active region. Specifically, the method of forming the metal silicide layer on each of the chips may be: the chip includes a substrate, and a gate structure is formed on the surface of the substrate; a source region and a drain region are respectively formed in the substrate on both sides of the gate structure; a metal layer is formed on the surface of the substrate, and a silicidation reaction is performed on the substrate to form metal silicide layers on the source region, the drain region, and the top surface of the gate structure respectively.

[0053] Among them, the material of the metal silicide layer may include one or more of titanium silicide, cobalt silicide, nickel silicide, or molybdenum silicide. Exemplarily, the material of the metal silicide layers formed on all the chips in the embodiments of the present invention is cobalt silicide.

[0054] Step S200, use the YE sampling rate set in the YE online inspection machine to sample the wafer to obtain a defect detection sample.

[0055] In this embodiment, one, more, or all of the chips in the wafer provided in step S100 can be selected as the defect detection sample according to the actual situation.

[0056] As an embodiment, the present invention provides a specific method for sampling the wafer to obtain a defect detection sample as follows: Select a preset number of chips from the wafer as the set of chips to be detected, and use the selected area of at least one chip selected from the set of chips to be detected as the target detection area of the chip; According to the position information of the target detection area of the chip and the preset positional relationship between the chips in the set of chips to be detected, determine the position information of the target detection areas of the remaining chips in the set of chips to be detected; Use the chips in the set of chips to be detected and the target detection areas of the chips as the defect detection samples.

[0057] Specifically, since on a wafer containing multiple chips, the relative positions of the multiple chips are fixed, and there will be a corresponding coordinate position for any position on each chip. We can calculate the coordinate information of the same position (point) on other chips on the same wafer as a point on one chip (the first chip). Therefore, after determining the wafer to be subjected to defect detection in the embodiment of the present invention, multiple chips can be selected from the wafer. For example, 17 (or other numbers) can be selected from the middle, edge, etc. of the wafer as the set of chips to be detected. Then, select one chip from the set of chips to be detected, that is, 17 chips. Then, use the selected area (the area where detection defects may exist) on one chip as the target detection area of the chip. Then, use the YE online detection machine to determine the coordinate information (position information) of the target detection area of the chip. Then, use the coordinate information of the target detection area of the chip and the positional relationship between the chips in the set of chips to be detected to calculate the coordinate information of the same position (target detection area) of the remaining 16 chips as the chip whose coordinate information was just determined. That is, through the above method, the coordinate information of the target detection area to be subjected to YE online detection for each of the 17 chips in the set of chips to be detected can be obtained.

[0058] Step S300, use the YE online detection machine to perform YE online defect detection on the defect detection sample, and generate an SEM image and an EDX elemental analysis map of the defect detection sample respectively.

[0059] In this embodiment, after the coordinate information of the target detection region of each chip in the defect detection sample is determined in step S200, the YE online inspection machine can be used to sequentially perform an electronic scan on the target detection region of each chip in the defect detection sample to obtain an SEM image of the target detection region of each chip; then, the EDX spectrometer in the YE online inspection machine can be used to sequentially perform an electronic scan on the target detection region of each chip in the defect detection sample to obtain an EDX elemental analysis map of the target detection region of each chip.

[0060] It can be understood that in the semiconductor device defect detection method provided by the present invention, the SEM image and the EDX elemental analysis map formed for each chip in each defect detection sample are images obtained respectively for the same position (target detection region) of the chip. Obviously, the defect detection method provided by the present invention introduces YE online inspection, thereby avoiding the problem that the TEM detection method can only detect one point or multiple points of one chip in a wafer at a time and cannot detect multiple points on multiple chips on the same wafer simultaneously.

[0061] Step S400: Determine whether there are defects in the metal silicide layers of the chips in the defect detection sample according to the comparison relationship between the SEM image and the reference SEM image, and / or the comparison relationship between the EDX elemental analysis map and the reference EDX elemental analysis map.

[0062] Among them, the reference SEM image can be an SEM image of a chip whose preset metal silicide layer does not contain defects, or the reference SEM image can be an SEM image of a chip in the defect detection sample. And the reference EDX elemental analysis map can be an EDX elemental analysis map of a chip whose preset metal silicide layer does not contain defects, or the reference EDX elemental analysis map can be an EDX elemental analysis map of a chip in the defect detection sample.

[0063] In this embodiment, for each chip in the defect detection sample, the SEM image of the chip can be compared separately with the reference SEM image. If there are any differences between the SEM image of the chip and the reference SEM image, it indicates that there are defects in the target detection area of the chip. If the SEM image of the chip is consistent with the reference SEM image, it indicates that there are no defects in the target detection area of the chip. Similarly, the EDX elemental analysis map of the chip can be compared separately with the reference EDX elemental analysis map. If the content of the metal elements in the EDX elemental analysis map of the chip is different from that in the reference EDX elemental analysis map, it indicates that there are defects in the target detection area of the chip. If the content of the metal elements in the EDX elemental analysis map of the chip is the same as that in the reference EDX elemental analysis map, it indicates that there are no defects in the target detection area of the chip. Moreover, the reference SEM image and the reference EDX elemental analysis map can be used simultaneously to judge the chip defects for each chip.

[0064] As an embodiment, the present invention provides a specific method for determining whether there are defects in the metal silicide layers of each chip in the defect detection sample according to the comparison relationship between the SEM image and the reference SEM image, and the comparison relationship between the EDX elemental analysis map and the reference EDX elemental analysis map, including the following steps:

[0065] Compare the SEM image of the target detection area of each chip with the reference SEM image, and select all the chips whose SEM images of the target detection areas are inconsistent with the reference SEM image.

[0066] For each selected chip, compare the EDX elemental analysis map of the selected chip with the reference EDX elemental analysis map, and determine the chips with the metal content in the EDX elemental analysis map of the selected chips lower than the preset threshold as the chips with defects in the metal silicide layer.

[0067] In this embodiment, when using the SEM image of the target detection area of each chip to compare with the reference SEM image, if there are any differences between the SEM image of the target detection area of the chip and the reference SEM image, it indicates that there are defects in the target detection area of the chip. If the SEM image of the target detection area of the chip is consistent with the reference SEM image, it indicates that there are no defects in the target detection area of the chip. Then, compare the EDX elemental analysis maps of the chips whose SEM images are inconsistent with the reference SEM image, so as to determine which chips in the defect detection sample have defects in the formed metal silicide layer through the secondary image comparison method.

[0068] It should be noted that the SEM image and the reference EDX elemental analysis diagram may be a single SEM image or EDX elemental analysis diagram, or may also be multiple SEM images or EDX elemental analysis diagrams. The present invention does not make specific limitations on this.

[0069] In summary, the present invention provides a defect detection method for quickly and multi-point detecting whether there are defects in the metal silicide layer of a semiconductor device. Specifically, in the defect detection method of the semiconductor device provided by the present invention, it replaces the existing TEM detection for detecting defects in the metal silicide layer with YE on-line detection, thereby avoiding the problem that the TEM detection method can only detect one point or multiple points of one chip in a wafer at a time, and cannot detect multiple points on multiple chips on the same wafer simultaneously. And, since the YE on-line detection method introduced by the present invention uses a chip-to-chip detection method, and then, the detection images of multiple chips are compared, and the places with differences are determined as abnormal positions. Therefore, the detection method provided by the present invention avoids the problems that the TEM detection needs to slice the wafer to make a wafer sample and then can detect the sample, which causes the sample to be unable to continue subsequent experiments, is not economical and practical, and at the same time cannot maintain the single variable of the test.

[0070] Furthermore, in the defect detection method of the semiconductor device provided by the present invention, it combines YE on-line detection and EDX elemental content comparative analysis, so as to quantitatively analyze the SEM image obtained by YE on-line detection through EDX elemental content analysis, and further achieve accurate and rapid determination of the metal silicide abnormality problems of multiple points of multiple chips in the wafer.

[0071] In addition, an embodiment of the present invention also provides an electronic device, including a processor, a communication interface, a memory, and a communication bus. Among them, the processor, the communication interface, and the memory complete mutual communication through the communication bus.

[0072] The memory is used to store a computer program.

[0073] The processor is used to implement a defect detection method of a semiconductor device provided by an embodiment of the present invention when executing the program stored on the memory.

[0074] Specifically, the above-mentioned defect detection method of a semiconductor device includes: providing a wafer, the wafer includes multiple chips, and a metal silicide layer is formed on each chip at a corresponding position in its active region.

[0075] Using the YE sampling rate set in the YE on-line detection machine, sample the wafer to obtain a defect detection sample.

[0076] Use the YE on-line inspection machine to perform YE on-line defect inspection on the defect detection sample, and generate an SEM image and an EDX elemental analysis map of the defect detection sample respectively.

[0077] Determine whether there are defects in the metal silicide layers of the chips in the defect detection sample according to the comparison relationship between the SEM image and the reference SEM image, and / or the comparison relationship between the EDX elemental analysis map and the reference EDX elemental analysis map.

[0078] For the specific implementation of each step of this method and the relevant explanatory content, reference can be made to the method embodiment shown in FIG. 1 above, which will not be elaborated here.

[0079] In addition, other implementation manners of a defect detection method for a semiconductor device implemented by a processor executing a program stored in a memory are the same as those mentioned in the method embodiment part above, and will not be elaborated here either.

[0080] The communication bus mentioned in the above electronic device may be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. This communication bus can be divided into an address bus, a data bus, a control bus, etc. For the sake of convenience of representation, only a thick line is used in the figure, but it does not mean that there is only one bus or one type of bus.

[0081] The communication interface is used for communication between the above electronic device and other devices.

[0082] The memory may include a Random Access Memory (RAM), and may also include a Non-Volatile Memory (NVM), such as at least one disk memory. Optionally, the memory 303 may also be at least one storage device located far from the aforementioned processor.

[0083] The above-mentioned processor 701 may be a general-purpose processor, including a Central Processing Unit (CPU), a Network Processor (NP), etc.; it may also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

[0084] In another embodiment provided by the present invention, there is also provided a computer-readable storage medium storing instructions, which when running on a computer, cause the computer to execute the defect detection method of the semiconductor device described in any one of the above embodiments.

[0085] In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using software, it may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions described in the embodiments of the present invention are generated in whole or in part. The computer may be a general-purpose computer, a dedicated computer, a computer network, or other programmable devices. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by wire (such as coaxial cable, optical fiber, Digital Subscriber Line (DSL)) or wirelessly (such as infrared, wireless, microwave, etc.). The computer-readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server or data center integrating one or more available media. The available medium may be a magnetic medium (such as a floppy disk, hard disk, magnetic tape), an optical medium (such as a DVD), or a semiconductor medium (such as a Solid State Disk (SSD)).

[0086] It should be noted that in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprising", "including" or any other variants thereof are intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements not only includes those elements but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the said element.

[0087] Each embodiment in this specification is described in a related manner. For the same or similar parts among the embodiments, reference can be made to each other, and the key point of each embodiment is to illustrate the differences from other embodiments. In particular, for the embodiments of the device, electronic device and computer-readable storage medium, since they are basically similar to the method embodiments, the description is relatively simple, and reference can be made to the relevant parts of the method embodiments for the related content.

[0088] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are all included in the protection scope of the present invention.

Claims

1. A method for defect detection of a semiconductor device, characterized in that, It includes the following steps: Provide a wafer, the wafer includes a plurality of chips, and a metal silicide layer is formed on each chip at a corresponding position of its active region; Use the YE sampling rate set in the YE online inspection machine to sample the wafer to obtain a defect detection sample; wherein, the step of using the YE sampling rate set in the YE online inspection machine to sample the wafer to obtain a defect detection sample includes: Select a preset number of chips from the wafer as the set of chips to be detected, and use at least one selected area of the chips selected from the set of chips to be detected as the target detection area of the chip; According to the position information of the target detection area of the chip and the preset position relationship between the chips in the set of chips to be detected, determine the position information of the target detection areas of the remaining chips in the set of chips to be detected; Use the chips in the set of chips to be detected and the target detection areas of each chip as the defect detection sample; Use the YE online inspection machine to perform YE online defect detection on the defect detection sample, and generate an SEM image and an EDX elemental analysis map of the defect detection sample respectively; wherein, the step of using the YE online inspection machine to perform YE online defect detection on the defect detection sample includes: Use the YE online inspection machine to sequentially perform electron scanning on the target detection area of each chip in the defect detection sample to obtain an SEM image of the target detection area of each chip; Use the EDX spectrometer in the YE online inspection machine to sequentially perform electron scanning on the target detection area of each chip in the defect detection sample to obtain an EDX elemental analysis map of the target detection area of each chip; According to the comparison relationship between the SEM image and the reference SEM image, and the comparison relationship between the EDX elemental analysis map and the reference EDX elemental analysis map, determine whether there are defects in the metal silicide layer of each chip in the defect detection sample; The step of determining whether there are defects in the metal silicide layer of each chip in the defect detection sample according to the comparison relationship between the SEM image and the reference SEM image, and the comparison relationship between the EDX elemental analysis map and the reference EDX elemental analysis map includes: Compare the SEM image of the target detection area of each chip with the reference SEM image, and select all the chips whose SEM images of the target detection areas are inconsistent with the reference SEM image; For each selected chip, compare the EDX elemental analysis map of the selected chip with the reference EDX elemental analysis map, and determine the chips whose metal content in the EDX elemental analysis map of the selected chip is lower than the preset threshold as the chips with defects in the metal silicide layer.

2. The method for defect detection of the semiconductor device according to claim 1, characterized in that, The material of the metal silicide layer includes one or more of titanium silicide, cobalt silicide, nickel silicide or molybdenum silicide.

3. The method for defect detection of the semiconductor device according to claim 1, characterized in that, The reference SEM image is the SEM image of a chip without defects in the preset metal silicide layer, or the SEM image of a chip in the defect detection sample.

4. The method for detecting defects of a semiconductor device according to claim 1, characterized in that, The reference EDX elemental analysis diagram is an EDX elemental analysis diagram of a preset metal silicide layer that does not include defective chips, or an EDX elemental analysis diagram of the chips in the defect detection sample.

5. The method for detecting defects of the semiconductor device according to claim 1, wherein, The step of forming a metal silicide layer stacked on corresponding positions of the active regions of the chip includes: The chip includes a substrate, and a gate structure is formed on the surface of the substrate; A source region and a drain region are respectively formed in the substrate on both sides of the gate structure; A metal layer is formed on the surface of the substrate, and a silicidation reaction is performed on the substrate to respectively form a metal silicide layer on the source region, the drain region, and the top surface of the gate structure.

6. The method for defect detection of a semiconductor device according to claim 5, characterized in that, The substrate is a silicon substrate.

7. An electronic device, characterized in that, It includes a processor, a communication interface, a memory, and a communication bus. Among them, the processor, the communication interface, and the memory complete mutual communication through the communication bus; The memory is used for storing computer programs; When the processor is used to execute the programs stored on the memory, it implements the steps of the defect detection method of the semiconductor device according to any one of claims 1-6.

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