semiconductor structure

Abstract

The present invention provides a semiconductor structure. By providing at least two isolation sidewalls with successively lowered bottoms on the sides of a gate structure and further lowering the bottom of a contact plug so that it extends into the substrate, the metal silicide layer is recessed deeper into the substrate, increasing the distance between the metal silicide layer and the gate structure. This effectively alleviates the problem of metal diffusion into the gate structure that occurs during and after the metal silicide layer is prepared.

Description

[0001] This application is a divisional application of application number 202010231321.8, application date 2020.03.27, and invention name “Semiconductor structure and its formation method”. Technical Field

[0002] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor structure. Background Art

[0003] As the main device in semiconductor integrated circuits, transistor devices are widely used in memory, logic circuits, etc. Figure 1 As shown, the transistor generally includes a gate structure 20 formed on the surface of a substrate 10 and a source / drain region 30 formed in the substrate 10 and located on the side of the gate structure 20, wherein the source / drain region 30 usually also needs to be electrically led out through a contact plug 50, that is, the bottom of the contact plug 50 extends to the substrate 10 to be electrically connected to the source / drain region 30.

[0004] In the prior art, in order to reduce the contact resistance between the contact plug 50 and the source / drain region 30, a metal silicide layer 40 is generally formed on the contact surface of the source / drain region 30, thereby enabling the contact plug 50 to be electrically connected to the source / drain region 30 through the metal silicide layer 40. However, in existing semiconductor structures, metal in the metal silicide layer 40 often diffuses into the gate structure 20 on its side, thereby affecting the semiconductor structure. Summary of the Invention

[0005] The object of the present invention is to provide a semiconductor structure to solve the problem that the metal in the metal silicide layer easily diffuses into the gate structure.

[0006] To solve the above technical problems, the present invention provides a semiconductor structure, comprising: a substrate; at least one gate structure formed on the substrate; a first isolation sidewall covering the sidewall of the gate structure, and the bottom of the first isolation sidewall is lower than the bottom of the gate structure; a second isolation sidewall covering the sidewall of the first isolation sidewall away from the gate structure, and the bottom of the second isolation sidewall is lower than the bottom of the first isolation sidewall; a third isolation sidewall covering the sidewall of the second isolation sidewall away from the gate structure, and the bottom of the third isolation sidewall is lower than the bottom of the first isolation sidewall; a contact plug formed on the side of the third isolation sidewall away from the gate structure, and the bottom of the contact plug is lower than the bottom of the second isolation sidewall and extends into the substrate; and a metal silicide layer located in the substrate at the bottom of the contact plug and directly contacting the contact plug and the substrate.

[0007] Optionally, the bottom of the second isolation spacer further extends laterally in a direction away from the gate structure to cover the surface of the substrate, and the contact plug penetrates the second isolation spacer to extend into the substrate.

[0008] Optionally, a top portion of an edge of the metal silicide layer contacts a bottom surface of the second isolation spacer.

[0009] Optionally, a boundary of the metal silicide layer close to the gate structure does not extend beyond a boundary of the second isolation sidewall close to the gate structure.

[0010] Optionally, the bottom of the third isolation spacer further extends laterally in a direction away from the gate structure to cover the second isolation spacer, and the contact plug sequentially penetrates the third isolation spacer and the second isolation spacer to extend into the substrate.

[0011] Optionally, the third isolation sidewall does not continuously cover the second isolation sidewall.

[0012] Optionally, a portion of the sidewall of the contact plug contacts the sidewall of the second isolation spacer, and another portion of the sidewall of the contact plug contacts the sidewall of the third isolation spacer.

[0013] Optionally, the top width of the contact plug is greater than the bottom width of the contact plug, wherein the top sidewall of the contact plug is adjacent to the sidewall of the second isolation spacer, and the bottom sidewall of the contact plug is adjacent to the sidewall of the third isolation spacer.

[0014] Optionally, the semiconductor structure further includes a fourth isolation sidewall, which is located at least between the sidewall of the gate structure and the first isolation sidewall, wherein the bottom of the fourth isolation sidewall is lower than the bottom of the gate structure and higher than the bottom of the first isolation sidewall.

[0015] Optionally, the fourth isolation spacer also covers the top surface of the gate structure.

[0016] Optionally, the semiconductor structure includes at least two gate structures, wherein two adjacent gate structures share a contact plug, and the first isolation sidewall, the second isolation sidewall and the third isolation sidewall are arranged between the contact plug and the two gate structures on both sides.

[0017] Optionally, a distance between two third isolation spacers on both sides of the contact plug is smaller than or equal to a width of the contact plug, and a sidewall of the contact plug contacts sidewalls of the two third isolation spacers on both sides.

[0018] In the semiconductor structure provided by the present invention, isolation sidewalls (i.e., first and second isolation sidewalls) with successively lower bottoms are provided on the sides of the gate structure, and the bottom of the contact plug is made lower and extends into the substrate. Accordingly, the metal silicide layer at the bottom of the contact plug is disposed in a deeper region of the substrate, effectively increasing the distance between the metal silicide layer and the gate structure. This can effectively alleviate the problem of metal diffusion into the gate structure that occurs during the preparation of the metal silicide layer and after the formation of the metal silicide layer. This is conducive to improving the device performance of the formed semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a schematic diagram of an existing semiconductor structure;

[0020] Figure 2a is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;

[0021] Figure 2b A schematic diagram of the structure of a semiconductor structure according to an embodiment of the present invention mainly illustrates a substrate;

[0022] Figure 3 is a schematic diagram of another semiconductor structure in one embodiment of the present invention;

[0023] Figure 4 is a schematic flow chart of a method for forming a semiconductor structure in one embodiment of the present invention;

[0024] Figure 5a to Figure 5j FIG. 1 is a structural diagram of a method for forming a semiconductor structure during its preparation process according to an embodiment of the present invention.

[0025] The accompanying drawings are numerals as follows:

[0026] 10 / 100-substrate;

[0027] 100a-first surface;

[0028] 100b-second surface;

[0029] 110-step part;

[0030] 110a-first step;

[0031] 110b-Second step;

[0032] 110c-third step;

[0033] 110d-the fourth step;

[0034] 20 / 200-gate structure;

[0035] 210-gate oxide layer;

[0036] 220-first gate conductive layer;

[0037] 230 - second gate conductive layer;

[0038] 240-third gate conductive layer;

[0039] 250-gate shielding layer;

[0040] 30 / 300-source and drain regions;

[0041] 310 - first doped region;

[0042] 320-second doping region;

[0043] 40 / 400-metal silicide layer;

[0044] 50 / 500-contact plug;

[0045] 500a-contact window;

[0046] 510-first conductive layer;

[0047] 520- second conductive layer;

[0048] 610-Fourth isolation side wall;

[0049] 620-first isolation side wall;

[0050] 630-second isolation side wall;

[0051] 640-third isolation side wall;

[0052] 700-Dielectric layer. DETAILED DESCRIPTION

[0053] The semiconductor structure and method for forming the same proposed by the present invention are further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the accompanying drawings are greatly simplified and not to exact scale, and are intended solely to facilitate and clearly illustrate the embodiments of the present invention.

[0054] Figure 2a is a schematic diagram of a semiconductor structure in one embodiment of the present invention, Figure 2b FIG. 1 is a schematic diagram of a semiconductor structure in an embodiment of the present invention, which mainly illustrates the structure of a substrate.

[0055] Combine Figure 2a and Figure 2bAs shown, the semiconductor structure in this embodiment includes: a substrate 100; a gate structure 200 formed on the top surface of the substrate 100; and source and drain regions 300 formed in the substrate 100. Specifically, the source and drain regions 300 are located on the sides of the gate structure 200, and the source and drain regions 300 can generally be electrically connected using contact plugs.

[0056] That is, the semiconductor structure further includes a contact plug 500 . The contact plug 500 is formed on a side of the gate structure 200 , and the bottom of the contact plug 500 extends to the substrate 100 to electrically connect to the source and drain regions 300 .

[0057] Continue to refer Figure 2a As shown, the semiconductor structure further includes a metal silicide layer 400. The metal silicide layer 400 is formed on the contact surface of the source / drain region 300 and extends into the source / drain region 300. The bottom of the contact plug 500 extends to the metal silicide layer 400, so that the contact plug 500 is in contact with the metal silicide layer 400. That is, the metal silicide layer 400 is formed between the source / drain region 300 and the contact plug 500, so that the source / drain region 300 and the contact plug 500 can be electrically connected through the metal silicide layer 400, which is beneficial to reducing the contact resistance between the source / drain region 300 and the contact plug 500.

[0058] Key References Figure 2b As shown, at least a portion of the substrate 100 located on the side of the gate structure 200 is successively recessed in a step-like manner in a direction away from the gate structure 200 to form a step portion 110. In this embodiment, the step portion 110 is adjacent to the gate structure 200 and extends in a direction away from the gate structure 200.

[0059] In a specific embodiment, the stepped portion 110 includes, for example, N steps, where N is a positive integer greater than or equal to 2. Furthermore, the N steps are mesas with N different mesa heights, and the mesa heights of the N steps decrease sequentially as they move away from the gate structure 200. For example, the N steps include a first step, a second step, ..., and an Nth step sequentially extending in a direction away from the gate structure 200, wherein the first step has the highest mesa height and the Nth step has the lowest mesa height.

[0060] It should be noted that the top surface of the substrate located on the side of the step portion 110 away from the gate structure 200 (i.e., the second surface 100b) may be lower than the top surface of the substrate directly below the gate structure (i.e., the first surface 100a); alternatively, the top surface of the substrate located on the side of the step portion 110 away from the gate structure 200 (i.e., the second surface 100b) may also be flush with the top surface of the substrate directly below the gate structure (i.e., the first surface 100a). For example, in this embodiment, the top surface of the substrate located on the side of the step portion 110 away from the gate structure 200 (i.e., the second surface 100b) is lower than the top surface of the substrate directly below the gate structure (i.e., the first surface 100a) and higher than the lowest terrace of the step portion 110.

[0061] Furthermore, the source / drain region 300 has a portion corresponding to the step portion 110. Specifically, the source / drain region 300 is formed on the side of the gate structure 200 and extends in a direction away from the gate structure 200, so that the source / drain region 300 extends to at least the position of the lowest terrace of the step portion 110. The top surface of the source / drain region 300 corresponding to the step portion 100 decreases in a gradient in a direction away from the gate structure 200, that is, at least a portion of the top surface of the source / drain region 300 conforms to the terrace of the step portion 110 in a stepped shape. In this embodiment, the source / drain region 300 further extends laterally to the position of the second surface 100b.

[0062] Continue to combine Figure 2a and Figure 2b As shown, the metal silicide layer 400 is formed on the surface of the source / drain region 300 located at the lowest step and extends into the source / drain region 300. That is, the metal silicide layer 400 is formed on the mesa of the N-step step farthest from the gate structure 200 (for example, the metal silicide layer 400 is formed on the mesa of the N-th step of the N-step step).

[0063] It should be noted that when preparing the metal silicide layer 400, it is usually formed by reacting a metal with silicon in the substrate 100. During this process, the metal diffuses in the substrate 100, thereby forming a metal silicide layer 400 having a certain thickness. Therefore, when the formed metal silicide layer is close to the gate structure, metal diffusion to the gate structure is likely to occur during the preparation of the metal silicide layer or after the metal silicide layer is formed, thereby affecting device performance, such as causing leakage current in the device and poor contact.

[0064] For example, reference Figure 1As shown, in the existing semiconductor structure, the metal silicide layer 40 is close to the gate structure 20, especially the top position of the metal silicide layer 40 and the bottom position of the gate structure 20 are both located at the same height position (that is, the top of the metal silicide layer 20 extends to the top surface of the substrate 10, and the bottom of the gate structure 20 is formed on the top surface of the substrate 10), so the metal in the metal silicide layer 40 can easily diffuse laterally to the gate structure 20 during laterally diffusion.

[0065] However, in this embodiment, specific reference is made to Figure 2a and Figure 2b As shown, because the substrate 100 on the side of the gate structure 200 has a stepped portion 110, the top surface of the source / drain region 300 correspondingly has a stepped portion, and the metal silicide layer 400 is further formed on the mesa of the source / drain region 300 located on the lowest step, the metal silicide layer 400 is accordingly recessed into a deeper position of the substrate 100, thereby causing the top position of the metal silicide layer 400 to be lower than the bottom position of the gate structure 200. In this case, the metal silicide layer 400 is located obliquely below the gate structure 200, which is equivalent to increasing the distance between the metal silicide layer 400 and the gate structure 200. When metal diffusion occurs, it is difficult for metal particles to cross the N-level steps and thus difficult to diffuse into the gate structure 200. Therefore, the problem of metal diffusion into the gate structure 200 that occurs during and after the preparation of the metal silicide layer 400 is effectively improved.

[0066] Continue to refer Figure 2a and Figure 2b As shown, in this embodiment, the step portion 110 is explained by taking the example of having four steps. Specifically, the step portion 110 includes a first step 110a, a second step 110b, a third step 110c, and a fourth step 110d, which are arranged in sequence along a direction away from the gate structure. The mesa of the second step 110b is lower than the mesa of the first step 110a, the mesa of the third step 110c is lower than the mesa of the second step 110b, and the mesa of the fourth step 110d is lower than the mesa of the third step 110c. In other words, the mesa of the first step 110a is the highest, and the mesa of the fourth step 110d is the lowest.

[0067] In this embodiment, the surface of the first step 110 a is lower than the first surface 100 a , and the second surface 100 b and the surface of the third step 110 c are flush.

[0068] Furthermore, the source / drain region 300 extends laterally from the gate structure 300 at least to the fourth step 110 d . Based on this, the metal silicide layer 400 is formed on the surface of the fourth step 110 d .

[0069] It should be noted that, in this embodiment, the mesa of the first step of the N steps (for example, the first step 110a in this embodiment) is lower than the top surface of the substrate directly below the gate structure (i.e., the first surface 100a), and the mesas of the second to N steps are successively lower, that is, among the N steps of this embodiment, the mesa height of the first step with the highest mesa is still lower than the bottom position of the gate structure 200. However, it should be appreciated that in other embodiments, the mesa of the first step of the N steps may also be flush with the top surface of the substrate directly below the gate structure (i.e., the first surface 100a).

[0070] Continue to refer Figure 2a As shown, the semiconductor structure further includes at least two layers of isolation spacers, which sequentially cover the sidewalls of the gate structure 200. Furthermore, at least a portion of the at least two isolation spacers is located on different mesas of the step portion 110. For example, of the at least two layers of isolation spacers, a portion is formed on the mesa of the first step, a portion is formed on the mesa of the second step, and so on. It should be appreciated that one or more layers of isolation spacers may be formed on the mesa of each step.

[0071] Furthermore, the at least two layers of isolation spacers include at least N-1 layers of isolation spacers, and the at least N-1 layers of isolation spacers are respectively located on the mesas of the 1st step to the N-1th step of the stepped portion 110. That is, among the N steps of the stepped portion 110, isolation spacers are formed on the mesas of the 1st step to the N-1th step, and the metal silicide layer 400 is formed on the mesas of the Nth step, and electrical contact is achieved between the contact plug 500 and the metal silicide layer 400 on the mesas of the Nth step.

[0072] In this embodiment, the table width of some steps can be defined by using the isolation sidewalls, which will be described in detail in the subsequent step portion formation method. Based on this, the isolation sidewalls on some steps can be aligned with the sidewalls away from the gate structure and the boundaries of the steps below them. For example, the at least two layers of isolation sidewalls can include at least N-1 layers of isolation sidewalls, and the 1st isolation layer to the N-2nd isolation sidewalls in the N-1 layers of isolation sidewalls are formed one-to-one on the table of the 1st step to the N-2nd step of the step portion 110, and the sidewalls of the 1st isolation layer to the N-2nd isolation sidewall are aligned one-to-one with the boundaries of the 1st step to the N-2nd step.

[0073] That is, in this embodiment, the at least two layers of isolation spacers are not only used to cover the gate structure 200 to isolate and protect the gate structure, but also used to define the step width and position of the step portion 110, further defining the formation position of the metal silicide layer 400. Based on this, it is equivalent to using the at least two layers of isolation spacers to effectively control the formation position of the metal silicide layer 400. For example, by increasing the number of isolation spacers, the number of steps of the step portion 110 can be increased, so that the metal silicide layer 400 can be formed deeper in the substrate 100.

[0074] Specifically, in this embodiment, the stepped portion 110 includes a first step 110a, a second step 110b, a third step 110c, and a fourth step 110d, and the at least two isolation spacers include a fourth isolation spacer 610 and a first isolation spacer 620. The fourth isolation spacer 610 covers the sidewalls of the gate structure 200, and the first isolation spacer 620 covers the sidewalls of the fourth isolation spacer 610 away from the gate structure 200. Furthermore, the fourth isolation spacer 610 is located on the mesa of the first step 110a, and the sidewalls of the fourth isolation spacer 610 away from the gate structure 200 are aligned with the boundary of the first step 110a. The first isolation spacer 620 is formed on the mesa of the second step 110b, and the sidewalls of the first isolation spacer 620 away from the gate structure 200 are aligned with the boundary of the second step 110b. In this case, the bottom of the first isolation spacer 620 is correspondingly lower than the bottom of the fourth isolation spacer 610.

[0075] It can be considered that in this embodiment, the fourth isolation spacer 610 is used to define the mesa width of the first step 110a (that is, the fourth isolation spacer 610 is used to define the boundary of the first step 110a away from the gate structure), and the first isolation spacer 620 is used to define the mesa width of the second step 110b (that is, the first isolation spacer 620 is used to define the boundary of the second step 110b away from the gate structure). At this time, it is equivalent to using the first isolation spacer 620 to define the boundary of the third step 110c close to the gate structure.

[0076] Furthermore, in this embodiment, the fourth step 110d can be defined using a patterning process. For example, during the process of forming a contact window to form the contact plug 500, the substrate 100 can be directly etched so that the etched substrate surface is sunken relative to the terrace of the third step 110c, thereby forming the fourth step 110d. It can be considered that the fourth step 110d is formed by etching a portion of the terrace of the third step 110c.

[0077] It should be noted that, in this embodiment, the first step (i.e., the first step 110a) is sunken relative to the first surface 100a of the substrate 100, and the boundary of the first step close to the gate structure 200 is aligned with the sidewall of the gate structure 200. It can be considered that the boundary of the first step 110a close to the gate structure is defined by the gate structure 200.

[0078] Continue to refer Figure 2a and Figure 2b As shown, the at least two layers of isolation spacers further include a second isolation spacer 630. The second isolation spacer 630 covers the sidewall of the first isolation spacer 620 away from the gate structure 200, and the second isolation spacer 630 is located on the terrace of the third step 110c. In this case, the bottom position of the second isolation spacer 630 is correspondingly lower than the bottom position of the first isolation spacer 620.

[0079] In this embodiment, the bottom of the second isolation spacer 630 further extends laterally in a direction away from the gate structure to cover the substrate surface on the side of the gate structure (i.e., the second surface 100b on the side of the step portion 11). Specifically, the source and drain regions 300 extend laterally to a position corresponding to the second surface 100b, and the second isolation spacer 630 also covers the second surface 100b, thereby enabling the second isolation spacer 630 to cover the source and drain regions 300.

[0080] Furthermore, the at least two layers of isolation spacers also include a third isolation spacer 640, which is formed on the second isolation spacer 630 and covers at least the sidewalls of the second isolation spacer 630. In this embodiment, both the third isolation spacer 640 and the second isolation spacer 630 are formed on the third step 110c, and the bottom of the third isolation spacer 640 also extends laterally away from the gate structure to cover the second surface 100b on the side of the step portion 110. In this case, the laterally extended bottom of the third isolation spacer 640 correspondingly covers the laterally extended bottom of the second isolation spacer 630.

[0081] Continue to refer Figure 2a and Figure 2b As shown, the source and drain region 300 includes a first doping region 310 and a second doping region 320, the doping concentration of the first doping region 310 is lower than the doping concentration of the second doping region 320, and the first doping region 310 is closer to the gate structure 200 and extends to the bottom of the gate structure 200, and the second doping region 320 is connected to the first doping region 310 and extends in a direction away from the gate structure 200.

[0082] In this embodiment, the first doped region 310, for example, extends laterally from below the gate structure 200 to below the first isolation spacer 620 (i.e., the first doped region 310 extends from below the gate structure 200 via the first step 110a to the second step 110b). The second doped region 320, for example, extends laterally from the second step 110b to the fourth step 110d and may further extend to the second surface 100b. In this case, the highest top position of the second doped region 320 is correspondingly lower than the highest top position of the first doped region 310.

[0083] In a specific embodiment, the semiconductor structure further includes a dielectric layer 700, which at least covers the outer side of the gate structure 200 and covers the substrate 100 on the side of the gate structure. In this embodiment, the dielectric layer 700 covers the outer sidewalls of the at least two isolation spacers.

[0084] Furthermore, the contact plug 500 penetrates the dielectric layer 700 to extend to the substrate 100 and is electrically connected to the source / drain region 300. In this embodiment, the dielectric layer 700 covers the sidewalls of the third isolation spacer 640, and the contact plug 500 is formed in the dielectric layer 700 near the third isolation spacer 640, with a portion of the sidewall of the contact plug 500 adjacent to the sidewall of the third isolation spacer 640.

[0085] It is understood that the at least two layers of isolation spacers can be used to isolate the contact plug 500 from the word line 200, and the outermost isolation spacer of the at least two layers of isolation spacers (for example, the third isolation spacer 640 in this embodiment) can also be used as a boundary barrier to control the formation position of the contact plug 500, so that the contact plug 500 can be controlled to be on the side of the outermost isolation spacer away from the gate structure (for example, so that part of the sidewall of the contact plug 500 is adjacent to the sidewall of the outermost isolation spacer). By controlling the formation position of the contact plug 500, the isolation performance between the contact plug 500 and the word line 200 can be guaranteed, and the coupling performance between the contact plug 500 and the word line 200 can be effectively improved based on the isolation of the multiple layers of isolation spacers, thereby reducing parasitic capacitance.

[0086] In a further embodiment, the at least two isolation spacers may be formed of at least two materials. For example, a portion of the isolation spacers may be formed of silicon oxide, while another portion may be formed of silicon nitride. In this embodiment, the fourth isolation spacer 610 may be formed of silicon nitride, the first isolation spacer 620 may be formed of silicon oxide, the second isolation spacer 630 may also be formed of silicon oxide, and the third isolation spacer 640 may be formed of silicon nitride.

[0087] Furthermore, the material of the outermost isolation spacer of the at least two isolation spacers can be different from the material of the dielectric layer 700. Thus, when etching the dielectric layer 700 to form the contact plug 500, the outermost isolation spacer can be used to provide a side etching barrier. Specifically, in this embodiment, the material of the third isolation spacer 640 is different from the material of the dielectric layer 700. For example, the material of the third isolation spacer 640 includes silicon nitride, while the material of the dielectric layer 700 includes silicon oxide.

[0088] It should be noted that in an optional solution, when etching to form the contact window, the outermost isolation sidewall is used to achieve etching barrier, in which case only a small amount of the outermost isolation sidewall is consumed, thereby making the contact plug filled in the contact window at least have its top sidewall adjacent to the outermost isolation sidewall. Figure 2a As shown, the top sidewall of the contact plug 500 is adjacent to the sidewall of the outermost isolation spacer (ie, the third isolation spacer 640 ).

[0089] Of course, in other solutions, the sidewalls of the contact plug can also be made to contact the sidewalls of the outermost isolation spacer and the sidewalls of the inner isolation spacer, that is, a portion of the sidewalls of the contact plug contacts the sidewalls of the second isolation spacer 630, and another portion of the sidewalls of the contact plug contacts the sidewalls of the third isolation spacer 640. Specifically, when etching to form the contact window, more of the outermost isolation spacer can be consumed, for example, the top of the outermost isolation spacer is consumed, and the bottom of the outermost isolation spacer is retained, so that the top sidewall of the contact plug filled in the contact window can be adjacent to the inner isolation spacer, and the bottom sidewall of the contact plug can be adjacent to the outermost isolation spacer. For example, refer to Figure 3 As shown, the top of the contact plug 500 extends laterally to the second isolation spacer 630 , so that the top sidewall of the contact plug 500 contacts the sidewall of the second isolation spacer 630 , and the bottom sidewall of the contact plug 500 contacts the sidewall of the third isolation spacer 640 .

[0090] also, Figure 3 In the scheme shown, when etching to form a contact window for accommodating the contact plug 500, part of the third isolation sidewall 640 is etched away to expose the second isolation sidewall 630, wherein the part located at the top corner and the bottom part of the third isolation sidewall 640 are retained while still covering the second isolation sidewall 630, so that the third isolation sidewall 640 discontinuously covers the second isolation sidewall 630.

[0091] As described above, in this embodiment, the fourth step 110d can be formed by etching a portion of the mesa of the third step 110c when forming the contact window of the contact plug 500. Specifically, before forming the contact window, the second isolation spacer 630 and the third isolation spacer 640 can be extended to cover the mesa of the third step 110c. Then, when forming the contact window, the dielectric layer 700, the second isolation spacer 630, and the third isolation spacer 640 are sequentially etched, and the mesa of the third step 110c is further etched to form a recessed fourth step 110d.

[0092] It is understood that by forming one or more isolation spacers on the third step 110c, the formation position of the contact plug 500 can be adjusted, and the position of the fourth step 110d and the position of the metal silicide layer 400 can be adjusted accordingly. For example, the center of the fourth step 110d can be aligned with the center of the second doped region 320, thereby allowing the metal silicide layer 400 and the contact plug 500 to be formed at the center of the second doped region 320.

[0093] Continue to refer Figure 2a As shown, in this embodiment, the terrace of the recessed fourth step 110d is an arc-shaped surface, and the metal silicide layer 400 is formed on the arc-shaped surface and further extends inward. In addition, the contact plug 500 sequentially penetrates the dielectric layer 700, the third isolation spacer 640, and the second isolation spacer 630 to extend to the metal silicide layer 400, thereby directly contacting the metal silicide layer 400.

[0094] Furthermore, the top width of the contact plug 500 is greater than the bottom width of the contact plug 500 , and the lateral width of the metal silicide layer 400 is greater than the bottom width of the contact plug 500 and smaller than the top width of the contact plug 500 .

[0095] Continue to refer Figure 2a As shown, the contact plug 500 includes a first conductive layer 510 and a second conductive layer 520. The first conductive layer 510 covers the bottom wall and sidewalls of the contact window, that is, correspondingly covers the metal silicide layer 400; and the second conductive layer 520 is formed on the first conductive layer 510 and fills the contact window.

[0096] It should be noted that in Figure 2a In the embodiment shown, only one gate structure 200 is shown, thereby forming a transistor device. However, in other embodiments (e.g., referring to Figure 3As shown), gate structures 200 may be formed on both sides of the same source / drain region 300 to form two transistor devices respectively, and the two transistor devices formed share the source / drain region 300. Figure 3 In the semiconductor structure shown, the shared source and drain regions 300 are symmetrically arranged with respect to the second doped region 320 , and two symmetrical step portions 110 are correspondingly provided between the two gate structures 200 .

[0097] That is, in Figure 3 In the illustrated embodiment, the semiconductor structure includes at least two gate structures 200, wherein two adjacent gate structures 200 share a contact plug 500. The first isolation spacer 620, the second isolation spacer 630, and the third isolation spacer 640 are disposed between the contact plug 500 and the two gate structures 200 on either side. Furthermore, the spacer structures on both sides of the contact plug 500 are symmetrically disposed.

[0098] In addition, Figure 3 In the illustrated embodiment, the spacing between the two third isolation spacers 640 on either side of the contact plug 500 can be less than or equal to the width of the contact plug 500, thereby allowing the sidewalls of the contact plug 500 to contact the sidewalls of the two third isolation spacers 640 on either side. In other words, the contact plug 500 is sandwiched between the isolation structures on either side. In a specific embodiment, the contact plug 500 has a structure that is wide at the top and narrow at the bottom. In this case, the top sidewall of the contact plug 500 further abuts the sidewalls of the two second isolation spacers 630 on either side, and the bottom sidewall of the contact plug 500 abuts the sidewalls of the two third isolation spacers 640 on either side.

[0099] Based on the semiconductor structure described above, a method for forming the semiconductor structure is described in detail below. Figure 4 FIG. 1 is a flow chart of a method for forming a semiconductor structure according to an embodiment of the present invention. Figure 5a to Figure 5j 1 is a schematic diagram of a method for forming a semiconductor structure in an embodiment of the present invention during its preparation process. The following describes in detail the various steps of forming the semiconductor structure in this embodiment in conjunction with the accompanying drawings.

[0100] In step S100, refer to Figure 5a As shown, a substrate 100 is provided, and a gate structure 200 is formed on the substrate 100 .

[0101] The gate structure 200 may include a gate oxide layer 210, a first gate conductive layer 220, a second gate conductive layer 230, a third gate conductive layer 240, and a gate shielding layer 250 stacked sequentially from bottom to top. Specifically, the material of the first gate conductive layer 220 includes, for example, polysilicon, the material of the second gate conductive layer 230 includes, for example, titanium nitride or titanium, the material of the third gate conductive layer 240 may include tungsten, and the material of the gate shielding layer 250 includes, for example, silicon nitride.

[0102] In step S200, refer to Figure 5b to Figure 5e As shown, source and drain regions 300 are formed on the side of the gate structure 200, and the substrate 100 is etched in sequence so that the portion of the substrate 100 located on the side of the gate structure 200 is successively recessed in a step-like manner in a direction away from the gate structure 200 to form a step portion 110, wherein the top surface of the source and drain regions 300 corresponding to the step portion 110 is gradually lowered in a direction away from the gate structure 200.

[0103] Part of the step in the stepped portion 110 may be defined by at least two layers of isolation spacers. For example, the stepped portion 110 may be formed by forming at least two layers of isolation spacers, and then etching the substrate 100 using the at least two layers of isolation spacers as a mask to gradually lower the top surface of the substrate 100.

[0104] In an alternative solution, at least N-2 layers of isolation spacers can be formed to define the first to N-2 steps of the N-step stepped portion 110 (in this case, the at least N-2 layers of isolation spacers are respectively located on the terraces of the first to N-2 steps of the stepped portion 110). The N-2 layer of isolation spacers is then used as a mask to etch the N-2 step to sink a portion of the substrate, thereby forming the N-1 step with a lower terrace. Alternatively, the N-step can be formed by etching the N-1 step during the fabrication of the contact plug.

[0105] In this embodiment, the formation of a stepped portion 110 having four steps is used as an example for explanation. Furthermore, the source / drain region 300 can be formed during the process of forming the isolation spacer and the stepped portion 110. Specifically, the method for forming the source / drain region 300 and the stepped portion 110 of the substrate 100 includes the following steps.

[0106] First step, specific reference Figure 5bAs shown, using the gate structure 200 as a mask, the substrate 100 on the side of the gate structure 200 is etched to cause the substrate surface located on the side of the gate structure 200 to sink, thereby forming the first step 110a of the stepped portion 110. At this time, the terrace of the first step 110a is correspondingly lower than the first surface 100a directly below the gate structure.

[0107] The second step, specific reference Figure 5c As shown, a fourth isolation spacer 610 is formed. The fourth isolation spacer 610 covers at least the sidewalls of the gate structure 200, and the bottom of the fourth isolation spacer 610 is located on the first step 110a. In this embodiment, the top of the fourth isolation spacer 610 further extends laterally to cover the top surface of the gate structure 200.

[0108] Step 3: Continue to refer to Figure 5c As shown, a first doped region 310 is formed in the substrate 100 and located on the side of the fourth isolation spacer 610 , and the first doped region 310 is further diffused to the bottom of the gate structure 200 through the fourth isolation spacer 610 .

[0109] Furthermore, the first doping region 310 is formed by, for example, an ion implantation process and a thermal annealing process, so that the implanted ions can diffuse through the fourth isolation spacer 610 to the bottom of the gate structure 200 .

[0110] Step 4, specific reference Figure 5d As shown, the fourth isolation spacer 610 is used as a mask to etch the substrate 100 on the side of the fourth isolation spacer 610, so that the substrate surface on the side of the fourth isolation spacer 610 is sunken to form the second step 110b of the stepped portion 110. At this time, the terrace of the second step 110b is correspondingly lower than the terrace of the first step 110a.

[0111] It should be appreciated that the step widths of the individual steps can be adjusted by adjusting the thickness of the isolation spacers. For example, the thickness of the fourth isolation spacer 610 can be adjusted to adjust the mesa width of the first step 110 a, thereby correspondingly adjusting the position of the second step 110 b near the boundary of the gate structure 200.

[0112] In addition, the order of the third step of forming the first doped region 310 and the fourth step of etching the substrate to form the second step 110b can be adjusted. For example, in other embodiments, the substrate can be etched first to form the second step, and then the ion implantation process can be performed to form the first doped region.

[0113] Step 5, specific reference Figure 5eAs shown, a first isolation spacer 620 is formed, the first isolation spacer 620 covers the sidewall of the fourth isolation spacer 610 , and the bottom of the first isolation spacer 620 is located on the second step 110 b .

[0114] In subsequent processes, the substrate 100 is further etched using the first isolation sidewall 620 as a mask to further form a third step. Similarly, by adjusting the width of the first isolation sidewall 620 , the mesa width of the second step 110 b can be adjusted accordingly.

[0115] Step 6, specific reference Figure 5f As shown, the first isolation spacer 620 is used as a mask to etch the substrate 100 on the side of the first isolation spacer 620, so that the substrate surface on the side of the first isolation spacer 620 is sunken to form the third step 110c of the stepped portion 110. At this time, the terrace of the third step 110c is correspondingly lower than the terrace of the second step 110b.

[0116] Furthermore, a second doping region 320 is formed in the substrate 100 and located on a side of the first isolation spacer 620, and the second doping region 320 is connected to the first doping region 310 below the first isolation spacer 620. The doping concentration of the second doping region 320 is higher than the doping concentration of the first doping region 310, and the second doping region 320 is diffused deeper into the substrate than the first doping region 310.

[0117] Similarly, the order of forming the second doped region 320 and etching the substrate to form the third step 110c can be adjusted. For example, in other embodiments, an ion implantation process can be performed first to form the second doped region 320, and then the substrate can be etched to form the third step 110c.

[0118] For further reference, Figure 5g As shown, after forming the third step 110c, the method further includes sequentially forming a second isolation spacer 630 and a third isolation spacer 640 on the third step 110c. Furthermore, the isolation material layer used to form the second isolation spacer 630 and the third isolation spacer 640 further extends to cover the mesa of the third step 110c, so that the isolation material layer further covers the surface of the second doped region 320.

[0119] Continue to refer Figure 5gAs shown, the method for forming the semiconductor structure further includes: forming a dielectric layer 700 on the substrate 100, wherein the dielectric layer 700 covers the periphery of the isolation spacer and covers the source / drain region 300. The material of the dielectric layer 700 may be different from the material of the outermost isolation spacer. That is, in this embodiment, the material of the dielectric layer 700 is different from the material of the third isolation spacer 640. For example, the material of the dielectric layer 700 includes silicon oxide, and the material of the third isolation spacer 640 includes silicon nitride.

[0120] It should be noted that, in this embodiment, in the process of forming the step portion 110 of the N-step step, the 1st step to the N-2nd step can be defined by the isolation sidewall. For example, the method of forming the 1st step to the N-2nd step includes: sequentially forming N-2 layers of isolation sidewalls, and etching the substrate after forming each isolation sidewall so that the surface of the substrate is sequentially sunken to form the 1st step to the N-2nd step, at which time the N-2 layers of isolation sidewalls are respectively located on the terraces of the 1st step to the N-2nd step. Furthermore, the method of forming the N-1st step can be: etching the N-2nd step using the N-2th layer of isolation sidewalls as a mask so that part of the substrate is sunken to form the N-1st step. Furthermore, the Nth step can be formed by etching the N-1st step during the process of preparing the contact plug.

[0121] Specifically, refer to Figure 5h As shown, the dielectric layer 700 and the isolation material layer are sequentially etched to the substrate 100 to expose the N-1 step of the substrate, and a portion of the table of the N-1 step is further etched to sink the table to form a contact window 500a. The bottom surface of the contact window 500a is lower than the table of the N-1 step and constitutes the Nth step of the step portion, that is, the table of the Nth step is lower than the table of the N-1 step.

[0122] In this embodiment, the bottom surface of the contact window 500 a corresponds to the fourth step 110 d , and the contact window 500 a exposes the second doping region 320 .

[0123] As described above, the material of the dielectric layer 700 is different from the material of the third isolation spacer 640. Therefore, when etching the dielectric layer 700 to form the contact window 500a, the third isolation spacer 640 can be used to provide a side etching barrier, effectively controlling the position of the formed contact window 500a. Based on this, for example, a portion of the third isolation spacer 640 is exposed on the sidewalls of the formed contact window 500a.

[0124] In an alternative solution, the number of isolation sidewall layers on the third step 110c can be adjusted to further adjust the position of the outermost isolation sidewall, thereby correspondingly adjusting the position of the formed contact window 500a. In this embodiment, the contact window 500a is located at or near the center of the second doped region 320.

[0125] In step S300, refer to Figure 5i As shown, a metal silicide layer 400 is formed on the surface of the source / drain region 300 located at the lowest step, and the metal silicide layer 400 also extends into the source / drain region 300. In this embodiment, the metal silicide layer 400 is formed on the surface of the second doped region 320, and the boundary of the metal silicide layer 400 extending laterally in the direction of the gate structure in the second doped region 320 does not exceed the boundary of the second isolation spacer 630 close to the gate structure. That is, in this embodiment, the boundary of the metal silicide layer 400 close to the gate structure does not exceed the boundary of the second isolation spacer 630 close to the gate structure. In addition, the top of the edge of the metal silicide layer 400 also contacts the bottom surface of the second isolation spacer 630.

[0126] Specifically, the method for forming the metal silicide layer 400 includes, for example, first forming a metal layer, the metal layer covering at least the bottom surface of the contact window 500 a to cover the second doped region 320 exposed in the contact window 500 a; then performing an annealing process to react the metal in the metal layer with the silicon in the second doped region 320 to form the metal silicide layer 400; and then removing the unreacted metal layer. The material of the metal silicide layer 400 includes, for example, cobalt silicide.

[0127] It should be noted that in the process of preparing the metal silicide layer 400, since the surface of the second doped region 320 exposed in the contact window sinks relative to the gate structure 200, there is a larger distance between the surface of the second doped region 320 and the gate structure 200, which can effectively improve the problem of metal diffusion into the gate structure.

[0128] In step S400, refer to Figure 5j As shown, a contact plug 500 is formed on the side of the gate structure 200, and the bottom of the contact plug 500 extends to the metal silicide layer 400. Specifically, the contact plug 500 is filled in the contact window 500a.

[0129] In summary, in the semiconductor structure described above, by making the substrate on the side of the gate structure present a stepped shape with a stepped portion, the top surface of the source and drain regions is adjusted to a stepped shape accordingly, thereby enabling the metal silicide layer to be formed on the mesa of the source and drain regions located on the lowest step. Accordingly, the metal silicide layer is recessed into a deeper position in the substrate and located obliquely below the gate structure, which is equivalent to increasing the distance between the metal silicide layer and the gate structure. In this way, when metal diffusion occurs, it is difficult for metal particles to cross the N steps and thus difficult to diffuse into the gate structure. Therefore, the problem of metal diffusion into the gate structure that occurs during the preparation process of the metal silicide layer and after the preparation of the metal silicide layer is completed is effectively improved.

[0130] It should be noted that although the present invention has been disclosed above with reference to preferred embodiments, the above embodiments are not intended to limit the present invention. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or to modify it into an equivalent embodiment with equivalent changes. Therefore, any simple modification, equivalent change, and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still fall within the scope of protection of the technical solution of the present invention.

[0131] It should also be understood that, unless otherwise specified or indicated, the terms "first", "second", "third", etc. in the specification are only used to distinguish the various components, elements, steps, etc. in the specification, and are not used to indicate the logical relationship or sequential relationship between the various components, elements, steps, etc.

[0132] It should also be understood that the terms described herein are intended to describe particular embodiments only and are not intended to limit the scope of the invention. It should be noted that the singular forms "a" and "an" as used herein and in the appended claims include plural references unless the context clearly indicates otherwise. For example, a reference to "a step" or "a device" means a reference to one or more steps or devices, and may include secondary steps as well as secondary devices. All conjunctions used should be understood in their broadest sense. Also, the word "or" should be understood to have the definition of a logical "or" rather than a logical "exclusive or" unless the context clearly indicates otherwise. Furthermore, implementation of the methods and / or apparatus in embodiments of the present invention may include performing selected tasks manually, automatically, or in combination.

Claims

1. A semiconductor structure, characterized in that include: substrate; at least one gate structure formed on the substrate; a first isolation spacer, located on the surface of the substrate, covering the sidewall of the gate structure, and having a bottom lower than the bottom of the gate structure; a second isolation spacer covering a sidewall of the first isolation spacer away from the gate structure, wherein a bottom of the second isolation spacer is lower than a bottom of the first isolation spacer; a third isolation spacer covering a sidewall of the second isolation spacer away from the gate structure, wherein a bottom of the third isolation spacer is lower than a bottom of the first isolation spacer; a contact plug formed on a side of the third isolation spacer away from the gate structure, wherein a bottom of the contact plug is lower than a bottom of the second isolation spacer and extends into the substrate; as well as, A metal silicide layer is located in the substrate at the bottom of the contact plug and directly contacts the contact plug and the substrate. The metal silicide layer falls between the first isolation spacer and the third isolation spacer near the boundary of the gate structure.

2. The semiconductor structure according to claim 1, wherein The bottom of the second isolation spacer further extends laterally in a direction away from the gate structure to cover the surface of the substrate, and the contact plug penetrates the second isolation spacer to extend into the substrate.

3. The semiconductor structure according to claim 2, wherein: A top portion of an edge of the metal silicide layer contacts a bottom surface of the second isolation spacer.

4. The semiconductor structure according to claim 2, wherein: The boundary of the metal silicide layer close to the gate structure does not exceed the boundary of the second isolation sidewall close to the gate structure.

5. The semiconductor structure according to claim 2, wherein: The bottom of the third isolation spacer further extends laterally in a direction away from the gate structure to cover the second isolation spacer, and the contact plug sequentially penetrates the third isolation spacer and the second isolation spacer to extend into the substrate.

6. The semiconductor structure according to claim 1, wherein The third isolation spacer does not continuously cover the second isolation spacer.

7. The semiconductor structure according to claim 1, wherein: A portion of the sidewall of the contact plug contacts the sidewall of the second isolation spacer, and another portion of the sidewall of the contact plug contacts the sidewall of the third isolation spacer.

8. The semiconductor structure according to claim 7, wherein: The top width of the contact plug is greater than the bottom width of the contact plug, wherein the top sidewall of the contact plug contacts the sidewall of the second isolation spacer, and the bottom sidewall of the contact plug contacts the sidewall of the third isolation spacer.

9. The semiconductor structure according to claim 1, wherein: It also includes a fourth isolation sidewall, which is located at least between the sidewall of the gate structure and the first isolation sidewall, wherein the bottom of the fourth isolation sidewall is lower than the bottom of the gate structure and higher than the bottom of the first isolation sidewall.

10. The semiconductor structure according to claim 9, wherein: The fourth isolation spacer also covers the top surface of the gate structure.

11. The semiconductor structure according to claim 1, wherein: The semiconductor structure includes at least two gate structures, wherein two adjacent gate structures share a contact plug, and the first isolation spacer, the second isolation spacer and the third isolation spacer are arranged between the contact plug and the two gate structures on both sides.

12. The semiconductor structure according to claim 11, wherein The distance between the two third isolation spacers on both sides of the contact plug is less than or equal to the width of the contact plug, and the sidewall of the contact plug contacts the sidewalls of the two third isolation spacers on both sides.

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