Array substrate and display panel

Abstract

The application discloses an array substrate and a display panel. The array substrate comprises a hole region and a plurality of wirings. The plurality of wirings are arranged around at least part of the circumference of the hole region. The plurality of wirings comprise a plurality of kinds of wirings for transmitting different signals. At least part of the wirings are free ends near the end of the hole region. The free ends of at least two wirings for transmitting the same signal in the wirings are connected to each other. The array substrate provided by the application reduces the number of free ends in the array substrate by connecting the free ends of at least two wirings for transmitting the same signal to each other, thereby realizing electrostatic protection of at least part of the wirings. After reducing the number of free ends in the array substrate, the amount of charges attracted by the free ends in the array substrate can be reduced, thereby reducing the influence of the release of the charges attracted by the free ends on the performance of the devices in the array substrate, improving the reliability of the devices in the array substrate, and thus improving the quality of the product and reducing the occurrence of display defects.

Description

Technical Field

[0001] This application belongs to the field of display technology, and in particular relates to an array substrate and a display panel. Background Technology

[0002] In existing display panels, there are usually holes formed in the display area. These holes can be blind holes or through holes. The light transmittance of the holes is higher, so that a photosensitive module can be integrated on the side of the display panel away from the light-emitting surface and in the area opposite to the holes. However, in existing display panels, display defects are prone to occur near the holes, such as bright lines, dark lines, and bright spots. Summary of the Invention

[0003] This application provides an array substrate and a display panel, wherein the devices in the array substrate have higher reliability, thereby improving product quality.

[0004] An embodiment of the first aspect of this application provides an array substrate, comprising:

[0005] Hole area;

[0006] Multiple traces are arranged circumferentially around at least a portion of the aperture area, and the multiple traces include various traces for transmitting different signals;

[0007] Wherein, at least a portion of the traces are free ends near the hole area;

[0008] At least two of the multiple traces used to transmit the same signal have their free ends connected to each other.

[0009] According to an embodiment of the first aspect of this application, the free ends of the trace used to transmit the same signal include a first free end and a second free end located on both sides of the hole area;

[0010] Wherein, at least some of the first free ends are electrically connected to each other, and / or, at least some of the second free ends are electrically connected to each other, and / or, at least some of the first free ends are electrically connected to at least some of the second free ends.

[0011] According to any of the foregoing embodiments of the first aspect of this application, the array substrate further includes a connection portion for connecting the free ends of at least two traces used to transmit the same signal.

[0012] According to any of the foregoing embodiments of the first aspect of this application, the array substrate includes multiple metal layers and an insulating layer located between adjacent metal layers, wherein the multiple metal layers include a first metal layer, a second metal layer and a third metal layer stacked together.

[0013] According to any of the foregoing embodiments of the first aspect of this application, at least two traces for transmitting the same signal are located in the same metal layer, and the connection portion is disposed in the same layer as the at least two traces for transmitting the same signal.

[0014] Alternatively, at least two traces used to transmit the same signal are located on different metal layers, and the connection is connected to the two traces located on different layers respectively through the insulating layer located between the different metal layers.

[0015] According to any of the foregoing embodiments of the first aspect of this application, the plurality of traces includes a first signal trace for transmitting the same signal and a second signal trace for transmitting the same signal; the connection portion includes a first connection portion for connecting to the free ends of at least two first signal traces and a second connection portion for connecting to the free ends of at least two second signal traces, wherein the first connection portion and the second connection portion are mutually insulated.

[0016] According to any of the foregoing embodiments of the first aspect of this application, the plurality of traces further includes a third signal trace for transmitting the same signal, and the connection portion includes a third connection portion for connecting to the free ends of at least two third signal traces, wherein the third connection portion is insulated from the first connection portion and the second connection portion.

[0017] According to any of the foregoing embodiments of the first aspect of this application, at least two of the first signal trace, the second signal trace, and the third signal trace are located in the same metal layer; or, the first signal trace, the second signal trace, and the third signal trace are all located in different metal layers.

[0018] According to any of the foregoing embodiments of the first aspect of this application, when the first signal trace, the second signal trace, and the third signal trace are all located in the first metal layer...

[0019] The first signal trace, the second signal trace, and the third signal trace correspond to the first scan signal line, the second scan signal line, and the light emission control signal line, respectively.

[0020] The second aspect of this application also provides a display panel, including any of the array substrates provided in the first aspect of this application.

[0021] The array substrate provided in this application includes a hole region and multiple traces arranged at least partially along the circumference of the hole region. Some traces have free ends near the hole region. Free ends easily attract and release charge. By connecting the free ends of at least two traces used to transmit the same signal to each other, the number of exposed free ends in the array substrate is reduced, thereby achieving electrostatic discharge protection for at least some of the traces. Reducing the number of free ends in the array substrate decreases the amount of charge attracted by the free ends, thus reducing the impact on the performance of devices in the array substrate when the free ends release the attracted charge, improving the reliability of devices in the array substrate, thereby enhancing product quality and reducing the occurrence of display defects. Attached Figure Description

[0022] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a schematic diagram of the structure of a display panel in the prior art;

[0024] Figure 2 This is a schematic diagram of the structure of an array substrate provided in an embodiment of this application;

[0025] Figure 3 yes Figure 2 An enlarged schematic diagram of region A in the image;

[0026] Figure 4 This is a partial structural diagram of the area around the hole region of another array substrate provided in this application embodiment;

[0027] Figure 5 This is a cross-sectional view of an array substrate provided in an embodiment of this application.

[0028] Figure 6 This is a partial structural diagram of the area around the hole region of another array substrate provided in this application embodiment;

[0029] Figure 7 The array substrate provided in the embodiments of this application Figure 8 This is a schematic diagram of another wiring structure of the array substrate provided in the embodiments of this application;

[0030] Figure 8 This is a schematic diagram of another wiring structure of the array substrate provided in the embodiments of this application;

[0031] Figure 9This is a schematic diagram of another wiring structure of the array substrate provided in the embodiments of this application;

[0032] Figure 10 This is a schematic diagram of another wiring structure of the array substrate provided in the embodiments of this application;

[0033] Figure 11 This is a schematic diagram of another wiring structure of the array substrate provided in the embodiments of this application;

[0034] Figure 12 This is a schematic diagram of another wiring structure of the array substrate provided in the embodiments of this application;

[0035] Figure 13 This is a schematic diagram of another wiring structure of the array substrate provided in the embodiments of this application;

[0036] A schematic diagram of a wiring structure;

[0037] Figure 14 This is a schematic diagram of another wiring structure of the array substrate provided in the embodiments of this application;

[0038] Figure 15 This is a schematic diagram of another wiring structure of the array substrate provided in the embodiments of this application;

[0039] Figure 16 This is a partial structural diagram of the area around the hole region of another array substrate provided in an embodiment of this application;

[0040] Figure 17 This is a partial structural diagram of the area around the hole region of another array substrate provided in an embodiment of this application;

[0041] Figure 18 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application.

[0042] In the attached image:

[0043] 1-Display panel; 10-Array substrate; 11-Substrate; 12-Trace; 121-Free end; 122-First free end; 123-Second free end; 124-First signal trace; 125-Second signal trace; 126-Third signal trace; 13-Connection portion; 131-First connection portion; 132-Second connection portion; 133-Third connection portion; 14-First metal layer; 141-Gate; 142-First electrode plate; 15-First insulating layer; 16-Second metal layer; 161-Second electrode plate; 17-Second insulating layer; 18-Third metal layer; 181-Source / drain; 19-Active layer; 20-Third insulating layer; 21-Planarization layer; 22-Buffer layer. Detailed Implementation

[0044] The features and exemplary embodiments of various aspects of this application will now be described in detail. Numerous specific details are set forth in the following detailed description in order to provide a comprehensive understanding of this application. However, it will be apparent to those skilled in the art that this application can be implemented without some of these specific details. The following description of embodiments is merely intended to provide a better understanding of this application by illustrating examples thereof.

[0045] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0046] like Figure 1 As shown, the display panel 1' includes an aperture region HL'. Display defects, such as bright lines, dark lines, and bright spots, are prone to occur near the aperture region HL'. The inventors discovered that the reason for display defects near the aperture region HL' is that the array substrate 10' includes various traces 11' and transistor devices. Specifically, some traces 11' are divided into two parts by the aperture region HL', causing the end of the separated trace 11' closest to the aperture region HL' to be exposed and prone to charge accumulation. When this charge accumulates and is released, it can break down the transistor, resulting in display defects. Based on the research on the above problems, the inventors provide an array substrate and a display panel.

[0047] To better understand this application, the following will be combined with... Figures 2 to 18 The array substrate and display panel according to embodiments of this application will be described in detail.

[0048] Please see Figure 2 This application provides an array substrate 10, including an aperture region HL and multiple traces 12. The multiple traces 12 are arranged around at least a portion of the aperture region HL in a circumferential direction c. The multiple traces 12 include various traces 12 used to transmit different signals. At least a portion of the traces 12 have free ends 121 near the aperture region HL. The free ends 121 of at least two traces 12 used to transmit the same signal are interconnected.

[0049] The array substrate 10 provided in this application includes an aperture region HL and multiple traces 12 arranged at least partially along the circumferential direction c of the aperture region HL. The ends of some traces 12 near the aperture region HL are free ends 121. These free ends 121 are exposed and easily attract and release charge. By connecting the free ends 121 of at least two traces 12 used to transmit the same signal to each other, the number of free ends 121 in the array substrate 10 is reduced, thereby achieving electrostatic discharge protection for at least some of the traces 12. Reducing the number of free ends 121 in the array substrate 10 reduces the amount of charge attracted by the free ends 121, thus reducing the impact on the performance of devices in the array substrate 10 when the free ends 121 attract and release charge, improving the reliability of devices in the array substrate 10, thereby improving product quality and reducing the occurrence of display defects.

[0050] In the array substrate 10 provided in this application, when the free ends 121 of each type of trace 12 are interconnected, the number of sharp points in the array substrate 10 that are prone to attracting charge can be further reduced, thereby further improving the electrostatic protection effect of the trace 12 and further reducing the impact of static electricity in the free ends 121 of the trace 12 on the performance of the devices in the array substrate 10, so that the devices can achieve good performance.

[0051] In the above-described embodiments, such as Figure 2 and Figure 3 As shown, the free end 121 of the trace 12 used to transmit the same signal includes a first free end 122 and a second free end 123 located on both sides of the hole area.

[0052] Specifically, a trace 12 extending along the first direction x can be separated by an aperture region to form two traces 12. Two free ends 121 are formed at the separated locations, located on both sides of the aperture region, namely the first free end 122 and the second free end 123. After the trace 12 is separated by the aperture region, the influence of the trace 12 on the transmittance of the aperture region HL can be reduced, thereby improving the light transmittance of the aperture region HL. This facilitates the integration of the photosensitive module under the array substrate 10 and enables the photosensitive module to achieve good results. The photosensitive module can be a fingerprint recognition module or a camera, etc., and this application does not make any special limitations.

[0053] Specifically, in the array substrate 10 provided in this application, the hole region HL can be a through hole or a blind hole, and this application does not make any special limitation.

[0054] In the above embodiments, such as Figure 3 As shown, among the multiple traces 12 used to transmit the same signal, at least a portion of the first free ends 122 are electrically connected to each other, and / or at least a portion of the second free ends 123 are electrically connected to each other, and / or at least a portion of the first free ends 122 are electrically connected to at least a portion of the second free ends 123.

[0055] When at least some of the first free ends 122 of multiple traces 12 used to transmit the same signal are electrically connected, and / or at least some of the second free ends 123 are electrically connected, the multiple first free ends 122 connected to each other are located on the same side of the hole area, so they are close to each other and easy to connect; and / or the multiple second free ends 123 connected to each other are located on the same side of the hole area, so they are close to each other and easy to connect.

[0056] like Figure 4 As shown, among the multiple traces 12 used to transmit the same signal, some of the first free ends 122 can be electrically connected to each other, some of the second free ends 123 can be electrically connected to each other, and some of the first free ends 122 and the second free ends 123 can be electrically connected. The connection can be made according to the actual wiring situation, and this application does not make any special limitations.

[0057] In one feasible implementation, the array substrate 10 further includes a connection portion 13 for connecting the free ends 121 of at least two traces 12 used to transmit the same signal.

[0058] When at least some of the first free ends 122 of the same type of trace are electrically connected, and / or at least some of the second free ends 123 are electrically connected, the length of the connection portion 13 can be saved, thereby simplifying the wiring in the array substrate 10.

[0059] In one feasible implementation, such as Figure 5 As shown, the array substrate 10 includes multiple metal layers and insulating layers located between adjacent metal layers. The multiple metal layers include a first metal layer 14, a second metal layer 16, and a third metal layer 18 stacked together. The insulating layer between the first metal layer 14 and the second metal layer 16 is a first insulating layer 15, and the insulating layer between the second metal layer 16 and the third metal layer 18 is a second insulating layer 17.

[0060] The array substrate 10 also includes a substrate 11, an active layer 19 formed between the substrate 11 and the first metal layer 14, and a third insulating layer 20, wherein the active layer 19 and the third insulating layer 20 are arranged sequentially in a direction away from the substrate 11.

[0061] Specifically, a buffer layer 22 is formed between the substrate 11 and the active layer 19. The buffer layer 22 can be made of organic or inorganic materials, or a combination of organic and inorganic material layers, to serve as a buffer.

[0062] Specifically, the array substrate 10 includes devices such as transistors and capacitors. The transistors include an active layer 19, a gate 141, and a source / drain electrode 181. The capacitors include a first electrode 142 and a second electrode 161. The active layer 19 can be made of polysilicon or metal oxide, etc. The gate 141 and the first electrode 142 of the capacitor are formed on a first metal layer 14, the second electrode 161 is formed on a second metal layer 16, and the source / drain electrode 181 is formed on a third metal layer 18. The first metal layer 14 and the second metal layer 16 are both made of metals such as molybdenum; the third metal layer 18 includes a first titanium layer, an aluminum layer, and a second titanium layer; or, the third metal layer 18 includes a molybdenum metal layer.

[0063] Specifically, the array substrate 10 also includes a planarization layer 21 located on the side of the third metal layer 18 facing away from the substrate 11. The surface of the planarization layer 21 facing away from the substrate 11 is planar to facilitate the preparation of subsequent film layers.

[0064] In one feasible implementation, such as Figure 6 As shown, at least two traces 12 used to transmit the same signal are located in the same metal layer, and the connection portion 13 is disposed in the same layer as the at least two traces 12 used to transmit the same signal. This allows the connection portion 13 and the traces 12 to be fabricated in the same layer, which facilitates the connection between the connection portion 13 and the traces 12 connected to the connection portion 13, simplifies the fabrication process, and ensures a stable connection effect.

[0065] When at least two traces 12 used to transmit the same signal are located in the same metal layer, specifically:

[0066] like Figure 7 As shown, at least two traces 12 (taking two first signal traces 124 as an example) used to transmit the same signal are located in the first metal layer 14. The connecting portion 13 that connects the traces 12 can be located in the first metal layer 14 and directly connected to the free end of each trace 12; or, as shown... Figure 8 As shown, the connecting portion 13 that connects the aforementioned traces 12 can be located in the second metal layer 16, and the connecting portion 13 penetrates the first insulating layer 15 and connects to each trace 12; or, as shown... Figure 9 As shown, the connecting part 13 that connects the above-mentioned traces 12 can be located in the third metal layer 18. The connecting part 13 passes through the first insulating layer 15 and the second insulating layer 17 to connect with each trace 12.

[0067] At least two traces 12 used to transmit the same signal are located on the second metal layer 16, such as Figure 10 As shown, the connecting portion 13 that connects the aforementioned traces 12 can be located in the second metal layer 16 and directly connected to each trace 12; or, as shown... Figure 11As shown, the connecting portion 13 that connects the above-mentioned traces 12 can be located in the third metal layer 18, and the connecting portion 13 penetrates the second insulating layer 17 to connect with each trace 12.

[0068] At least two traces 12 used to transmit the same signal are located on the third metal layer 18, such as Figure 12 As shown, the connecting part 13 that connects the above-mentioned traces 12 can be located in the third metal layer 18 and directly connected to each trace 12.

[0069] In another feasible implementation, at least two traces 12 for transmitting the same signal are located in different metal layers, and the connection portion 13 is connected to the two traces 12 located in different layers respectively through an insulating layer that passes through the different metal layers.

[0070] In the above embodiments, such as Figure 13 As shown, when a portion of the same type of trace 12 is located in the first metal layer 14 and a portion is located in the second metal layer 16, the connecting portion 13 penetrates the first insulating layer 15 to connect with the trace 12 located in the first metal layer 14 and the second metal layer 16.

[0071] like Figure 14 As shown, when part of the same type of trace 12 is located in the second metal layer 16 and part is located in the third metal layer 18, the connecting part 13 penetrates the second insulating layer 17 to connect with the trace 12 located in the second metal layer 16 and the third metal layer 18.

[0072] like Figure 15 As shown, when a portion of the same type of trace 12 is located in the first metal layer 14 and a portion is located in the third metal layer 18, the connecting portion 13 penetrates the first insulating layer 15 and the second insulating layer 17 to connect with the trace 12 located in the first metal layer 14 and the third metal layer 18.

[0073] In one feasible implementation, such as Figure 16 As shown, the multiple traces 12 include a first signal trace 124 for transmitting the same signal and a second signal trace 125 for transmitting the same signal; the connection portion 13 includes a first connection portion 131 for connecting to the free ends 121 of at least two first signal traces 124, and a second connection portion 132 for connecting to the free ends 121 of at least two second signal traces 125, wherein the first connection portion 131 and the second connection portion 132 are insulated from each other.

[0074] In the above embodiment, the first signal trace 124 and the second signal trace 125 are different types of traces 12. The free ends 121 of the multiple first signal traces 124 are connected by a first connecting portion 131, and the free ends 121 of the multiple second signal traces 125 are connected by a second connecting portion 132. The first connecting portion 131 and the second connecting portion 132 are insulated from each other to avoid mutual interference between the first signal traces 124 and the second signal traces 125, thereby ensuring the accuracy of signal transmission and ensuring the performance of the array substrate 10.

[0075] In one feasible implementation, such as Figure 17 As shown, the multiple traces 12 also include a third signal trace 126 for transmitting the same signal, and the connection portion 13 includes a third connection portion 133 for connecting to the free ends 121 of at least two third signal traces 126. The third connection portion 133 is insulated from the first connection portion 131 and the second connection portion 132.

[0076] In the above embodiment, the third signal trace 126 is a different type of trace 12 from the first signal trace 124 and the second signal trace 125. The free ends 121 of the multiple third signal traces 126 are connected by a third connection portion 133. The third connection portion 133 is insulated from the first connection portion 131 and the second connection portion 132 to avoid mutual interference between the third signal trace 126 and the first signal trace 124 and the second signal trace 125, thereby ensuring the accuracy of signal transmission and the performance of the array substrate 10.

[0077] In one feasible implementation, at least two of the first signal trace 124, the second signal trace 125, and the third signal trace 126 are located in the same metal layer; or, the first signal trace 124, the second signal trace 125, and the third signal trace 126 are all located in different metal layers.

[0078] When two of the first signal trace 124, the second signal trace 125, and the third signal trace 126 are located on the same metal layer, and the third signal trace is located on another metal layer, specifically:

[0079] When the first signal trace 124 and the second signal trace 125 are located on the same metal layer, the first connection portion 131 and the second connection portion 132 are located on different layers to achieve mutual insulation between the first connection portion 131 and the second connection portion 132.

[0080] When the first signal trace 124 and the third signal trace 126 are located on the same metal layer, the first connection portion 131 and the third connection portion 133 are located on different layers to achieve mutual insulation between the first connection portion 131 and the third connection portion 133.

[0081] When the second signal trace 125 and the third signal trace 126 are located on the same metal layer, the second connection portion 132 and the third connection portion 133 are located on different layers to achieve mutual insulation between the second connection portion 132 and the third connection portion 133.

[0082] Specifically, when the first signal trace 124 and the second signal trace 125 are located in the first metal layer 14, the first connection portion 131 can be located in the first metal layer 14, and the second connection portion 132 can be located in the second metal layer 16. The second connection portion 132 penetrates the first insulating layer 15 to connect with the free end 121 of the second signal trace 125. At this time, the third signal trace 126 can be located in the second metal layer 16 or the third metal layer 18, and the third connection portion 133 is located in the third metal layer 18. When the third signal trace 126 is located in the second metal layer 16, the third connection portion 133 penetrates the second insulating layer 17 to connect with the free end 121 of the third signal trace 126; when the third signal trace 126 is located in the third metal layer 18, the third connection portion 133 and the free end 121 of the third signal trace 126 are fabricated and connected in the same layer, which can save fabrication process.

[0083] When the first signal trace 124 and the second signal trace 125 are located in the second metal layer 16, the first connection portion 131 can be located in the second metal layer 16, and the second connection portion 132 can be located in the third metal layer 18. The second connection portion 132 penetrates the second insulating layer 17 to connect with the free end 121 of the second signal trace 125. At this time, the third signal trace 126 can be located in the first metal layer 14, and the third connection portion 133 is located in the first metal layer 14. The third connection portion 133 and the free end 121 of the third signal trace 126 are fabricated and connected in the same layer, which can save fabrication process.

[0084] When the second signal trace 125 and the third signal trace 126 are located on the same metal layer, or when the second signal trace 125 and the third signal trace 126 are located on the same metal layer, the arrangement of the connection portion 13 is similar to the arrangement of the connection portion 13 when the first signal trace 124 and the second signal trace 125 are located on the same metal layer, and will not be described again in this application.

[0085] When the first signal trace 124, the second signal trace 125, and the third signal trace 126 are all located in the same metal layer, specifically, when the first signal trace 124, the second signal trace 125, and the third signal trace 126 are all located in the first metal layer 14, the first connection portion 131, the second connection portion 132, and the third connection portion 133 can be respectively disposed in the first metal layer 14, the second metal layer 16, and the third metal layer 18 to achieve mutual insulation between the first connection portion 131, the second connection portion 132, and the third connection portion 133.

[0086] Specifically, different first signal traces 124 include a first free end 122 or a second free end 123, and different second signal traces 125 include a first free end 122 or a second free end 123. When at least a portion of the first free ends 122 of the first signal traces 124 are connected through a first connecting portion 131, at least a portion of the second free ends 123 of the first signal traces 124 are connected through a first connecting portion 131, and at least a portion of the first free ends 122 of the second signal traces 125 are connected through a second connecting portion 132... When at least a portion of the second free ends 123 of the second signal trace 125 are connected via the second connecting portion 132, the first connecting portion 131 connecting the first free end 122 of the first signal trace 124 and the second connecting portion 132 connecting the second free end 123 of the second signal trace 125 can be disposed on the same layer, or the first connecting portion 131 connecting the second free end 123 of the first signal trace 124 and the second connecting portion 132 connecting the first free end 122 of the second signal trace 125 can be disposed on the same layer. When the first signal trace 124 and the second signal trace 125 are located in the first metal layer 14 and the second metal layer 16, respectively, the first connecting portion 131 connecting the first free end 122 of the first signal trace 124 and the second connecting portion 132 connecting the second free end 123 of the second signal trace 125 can be disposed in the same layer, and the first connecting portion 131 connecting the second free end 123 of the first signal trace 124 and the second connecting portion 132 connecting the first free end 122 of the second signal trace 125 can be disposed in the same layer. The first connecting portions 131 and the second connecting portions 132 located in the same layer can be insulated from each other by not making contact.

[0087] The above-described embodiments provide more options for wiring in the pixel circuit layer, and this application does not specifically limit the specific wiring method.

[0088] In one feasible implementation, when the first signal line 124, the second signal line 125, and the third signal line 126 are all located in the first metal layer 14, the first signal line 124, the second signal line 125, and the third signal line 126 correspond to the first scan signal line, the second scan signal line, and the light emission control signal line, respectively. Since the first signal line 124, the second signal line 125, and the third signal line 126 are located in the same layer as the gate 141, the charge accumulated at the tips can easily have a serious impact on the characteristics of the transistor. By connecting the free ends 121 of at least two traces 12 used to transmit the same signal to each other, the number of free ends 121 in the first signal trace 124, the second signal trace 125, and the third signal trace 126 can be reduced. This reduces the amount of charge attracted by the free ends 121 in the array substrate 10 and weakens the attraction of the first metal layer 14 to the charge, thus achieving electrostatic protection. This reduces the impact of the free ends 121 on the performance of the devices in the array substrate 10 when the charge is released, improves the reliability of the devices in the array substrate 10, thereby improving product quality and reducing the occurrence of display defects.

[0089] This application also provides a display panel 1, such as Figure 18 As shown, including any of the array substrates 10 provided in the above embodiments of this application, since the number of sharp points in the pixel circuit layer that are easy to attract charges is reduced in the array substrate 10, the electrical characteristics of the array substrate 10 are more stable and the reliability is stronger, which can effectively reduce the occurrence of display defects in the display panel 1 and improve the display quality of the display panel 1.

[0090] The embodiments described above are not exhaustive and do not limit the invention to specific examples. Clearly, many modifications and variations can be made based on the above description. These embodiments are selected and specifically described in this specification to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to effectively utilize this application and its modifications. This application is limited only by the claims and their full scope and equivalents.

Claims

1. An array substrate, characterized in that, include: Hole area; Multiple traces are arranged circumferentially around at least a portion of the aperture area, and the multiple traces include various traces for transmitting different signals; Wherein, at least a portion of the traces are free ends near the hole area; The free ends of at least two of the multiple traces used to transmit the same signal are connected to each other. The plurality of traces extend along a first direction, and the free ends of the traces used to transmit the same signal include a first free end and a second free end located on both sides of the aperture area along the first direction; at least some of the first free ends are electrically connected to each other, and / or at least some of the second free ends are electrically connected to each other.

2. The array substrate according to claim 1, characterized in that, A portion of the first free end is electrically connected to a portion of the second free end.

3. The array substrate according to claim 1, characterized in that, It also includes a connector for connecting the free ends of at least two traces used to transmit the same signal.

4. The array substrate according to claim 3, characterized in that, The array substrate includes multiple metal layers and an insulating layer located between adjacent metal layers. The multiple metal layers include a first metal layer, a second metal layer, and a third metal layer stacked together.

5. The array substrate according to claim 4, characterized in that, At least two traces used to transmit the same signal are located in the same metal layer, and the connection portion is disposed in the same layer as the at least two traces used to transmit the same signal. Alternatively, at least two traces used to transmit the same signal are located on different metal layers, and the connection is connected to the two traces located on different layers respectively through the insulating layer located between the different metal layers.

6. The array substrate according to claim 4, characterized in that, The multiple traces include a first signal trace for transmitting the same signal and a second signal trace for transmitting the same signal; the connection includes a first connection for connecting to the free ends of at least two first signal traces and a second connection for connecting to the free ends of at least two second signal traces, wherein the first connection and the second connection are insulated from each other.

7. The array substrate according to claim 6, characterized in that, The multiple traces also include a third signal trace for transmitting the same signal, and the connection portion includes a third connection portion for connecting to the free ends of at least two third signal traces, wherein the third connection portion is insulated from the first connection portion and the second connection portion.

8. The array substrate according to claim 7, characterized in that, At least two of the first signal trace, the second signal trace, and the third signal trace are located in the same metal layer; or, the first signal trace, the second signal trace, and the third signal trace are all located in different metal layers.

9. The array substrate according to claim 8, characterized in that, When the first signal trace, the second signal trace, and the third signal trace are all located in the first metal layer. The first signal trace, the second signal trace, and the third signal trace correspond to the first scan signal line, the second scan signal line, and the light emission control signal line, respectively.

10. A display panel, characterized in that, Includes the array substrate as described in any one of claims 1-9.

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