Array substrate, display panel, and manufacturing method of array substrate

Abstract

The embodiments of the present application disclose an array substrate, a display panel, and a method for manufacturing the array substrate. The array substrate includes a base substrate and a thin film transistor layer, wherein the thin film transistor layer is disposed on the base substrate; the thin film transistor layer includes a first thin film transistor, wherein the first thin film transistor includes a first active layer, a first gate insulating layer, and a first source-drain electrode layer stacked on the base substrate, wherein the first gate insulating layer is located between the first active layer and the first source-drain electrode layer, and the first source-drain electrode layer includes a first source electrode and a first drain electrode electrically connected to the first active layer; the first thin film transistor also includes a first gate electrode, which is located on the first gate insulating layer and is disposed in the same layer as the first source-drain electrode layer. By disposing the first gate electrode in the same layer as the first source-drain electrode layer, the first gate electrode, the first source electrode, and the first drain electrode can be manufactured using the same photomask, thereby simplifying the manufacturing process of the array substrate, improving the production efficiency of the array substrate, and reducing the production cost.

Description

Technical Field

[0001] The present application relates to the field of display, and in particular to an array substrate, a display panel, and a method for manufacturing the array substrate. Background Art

[0002] With the development of display technology, display panels, featuring high image quality, power efficiency, thin design, and a wide range of applications, have gradually become the mainstream in display devices. Thin-film transistors (TFTs), the primary driving components in display panels, are directly related to the development direction of high-performance display panels.

[0003] Depending on the active layer material, thin-film transistors are classified into amorphous silicon (a-Si) TFTs, low-temperature polycrystalline silicon (LTPS) TFTs, and metal oxide (Metal Oxide) TFTs. Each type of thin-film transistor has its own unique advantages. Combining multiple types of thin-film transistors into a hybrid TFT structure can effectively improve the display quality of a display panel. However, in the prior art, the manufacturing process of array substrates with this hybrid thin-film transistor structure is relatively complex, resulting in low production efficiency and excessively high production costs. Summary of the Invention

[0004] The embodiments of the present application provide an array substrate, a display panel, and a method for manufacturing the array substrate, which can solve the problem of low production efficiency caused by the complex manufacturing process of the existing array substrate.

[0005] An embodiment of the present application provides an array substrate, comprising:

[0006] substrate;

[0007] A thin film transistor layer is arranged on the base substrate; the thin film transistor layer includes a first thin film transistor, the first thin film transistor includes a first active layer, a first gate insulating layer and a first source-drain electrode layer stacked on the base substrate, the first gate insulating layer is located between the first active layer and the first source-drain electrode layer, the first source-drain electrode layer includes a first source electrode and a first drain electrode electrically connected to the first active layer; the first thin film transistor also includes a first gate electrode, the first gate electrode is located on the first gate insulating layer, and the first gate electrode and the first source-drain electrode layer are arranged in the same layer.

[0008] Optionally, in some embodiments of the present application, there is a gap between the first gate and the first source and the first drain, and a first opening is formed on the first gate insulating layer at a position corresponding to the gap.

[0009] Optionally, in some embodiments of the present application, the array substrate includes a planar layer, which is disposed on the first source and drain layer and the first gate, and the planar layer fills the gap and the first opening.

[0010] Optionally, in some embodiments of the present application, the first thin film transistor further includes a second gate and an interlayer dielectric layer, the second gate is located on a side of the first active layer close to the substrate, and the interlayer dielectric layer is located between the first active layer and the second gate.

[0011] Optionally, in some embodiments of the present application, the array substrate includes a second thin film transistor, which is arranged in parallel with the first thin film transistor on the base substrate; the second thin film transistor includes a second active layer, the first gate insulation layer and a second source-drain layer stacked on the base substrate, the first gate insulation layer is located between the second active layer and the second source-drain layer, the second source-drain layer includes a second source and a second drain electrically connected to the second active layer; the second source-drain layer is arranged on the same layer as the first source-drain layer and the first gate.

[0012] Optionally, in some embodiments of the present application, a second opening is provided on the first gate insulating layer at a position corresponding to the first source electrode, the second opening leaks out of the second active layer, and the first source electrode is electrically connected to the second active layer through the second opening.

[0013] Optionally, in some embodiments of the present application, the second thin film transistor includes a third gate and a second gate insulating layer, the third gate is provided corresponding to the second active layer, and the second gate insulating layer is located between the third gate and the second active layer;

[0014] The third gate is located on a side of the second active layer away from the substrate; or,

[0015] The third gate is located on a side of the second active layer close to the base substrate.

[0016] Optionally, in some embodiments of the present application, the third gate and the second gate are provided in the same layer; or,

[0017] The third gate is provided in the same layer as the first source and drain layer.

[0018] Optionally, in some embodiments of the present application, the material of the first active layer includes one or more of indium gallium zinc oxide, indium tin oxide, or indium zinc oxide; and the material of the second active layer includes low-temperature polysilicon.

[0019] Correspondingly, an embodiment of the present application further provides a display panel, which includes any of the array substrates described above.

[0020] Accordingly, an embodiment of the present application further provides a method for manufacturing an array substrate, the method comprising:

[0021] providing a substrate;

[0022] forming a first active layer and a first gate insulating layer in sequence on the base substrate;

[0023] A first gate, a first source and a first drain are formed on the first gate insulating layer, so that the first source and the first drain are electrically connected to the first active layer; the first active layer, the first gate insulating layer, the first gate, the first source and the first drain form a first thin film transistor.

[0024] Optionally, in some embodiments of the present application, sequentially forming a first active layer and a first gate insulating layer on the base substrate includes:

[0025] forming a second active layer and a second gate insulating layer in sequence on the base substrate;

[0026] forming a second gate and a third gate on the second gate insulating layer, so that the third gate is disposed corresponding to the second active layer;

[0027] forming an interlayer dielectric layer on the second gate and the third gate;

[0028] forming a first active layer on the interlayer dielectric layer at a position corresponding to the second gate;

[0029] A first gate insulating layer is formed on the first active layer.

[0030] Optionally, in some embodiments of the present application, forming a first gate, a first source, and a first drain on the first gate insulating layer includes:

[0031] A first gate, a first source, a first drain, a second source and a second drain are formed on the first gate insulating layer, so that the first source and the first drain are electrically connected to the first active layer, and the first source, the second source and the second drain are electrically connected to the second active layer; the second active layer, the second gate insulating layer, the third gate, the first gate insulating layer, the first source and the first drain form a second thin film transistor.

[0032] In an embodiment of the present application, an array substrate includes a base substrate and a thin-film transistor layer. The thin-film transistor layer includes a first thin-film transistor. The first thin-film transistor includes a first active layer, a first gate insulating layer, a first source-drain electrode layer, and a first gate. The first source-drain electrode layer includes a first source electrode and a first drain electrode electrically connected to the first active layer. The first gate is disposed in the same layer as the first source-drain electrode layer. By disposing the first gate and the first source-drain electrode layer in the same layer, the first gate, the first source electrode, and the first drain electrode can be simultaneously fabricated using the same photomask during the manufacturing process, thereby simplifying the manufacturing process of the array substrate, improving the production efficiency of the array substrate, and reducing the production cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0034] Figure 1 This is a schematic structural diagram of an array substrate provided in an embodiment of the present application;

[0035] Figure 2 is a structural diagram of a display panel provided in an embodiment of the present application;

[0036] Figure 3 This is a flow chart of a method for manufacturing an array substrate provided in an embodiment of the present application;

[0037] Figure 4 This embodiment of the present application provides Figure 3 Flowchart of step S200;

[0038] Figure 5 This embodiment of the present application provides Figure 3 A schematic structural diagram of step S200;

[0039] Figure 6 This embodiment of the present application provides Figure 3 Schematic diagram of the structure of step S300.

[0040] Description of reference numerals:

[0041]

[0042] DETAILED DESCRIPTION

[0043] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise specified, the directional words used, such as "upper" and "lower", generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the accompanying drawings; and "inside" and "outside" refer to the outline of the device.

[0044] The embodiments of the present application provide an array substrate, a display panel, and a method for manufacturing the array substrate. Each of these is described in detail below. It should be noted that the order in which the following embodiments are described does not limit the preferred order of the embodiments.

[0045] First, the embodiment of the present application provides an array substrate, such as Figure 1 、 Figure 5 and Figure 6 As shown, the array substrate 100 includes a base substrate 110, which serves as a supporting structure in the array substrate 100 and is used to support other film structures on the array substrate 100 to maintain the relative stability of the array substrate 100. The base substrate 110 can be a glass substrate or a rigid substrate or a flexible substrate made of other materials, which is not limited here.

[0046] The array substrate 100 includes a thin film transistor layer 120, which is arranged on the base substrate 110. The thin film transistor layer 120 serves as a switch control structure on the array substrate 100, and is used to control other functional layer structures arranged on the array substrate 100 to meet different application requirements.

[0047] Among them, the thin film transistor layer 120 includes a first thin film transistor 121, and the first thin film transistor 121 includes a first active layer 1211, a first gate insulating layer 1212 and a first source and drain layer 1213 stacked on the base substrate 110, and the first gate insulating layer 1212 is located between the first active layer 1211 and the first source and drain layer 1213, and is used to separate the first active layer 1211 and the first source and drain layer 1213 to facilitate the design of the connection method between the first source and drain layer 1213 and the first active layer 1211.

[0048] It should be noted that the first active layer 1211, the first gate insulating layer 1212 and the first source-drain layer 1213 are arranged in sequence along the direction away from the base substrate 110, or the first source-drain layer 1213, the first gate insulating layer 1212 and the first active layer 1211 are arranged in sequence along the direction away from the base substrate 110, that is, the positions of the first active layer 1211 and the first source-drain layer 1213 relative to the base substrate 110 can be swapped, and the specific arrangement method can be adjusted accordingly according to actual design requirements.

[0049] Among them, the first source-drain layer 1213 includes a first source electrode 1213a and a first drain electrode 1213b electrically connected to the first active layer 1211. By electrically connecting the first source electrode 1213a and the first drain electrode 1213b to the first active layer 1211 and regulating the driving voltage on the first source electrode 1213a and the first drain electrode 1213b, the first active layer 1211 connected between the first source electrode 1213a and the first drain electrode 1213b can be turned on and off, thereby realizing control of other functional layer structures arranged on the array substrate 100.

[0050] Optionally, the first thin film transistor 121 also includes a first gate 1214, which is located on the first gate insulating layer 1212. The first gate 1214 serves as a switching structure of the first thin film transistor 121. By adjusting the driving voltage at the input end of the first gate 1214, the first thin film transistor 121 can be controlled to be turned on or off, thereby realizing the regulation of other functional structures by the first thin film transistor 121.

[0051] Among them, the first gate 1214 is arranged on the same layer as the first source-drain layer 1213, that is, the first gate 1214 and the first source-drain layer 1213 belong to the same metal layer, that is, the first gate 1214 is arranged on the same layer as the first source 1213a and the first drain 1213b. This structural setting method enables the first gate 1214 and the first source 1213a and the first drain 1213b in the first source-drain layer 1213 to be manufactured simultaneously using the same mask during the manufacturing process, thereby saving one mask, simplifying the process of the array substrate 100, improving the production efficiency of the array substrate 100, and reducing production costs.

[0052] In the embodiment of the present application, the array substrate 100 includes a base substrate 110 and a thin film transistor layer 120. The thin film transistor layer 120 includes a first thin film transistor 121. The first thin film transistor 121 includes a first active layer 1211, a first gate insulating layer 1212, a first source-drain electrode layer 1213, and a first gate electrode 1214. The first source-drain electrode layer 1213 includes a first source electrode 1213a and a first drain electrode 1213b electrically connected to the first active layer 1211. The first gate electrode 1214 is disposed in the same layer as the first source-drain electrode layer 1213. By disposing the first gate electrode 1214 in the same layer as the first source-drain electrode layer 1213, the first gate electrode 1214, the first source electrode 1213a, and the first drain electrode 1213b can be simultaneously formed using the same photomask during the manufacturing process, thereby simplifying the manufacturing process of the array substrate 100, improving the production efficiency of the array substrate 100, and reducing the production cost.

[0053] Optionally, there is a gap 1215 between the first gate 1214 and the first source 1213a and the first drain 1213b, that is, the first gate 1214 and the first source 1213a and the first drain 1213b are spaced apart to avoid mutual interference between the first gate 1214, the first source 1213a and the first drain 1213b, thereby affecting the normal conduction and disconnection of the first thin film transistor 121.

[0054] Among them, a first opening 1212a is opened on the first gate insulating layer 1212 at a position corresponding to the gap 1215 to ensure that the first gate 1214 is completely separated from the first source 1213a and the first drain 1213b, so as to avoid incomplete etching due to etching accuracy or etching depth during the manufacturing process of the array substrate 100, which may cause interference between the first gate 1214 and the first source 1213a and the first drain 1213b, thereby ensuring the structural stability of the first thin film transistor 121.

[0055] Optionally, the array substrate 100 includes a planarization layer 123, which is disposed on the first source / drain electrode layer 1213 and the first gate electrode 1214. The planarization layer 123 fills the gap 1215 between the first gate electrode 1214 and the first source electrode 1213a and the first drain electrode 1213b, as well as the first opening 1212a in the first gate insulation layer 1212. Providing the planarization layer 123 not only flattens the surface of the array substrate 100 to facilitate connection between the array substrate 100 and subsequent functional layer structures, but also improves electrical insulation between the first gate electrode 1214 and the first source electrode 1213a and the first drain electrode 1213b, thereby preventing mutual interference and improving the structural stability of the first thin-film transistor 121.

[0056] Optionally, the first thin film transistor 121 also includes a second gate 1216 and an interlayer dielectric layer 1217, the second gate 1216 is located on the side of the first active layer 1211 close to the base substrate 110, and the interlayer dielectric layer 1217 is located between the first active layer 1211 and the second gate 1216 to separate the second gate 1216 from the first active layer 1211, thereby avoiding direct contact between the second gate 1216 and the first active layer 1211, thereby affecting the control of the conduction and disconnection of the first thin film transistor 121.

[0057] Among them, a second gate 1216 is set on the side of the first active layer 1211 close to the base substrate 110, so that the second gate 1216 and the first gate 1214 form a double-gate structure. The second gate 1216 can play an effective electrostatic shielding role between the first gate and the first drain 1213b, thereby greatly reducing the feedback capacitance between the first gate 1214 and the first drain 1213b, thereby improving the carrier mobility of the first thin film transistor 121.

[0058] In addition, the second gate 1216 is arranged corresponding to the first active layer 1211. The second gate 1216 can also serve as a light-shielding metal layer 124 to block external ambient light, preventing external ambient light from irradiating the first active layer 1211 and affecting the structure of the first active layer 1211, thereby further improving the overall structural stability of the first thin film transistor 121.

[0059] It should be noted that the second gate 1216 can also be disposed on the side of the first active layer 1211 facing away from the base substrate 110, that is, the second gate 1216 and the first gate 1214 are located on the same side of the first active layer 1211. The second gate 1216 and the first gate 1214 can also form a dual-gate structure to improve the carrier mobility of the first thin-film transistor 121. In this case, to prevent external ambient light from affecting the structure of the first active layer 1211, a light-shielding metal layer 124 can be formed on the base substrate 110 at a position corresponding to the first active layer 1211 to ensure the overall structural stability of the first thin-film transistor 121.

[0060] Optionally, the array substrate 100 includes a second thin film transistor 122, which is arranged in parallel with the first thin film transistor 121 on the base substrate 110. By designing the coordination between the multiple thin film transistors, the diversity of the drive control of the array substrate 100 can be increased, thereby meeting the different control requirements of other functional layer structures arranged on the array substrate 100.

[0061] Among them, the second thin film transistor 122 includes a second active layer 1221, a first gate insulating layer 1212 and a second source-drain layer 1226 stacked on the base substrate 110, and the first gate insulating layer 1212 is located between the second active layer 1221 and the second source-drain layer 1226, and is used to separate the second active layer 1221 and the second source-drain layer 1226 to facilitate the design of the connection method between the second source-drain layer 1226 and the second active layer 1221.

[0062] It should be noted that the second active layer 1221, the first gate insulating layer 1212 and the second source-drain layer 1226 are arranged in sequence along the direction away from the base substrate 110, or the second source-drain layer 1226, the first gate insulating layer 1212 and the second active layer 1221 are arranged in sequence along the direction away from the base substrate 110, that is, the positions of the second active layer 1221 and the second source-drain layer 1226 relative to the base substrate 110 can be exchanged, and the specific arrangement method can be adjusted accordingly according to actual design requirements.

[0063] Among them, the second source-drain layer 1226 includes a second source 1226a and a second drain 1226b electrically connected to the second active layer 1221. By electrically connecting the second source 1226a and the second drain 1226b to the second active layer 1221 and regulating the driving voltage on the second source 1226a and the second drain 1226b, the second active layer 1221 connected between the second source 1226a and the second drain 1226b can be turned on and off, thereby realizing control of other functional layer structures arranged on the array substrate 100.

[0064] Optionally, the second source-drain electrode layer 1226 is provided in the same layer as the first source-drain electrode layer 1213 and the first gate electrode 1214. That is, the second source-drain electrode 1226, the first source-drain electrode 1213, and the first gate electrode 1214 are provided in the same layer. That is, the second source electrode 1226a, the second drain electrode 1226b, the first source electrode 1213a, the first drain electrode 1213b, and the first gate electrode 1214 are provided in the same layer. This structural arrangement allows the second source electrode 1226a, the second drain electrode 1226b, the first source electrode 1213a, the first drain electrode 1213b, and the first gate electrode 1214 to be simultaneously formed using the same photomask during the fabrication of the array substrate 100, thereby simplifying the fabrication process of the array substrate 100, improving production efficiency, and reducing production costs.

[0065] Optionally, a second opening 1212b is provided on the first gate insulating layer 1212 at a position corresponding to the first source electrode 1213a, the second opening 1212b leaks out of the second active layer 1221, and the first source electrode 1213a is electrically connected to the second active layer 1221 through the second opening 1212b; at the same time, a third opening 1212c is provided on the first gate insulating layer 1212 at a position corresponding to the first source electrode 1213a and the first drain electrode 1213b, and the first source electrode 1213a and the first drain electrode 1213b are electrically connected to the second active layer 1221 through the third opening. The hole 1212c is electrically connected to the first active layer 1211; a fourth opening 1212d is also provided on the first gate insulating layer 1212 at positions corresponding to the second source electrode 1226a and the second drain electrode 1226b, and the second source electrode 1226a and the second drain electrode 1226b are electrically connected to the second active layer 1221 through the fourth opening 1212d, thereby realizing electrical connection between the first thin film transistor 121 and the second thin film transistor 122, so as to facilitate the coordination and regulation of other functional layer structures arranged on the array substrate 100.

[0066] Optionally, the second thin film transistor 122 includes a third gate 1223 and a second gate insulating layer 1222, wherein the third gate 1223 is arranged corresponding to the second active layer 1221, and the second gate insulating layer 1222 is located between the third gate 1223 and the second active layer 1221 to separate the third gate 1223 from the second active layer 1221, thereby avoiding direct contact between the third gate 1223 and the second active layer 1221, thereby affecting the control of the conduction and disconnection of the second thin film transistor 122.

[0067] In some embodiments, the third gate 1223 is located on the side of the second active layer 1221 away from the base substrate 110. By regulating the driving voltage at the input end of the third gate 1223, the conduction or disconnection between the second source 1226a and the second drain 1226b can be regulated, thereby achieving control of the conduction or disconnection of the second thin film transistor 122.

[0068] Since the third gate 1223 is located on the side of the second active layer 1221 away from the base substrate 110, external ambient light may be irradiated to the second active layer 1221 through the base substrate 110, affecting the structure of the second active layer 1221. Therefore, it is necessary to set a light-shielding metal layer 124 on the side of the second active layer 1221 close to the base substrate 110 to prevent the second active layer 1221 from undergoing structural changes due to irradiation by external ambient light, thereby ensuring the structural stability of the second thin film transistor 122.

[0069] In other embodiments, the third gate 1223 is located on the side of the second active layer 1221 close to the base substrate 110. In this case, in addition to being able to regulate the conduction or disconnection between the second source 1226a and the second drain 1226b, the third gate 1223 can also serve as a light-shielding metal layer 124 to protect the second active layer 1221 and ensure the structural stability of the second thin film transistor 122.

[0070] Optionally, the third gate 1223 can be set on the same layer as the second gate 1216, that is, the third gate 1223 and the second gate 1216 belong to the same metal layer. This structural setting method enables the third gate 1223 and the second gate 1216 to be manufactured simultaneously using the same mask during the production process of the array substrate 100, thereby simplifying the process of the array substrate 100, improving production efficiency and reducing production costs.

[0071] In some embodiments, the third gate 1223 can also be set in the same layer as the first source and drain layer 1213, that is, the third gate 1223, the second source 1226a, the second drain 1226b, the first source 1213a, the first drain 1213b and the first gate 1214 all belong to the same metal layer, thereby further simplifying the process of the array substrate 100, improving production efficiency and reducing production costs.

[0072] Optionally, the second thin film transistor 122 also includes a fourth gate 1225 and a third gate insulating layer 1224, the third gate insulating layer 1224 is located between the third gate 1223 and the fourth gate 1225, the fourth gate 1225 is arranged corresponding to the second active layer 1221, and the setting of the fourth gate 1225 forms a dual-gate structure in the second thin film transistor 122, thereby improving the carrier mobility of the second thin film transistor 122.

[0073] When both the third gate 1223 and the fourth gate 1225 are located on the side of the second active layer 1221 facing away from the base substrate 110, a light-shielding metal layer 124 needs to be provided on the side of the second active layer 1221 close to the base substrate 110 to ensure the structural stability of the array substrate 100. When at least one of the third gate 1223 and the fourth gate 1225 is located on the side of the second active layer 1221 close to the base substrate 110, the gate can also serve as the light-shielding metal layer 124, thereby omitting the light-shielding metal layer 124 and simplifying the overall structure of the array substrate 100.

[0074] Optionally, in the embodiment of the present application, the material of the first active layer 1211 includes one or more of indium gallium zinc oxide, indium tin oxide or indium zinc oxide, and the material of the second active layer 1221 includes low-temperature polysilicon, that is, the first thin-film transistor 121 is a metal oxide (Metal Oxide) thin-film transistor, and the second thin-film transistor 122 is a low-temperature polysilicon (Low Temperature Poly-silicon, LTPS) thin-film transistor.

[0075] Among them, low-temperature polysilicon thin-film transistors have advantages such as high mobility, small size, fast charging, and fast switching speed, and are very effective when used for gate driving. Metal oxide thin-film transistors have the advantages of good uniformity and low leakage current, and can be used for display pixel driving. Therefore, by forming a hybrid thin-film transistor structure with low-temperature polysilicon thin-film transistors and metal oxide thin-film transistors, the drive current in the gate drive circuit of the display device can be increased, and the leakage current when driving the display pixels of the display device can be reduced, thereby improving the applicability of the array substrate 100.

[0076] Secondly, an embodiment of the present application also provides a display panel, which includes an array substrate. The specific structure of the array substrate refers to the above embodiment. Since this display panel adopts all the technical solutions of all the above embodiments, it at least has all the beneficial effects brought by the technical solutions of the above embodiments, which will not be repeated here one by one.

[0077] Figure 2 is a schematic structural diagram of a display panel provided in an embodiment of the present application, such as Figure 2 As shown, the display panel 10 includes an array substrate 100 , a light emitting device 200 and a packaging component 300 , wherein the light emitting device 200 is disposed on the array substrate 100 , and the packaging component 300 is disposed on the light emitting device 200 .

[0078] Among them, the light-emitting device 200 includes multiple light-emitting pixels, the array substrate 100 includes multiple first thin film transistors 121 and multiple second thin film transistors 122, and the light-emitting pixels are electrically connected to the corresponding first thin film transistors 121 and second thin film transistors 122. By designing the connection method between the light-emitting pixels and the first thin film transistors 121 and the second thin film transistors 122, and regulating the conduction or disconnection method of the first thin film transistors 121 and the second thin film transistors 122, the light-emitting mode of multiple light-emitting pixels can be controlled, thereby realizing different display requirements of the display panel 10 and improving the display effect of the display panel 10.

[0079] It should be noted that the display panel 10 in the embodiment of the present application has a very wide range of applications, including various display and lighting display devices such as televisions, computers, mobile phones, foldable and rollable display screens, as well as wearable devices such as smart bracelets and smart watches, all of which are within the scope of the application field of the display panel 10 in the embodiment of the present application.

[0080] Finally, the present invention also provides a method for manufacturing an array substrate. Figure 3 As shown, the method for manufacturing the array substrate includes the following steps:

[0081] S100: Provide a base substrate 110. The base substrate 110 serves as a support structure in the array substrate 100, used to support other film structures on the array substrate 100 to maintain the relative stability of the array substrate 100. The base substrate 110 can be a glass substrate or a rigid or flexible substrate made of other materials, without limitation.

[0082] S200 , sequentially forming a first active layer 1211 and a first gate insulating layer 1212 on the base substrate 110 .

[0083] like Figure 5 As shown, after the base substrate 110 is cleaned, a first active layer 1211 is first deposited on the base substrate 110 and etched according to design requirements to form a target pattern. The material used for the first active layer 1211 includes one or more of indium gallium zinc oxide, indium tin oxide, or indium zinc oxide, that is, the first active layer 1211 is a metal oxide semiconductor.

[0084] The thickness of the first active layer 1211 is greater than or equal to 400 angstroms and less than or equal to 1000 angstroms. If the thickness of the first active layer 1211 is too thin, the carrier mobility of the first active layer 1211 may be affected, thereby affecting the overall performance of the array substrate 100. If the thickness of the first active layer 1211 is too thick, the overall thickness of the array substrate 100 may be too large, which is not conducive to the structural design of the array substrate 100.

[0085] In the actual manufacturing process, the thickness of the first active layer 1211 is set to 400 angstroms, 600 angstroms, 800 angstroms or 1000 angstroms, etc. The specific thickness value can be adjusted accordingly according to actual design requirements and is not particularly limited here.

[0086] After forming the first active layer 1211, a first gate insulating layer 1212 needs to be formed on its surface. The first gate insulating layer 1212 covers the first active layer 1211 and the base substrate 110. On the one hand, the first gate insulating layer 1212 can separate the first active layer 1211, facilitating the design of the connection between subsequent film layers and the first active layer 1211; on the other hand, the first gate insulating layer 1212 can planarize the surface of the first active layer 1211, facilitating the efficient fabrication of subsequent film layers.

[0087] The material used for the first gate insulating layer 1212 includes one or more of silicon oxide, silicon nitride, or silicon oxynitride. The thickness of the first gate insulating layer 1212 is greater than or equal to 1000 angstroms and less than or equal to 5000 angstroms. While ensuring that the first gate insulating layer 1212 provides sufficient physical and electrical insulation, it also prevents the first gate insulating layer 1212 from being too thick, which would otherwise increase the overall thickness of the array substrate 100, thereby facilitating the overall structural design of the array substrate 100.

[0088] S300 , forming a first gate electrode 1214 , a first source electrode 1213 a , and a first drain electrode 1213 b on the first gate insulating layer 1212 , so that the first source electrode 1213 a and the first drain electrode 1213 b are electrically connected to the first active layer 1211 .

[0089] like Figure 6 As shown, after the first active layer 1211 is separated by the first gate insulating layer 1212, a first gate 1214, a first source 1213a and a first drain 1213b need to be formed on the first gate insulating layer 1212. Since the first gate 1214, the first source 1213a and the first drain 1213b are all conductive structures, when the materials used are the same, the first gate 1214, the first source 1213a and the first drain 1213b can be made simultaneously using the same mask. At this time, the first gate 1214, the first source 1213a and the first drain 1213b are in the same film layer, which is beneficial to simplify the process technology of the array substrate 100 and improve the production efficiency of the array substrate 100.

[0090] Among them, the first active layer 1211, the first gate insulating layer 1212, the first gate 1214, the first source 1213a and the first drain 1213b together form the first thin film transistor 121. Since the material used for the first active layer 1211 includes one or more of indium gallium zinc oxide, indium tin oxide or indium zinc oxide, the first thin film transistor 121 is a metal oxide thin film transistor.

[0091] It should be noted that in the process of forming the first gate insulating layer 1212, a third opening 1212c is opened at a position corresponding to the first active layer 1211 on the first gate insulating layer 1212 by etching, and the third opening 1212c leaks part of the first active layer 1211. When the first source electrode 1213a and the first drain electrode 1213b are formed, the first source electrode 1213a and the first drain electrode 1213b will respectively fill the corresponding third opening 1212c, thereby realizing electrical connection between the first source electrode 1213a and the first drain electrode 1213b and the first active layer 1211.

[0092] The method for manufacturing the array substrate 100 in the embodiment of the present application includes sequentially forming a first active layer 1211 and a first gate insulating layer 1212 on a base substrate 110, then forming a first gate electrode 1214, a first source electrode 1213a, and a first drain electrode 1213b on the first gate insulating layer 1212, and electrically connecting the first source electrode 1213a and the first drain electrode 1213b to the first active layer 1211. By simultaneously forming the first gate electrode 1214, the first source electrode 1213a, and the first drain electrode 1213b on the first gate insulating layer 1212, the first gate electrode 1214, the first source electrode 1213a, and the first drain electrode 1213b are located in the same film layer, thereby omitting a separate photomask for forming the first gate electrode 1214. This simplifies the manufacturing process of the array substrate 100, improves production efficiency, and reduces production costs.

[0093] Optional, such as Figure 4 As shown, in step S200, a first active layer 1211 and a first gate insulating layer 1212 are sequentially formed on the base substrate 110, which mainly includes the following steps:

[0094] S210 , sequentially forming a second active layer 1221 and a second gate insulating layer 1222 on the base substrate 110 .

[0095] After cleaning the base substrate 110, a second active layer 1221 is first deposited on the base substrate 110 and etched according to design requirements to form a target pattern. The second active layer 1221 is made of low-temperature polysilicon, that is, the second active layer 1221 is a low-temperature polysilicon semiconductor.

[0096] After forming the second active layer 1221, a second gate insulating layer 1222 needs to be formed on its surface. The second gate insulating layer 1222 covers the second active layer 1221 and the base substrate 110. On the one hand, the second gate insulating layer 1222 can separate the second active layer 1221, facilitating the design of the connection between subsequent film layers and the second active layer 1221; on the other hand, the second gate insulating layer 1222 can planarize the surface of the second active layer 1221, facilitating the efficient fabrication of subsequent film layers.

[0097] The material used for the second gate insulating layer 1222 includes one or more of silicon oxide, silicon nitride, or silicon oxynitride. The thickness of the second gate insulating layer 1222 is greater than or equal to 1000 angstroms and less than or equal to 5000 angstroms. While ensuring that the second gate insulating layer 1222 provides sufficient physical and electrical insulation, it also prevents the second gate insulating layer 1222 from being too thick, which would otherwise increase the overall thickness of the array substrate 100, thereby facilitating the overall structural design of the array substrate 100.

[0098] S220 , forming a second gate 1216 and a third gate 1223 on the second gate insulating layer 1222 , so that the third gate 1223 is disposed corresponding to the second active layer 1221 .

[0099] After forming the second gate insulating layer 1222, a metal layer is deposited on the second gate insulating layer 1222, and then the metal layer is etched according to design requirements to form a third gate 1223 at a position corresponding to the second active layer 1221, so as to facilitate the structural design of the thin film transistor corresponding to the second active layer 1221.

[0100] While etching the metal layer, a second gate 1216 is formed on the second gate insulating layer 1222, wherein the second gate 1216 corresponds to another thin film transistor, and its specific setting position can be adjusted accordingly according to the setting requirements of the thin film transistor. It is only necessary to ensure that the second gate 1216 and the third gate 1223 are the same metal layer, so that the second gate 1216 and the third gate 1223 can be formed simultaneously under a mask, thereby simplifying the process of the array substrate 100, improving production efficiency and reducing production costs.

[0101] S230 , forming an interlayer dielectric layer 1217 on the second gate 1216 and the third gate 1223 .

[0102] After forming the second gate 1216 and the third gate 1223 by pattern etching, an interlayer dielectric layer 1217 is deposited on the second gate 1216 and the third gate 1223. The interlayer dielectric layer 1217 covers the second gate 1216, the third gate 1223, and the second gate insulating layer 1222. On the one hand, the interlayer dielectric layer 1217 can separate the second gate 1216 and the third gate 1223, facilitating the design of the connection between subsequent film layers and the second gate 1216 and the third gate 1223. On the other hand, the interlayer dielectric layer 1217 can planarize the surface of the second gate 1216 and the third gate 1223, facilitating the efficient fabrication of subsequent film layers.

[0103] The material used for the interlayer dielectric layer 1217 includes one or more of silicon oxide, silicon nitride, or silicon oxynitride. The thickness of the interlayer dielectric layer 1217 is greater than or equal to 1000 angstroms and less than or equal to 5000 angstroms. While ensuring that the interlayer dielectric layer 1217 provides sufficient physical and electrical insulation, it also prevents the interlayer dielectric layer 1217 from being too thick, which would otherwise increase the overall thickness of the array substrate 100, thereby facilitating the overall structural design of the array substrate 100.

[0104] S240 , forming a first active layer 1211 on the interlayer dielectric layer 1217 at a position corresponding to the second gate 1216 .

[0105] After forming the interlayer dielectric layer 1217, a first active layer 1211 is deposited on the interlayer dielectric layer 1217. The first active layer 1211 is then etched to form a target pattern, and the first active layer 1211 is aligned with the second gate 1216. The first active layer 1211 and the second gate 1216 correspond to the same thin film transistor, and arranging the first active layer 1211 and the second gate 1216 in correspondence facilitates the structural design of the thin film transistor.

[0106] S250 , forming a first gate insulating layer 1212 on the first active layer 1211 .

[0107] After the first active layer 1211 is formed by pattern etching, a first gate insulating layer 1212 needs to be formed on its surface so that the first gate insulating layer 1212 covers the first active layer 1211 and the interlayer dielectric layer 1217. On the one hand, the first gate insulating layer 1212 can separate the first active layer 1211, facilitating the design of the connection between subsequent film layers and the first active layer 1211; on the other hand, the first gate insulating layer 1212 can planarize the surface of the first active layer 1211, facilitating the efficient fabrication of subsequent film layers.

[0108] Optionally, forming the first gate 1214, the first source 1213a, and the first drain 1213b on the first gate insulating layer 1212 in step S300 includes:

[0109] A first gate 1214, a first source 1213a, a first drain 1213b, a second source 1226a and a second drain 1226b are formed on the first gate insulating layer 1212, so that the first source 1213a and the first drain 1213b are electrically connected to the first active layer 1211, and the first source 1213a, the second source 1226a and the second drain 1226b are electrically connected to the second active layer 1221.

[0110] The second active layer 1221, the second gate insulating layer 1222, the third gate 1223, the first gate insulating layer 1212, the first source electrode 1213a, and the first drain electrode 1213b form a second thin film transistor 122. Since the second active layer 1221 is made of low-temperature polysilicon, the second thin film transistor 122 is a low-temperature polysilicon thin film transistor.

[0111] It should be noted that in the process of forming the first gate insulating layer 1212, a third opening 1212c is opened on the first gate insulating layer 1212 at a position corresponding to the first active layer 1211 by etching, and the third opening 1212c leaks a portion of the first active layer 1211 to facilitate the electrical connection between the first source electrode 1213a and the first drain electrode 1213b and the first active layer 1211; a fourth opening 1212d is opened on the first gate insulating layer 1212 at a position corresponding to the second active layer 1221 by etching, and the fourth opening 1212d leaks a portion of the second active layer 1221 to facilitate the electrical connection between the second source electrode 1226a and the second drain electrode 1226b and the second active layer 1221.

[0112] In addition, a second opening 1212b is opened on the first gate insulating layer 1212 at a position corresponding to the second active layer 1221 by etching, and the first source electrode 1213a is electrically connected to the second active layer 1221 through the second opening 1212b, that is, the first source electrode 1213a is electrically connected to the first active layer 1211 and the second active layer 1221 at the same time to achieve electrical connection between the first thin film transistor 121 and the second thin film transistor 122, so as to facilitate the coordination and regulation of other functional layer structures arranged on the array substrate 100.

[0113] Specifically, when forming the first gate 1214, the first source 1213a, the first drain 1213b, the second source 1226a and the second drain 1226b on the first gate insulating layer 1212, a metal layer is first deposited on the first gate insulating layer 1212, and then the metal layer is etched according to the target pattern design requirements to simultaneously form the first gate 1214, the first source 1213a, the first drain 1213b, the second source 1226a and the second drain 1226b on the first gate insulating layer 1212, thereby omitting unnecessary masking processes, simplifying the process steps of the array substrate 100, and improving production efficiency.

[0114] Among them, since the first gate 1214, the first source 1213a and the first drain 1213b belong to the first thin film transistor 121 and are located relatively close to each other, in order to ensure that the first gate 1214 is completely separated from the first source 1213a and the first drain 1213b, when etching the metal layer, a gap 1215 is formed between the first gate 1214 and the first source 1213a and the first drain 1213b, and the first gate insulating layer 1212 is further etched. Etching is performed to form a first opening 1212a on the first gate insulating layer 1212 at a position corresponding to the gap 1215 to ensure that the first gate 1214 is completely separated from the first source 1213a and the first drain 1213b, thereby avoiding incomplete etching due to etching accuracy or etching depth during the manufacturing process of the array substrate 100, which may cause interference between the first gate 1214 and the first source 1213a and the first drain 1213b, thereby ensuring the structural stability of the first thin film transistor 121.

[0115] Optionally, the method for manufacturing the array substrate 100 in the embodiment of the present application further includes forming a planarization layer 123 on the first gate electrode 1214, the first source electrode 1213a, the first drain electrode 1213b, the second source electrode 1226a, and the second drain electrode 1226b. The planarization layer 123 covers the first gate insulating layer 1212 and fills the gap 1215 between the first gate electrode 1214 and the first source electrode 1213a and the first drain electrode 1213b, as well as the first opening 1212a in the first gate insulating layer 1212. Providing the planarization layer 123 not only flattens the surface of the array substrate 100 to facilitate connection between the array substrate 100 and subsequent functional layer structures, but also improves electrical insulation between the first gate electrode 1214 and the first source electrode 1213a and the first drain electrode 1213b, thereby preventing mutual interference and enhancing the structural stability of the first thin-film transistor 121.

[0116] Optionally, in the process of manufacturing the array substrate 100, in order to further improve the structural stability of the array substrate 100, after the base substrate 110 is cleaned, a light-shielding metal layer 124 is first formed directly on the surface of the array substrate 100, and then a buffer layer 125 is formed on the light-shielding metal layer 124.

[0117] The location of the light-shielding metal layer 124 can be adjusted based on the target location of the corresponding thin-film transistors, simply by aligning the light-shielding metal layer 124 with the corresponding first active layer 1211 and second active layer 1221. Forming the light-shielding metal layer 124 on the base substrate 110 prevents external ambient light from passing through the base substrate 110 and reaching the first active layer 1211 and second active layer 1221, thereby ensuring the structural stability of the first active layer 1211 and second active layer 1221.

[0118] The buffer layer 125 can separate the light-shielding metal layer 124 from subsequent film layers to avoid mutual interference; at the same time, the buffer layer 125 can also flatten the surface of the light-shielding metal layer 124 to facilitate the effective formation of subsequent film layers.

[0119] It should be noted that during the manufacturing process of the array substrate 100, the various metal film layers in the embodiment of the present application, including the first gate 1214, the second gate 1216, the first source 1213a and the first drain 1213b in the first thin film transistor 121, and the third gate 1223, the fourth gate 1225, the second source 1226a and the second drain 1226b in the second thin film transistor 122, can be coordinated with each other to adopt the same-layer manufacturing method if the manufacturing process is feasible, so as to save the number of mask times to the greatest extent, simplify the process of the array substrate 100, and improve production efficiency.

[0120] Among them, the first thin film transistor 121 and the second thin film transistor 122 can both be a bottom gate structure or a top gate structure. According to the actual structural design requirements, the positions of their corresponding gates can be adjusted. When the relative positions of the first gate 1214, the second gate 1216, the third gate 1223 and the fourth gate 1225 change, the corresponding production process can also be changed accordingly. The gate structure set on the same layer using one mask can also be adjusted accordingly. It is only necessary to ensure that the number of masks is saved while meeting the structural design requirements of the array substrate 100, simplify the process of the array substrate 100, improve the production efficiency of the array substrate 100, and reduce the production cost.

[0121] The above is a detailed introduction to an array substrate, a display panel and a method for manufacturing an array substrate provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea; at the same time, for technical personnel in this field, based on the ideas of the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. An array substrate, characterized in that: The array substrate includes: substrate; a thin film transistor layer disposed on the base substrate; the thin film transistor layer including a first thin film transistor, the first thin film transistor including a first active layer, a first gate insulating layer, and a first source-drain electrode layer stacked on the base substrate, the first gate insulating layer being located between the first active layer and the first source-drain electrode layer, the first source-drain electrode layer including a first source electrode and a first drain electrode electrically connected to the first active layer; the first thin film transistor also including a first gate electrode, the first gate electrode being located on the first gate insulating layer, and the first gate electrode and the first source-drain electrode layer being disposed on the same layer; There is a gap between the first gate and the first source and the first drain, and a first opening is formed on the first gate insulating layer at a position corresponding to the gap; The array substrate includes a planar layer, which is disposed on the first source and drain electrode layer and the first gate electrode, and fills the gap and the first opening.

2. The array substrate according to claim 1, wherein: The first thin film transistor further includes a second gate and an interlayer dielectric layer. The second gate is located on a side of the first active layer close to the base substrate. The interlayer dielectric layer is located between the first active layer and the second gate.

3. The array substrate according to claim 2, wherein: The array substrate includes a second thin film transistor, which is arranged in parallel with the first thin film transistor on the base substrate; the second thin film transistor includes a second active layer, the first gate insulating layer and a second source-drain layer stacked on the base substrate, the first gate insulating layer is located between the second active layer and the second source-drain layer, the second source-drain layer includes a second source and a second drain electrically connected to the second active layer; the second source-drain layer is arranged on the same layer as the first source-drain layer and the first gate.

4. The array substrate according to claim 3, wherein: A second opening is formed on the first gate insulating layer at a position corresponding to the first source electrode, the second opening leaking out of the second active layer, and the first source electrode is electrically connected to the second active layer through the second opening.

5. The array substrate according to claim 3, wherein: The second thin film transistor includes a third gate and a second gate insulating layer, the third gate is arranged corresponding to the second active layer, and the second gate insulating layer is located between the third gate and the second active layer; The third gate is located on a side of the second active layer away from the substrate; or, The third gate is located on a side of the second active layer close to the base substrate.

6. The array substrate according to claim 5, wherein: The third gate is provided on the same layer as the second gate; or, The third gate is provided in the same layer as the first source and drain layer.

7. The array substrate according to any one of claims 3 to 6, wherein: The material of the first active layer includes one or more of indium gallium zinc oxide, indium tin oxide or indium zinc oxide; the material of the second active layer includes low-temperature polysilicon.

8. A display panel, characterized in that: The display panel comprises the array substrate according to any one of claims 1 to 7.

9. A method for manufacturing an array substrate, characterized in that: The method comprises: providing a substrate; forming a first active layer and a first gate insulating layer in sequence on the base substrate; forming a first gate, a first source, and a first drain on the first gate insulating layer, electrically connecting the first source and the first drain to the first active layer, with gaps between the first gate and the first source and the first drain, and forming a first opening on the first gate insulating layer at a position corresponding to the gap; the first active layer, the first gate insulating layer, the first gate, the first source, and the first drain forming a first thin film transistor; A flat layer is formed on the first gate, the first source, and the first drain, wherein the flat layer covers the first gate insulating layer and fills the gap and the first opening.

10. The method for manufacturing an array substrate according to claim 9, wherein: The step of sequentially forming a first active layer and a first gate insulating layer on the base substrate comprises: forming a second active layer and a second gate insulating layer in sequence on the base substrate; forming a second gate and a third gate on the second gate insulating layer, so that the third gate is disposed corresponding to the second active layer; forming an interlayer dielectric layer on the second gate and the third gate; forming a first active layer on the interlayer dielectric layer at a position corresponding to the second gate; A first gate insulating layer is formed on the first active layer.

11. The method for manufacturing an array substrate according to claim 10, wherein: The forming of a first gate, a first source, and a first drain on the first gate insulating layer includes: A first gate, a first source, a first drain, a second source and a second drain are formed on the first gate insulating layer, so that the first source and the first drain are electrically connected to the first active layer, and the first source, the second source and the second drain are electrically connected to the second active layer; the second active layer, the second gate insulating layer, the third gate, the first gate insulating layer, the first source and the first drain form a second thin film transistor.

Images