Detection device

Abstract

The present invention provides a detection device that can improve detection accuracy. The detection device includes: a plurality of detection elements arranged in a matrix; a plurality of scanning lines connected to the plurality of detection elements arranged in a first direction, supplying a plurality of drive signals to the detection elements; a plurality of output signal lines connected to the plurality of detection elements arranged in a second direction, outputting detection signals; a drive circuit supplying a plurality of drive signals to the detection elements; and a detection circuit supplied with detection signals via the output signal lines. The detection element includes: a photoelectric conversion element; a source follower transistor outputting a signal corresponding to the charge generated by the photoelectric conversion element; and a readout transistor reading the output signal of the source follower transistor and outputting a detection signal. During reset, an initial voltage superimposed with a prescribed reference voltage and a threshold voltage of the source follower transistor is applied to the photoelectric conversion element.

Description

Technical Field

[0001] The invention relates to a detection device. Background Art

[0002] For example, a photoelectric conversion device using a PIN (Positive Intrinsic Negative Diode) type photodiode as a photoelectric conversion element for detection is known (for example, refer to Patent Document 1). Such a photoelectric conversion device has a field effect transistor that receives a signal charge generated in a photoelectric conversion unit through a gate, and a source follower transistor that reads a signal voltage corresponding to the signal charge received by the field effect transistor to a signal line is provided for each pixel, and a charge based on input information after photoelectric conversion in the photoelectric conversion unit is transferred to an external capacitor, and converted into a signal voltage through the external capacitor.

[0003] Patent Document 1: Japanese Patent Application Publication No. 2011-10054

[0004] In a detection device using a PIN-type photodiode, it is required to improve the detection sensitivity. For example, a PIN-type photodiode can increase the photocurrent by increasing the sensor area. On the other hand, in order to improve the detection accuracy, high precision is required. When it is desired to take into account both the expansion of the sensor area and high precision, the deviation of the threshold voltage increases due to the miniaturization of the source follower transistor, and there is a possibility that the detection accuracy will be reduced. Summary of the invention

[0005] An object of the present invention is to provide a detection device capable of improving detection accuracy.

[0006] One aspect of the present invention involves a detection device comprising: a plurality of detection elements arranged in a matrix in a detection area; a plurality of scanning lines connected to the plurality of detection elements arranged in a first direction, supplying a plurality of drive signals to the detection elements; a plurality of output signal lines connected to the plurality of detection elements arranged in a second direction different from the first direction, detection signals from the detection elements being output to the output signal lines; a drive circuit supplying a plurality of the drive signals to the detection elements; and a detection circuit to which the detection signals are supplied via the output signal lines, wherein the detection elements comprise: a photoelectric conversion element; a source follower transistor outputting a signal corresponding to a charge generated by the photoelectric conversion element; and a readout transistor reading out the output signal of the source follower transistor and outputting the detection signal, wherein during a reset period, an initial voltage superimposed with a prescribed reference voltage and a threshold voltage of the source follower transistor is applied to the photoelectric conversion element. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1AThis is a cross-sectional view showing a schematic cross-sectional structure of a detection device with an illumination device including the detection device according to the embodiment.

[0008] Figure 1B It is a cross-sectional view showing a schematic cross-sectional structure of a detection device with an illumination device according to a modification.

[0009] Figure 2 It is a top view showing the detection device involved in the embodiment.

[0010] Figure 3 It is a block diagram showing a configuration example of a detection device according to an embodiment.

[0011] Figure 4 : is a circuit diagram showing a detection element according to the embodiment.

[0012] Figure 5 : is a circuit diagram showing a detection element according to a comparative example.

[0013] Figure 6 : is a timing waveform chart showing an operation example of the detection element according to the comparative example.

[0014] Fig. 7A It is shown Figure 6 FIG. 2 is a diagram showing an equivalent circuit of a detection element in a period t11 - t12 .

[0015] Figure 7B It is shown Figure 6 FIG. 2 is a diagram showing an equivalent circuit of a detection element in a period t12 - t13 .

[0016] Figure 7C It is shown Figure 6 FIG. 2 is a diagram showing an equivalent circuit of a detection element in a period t13 - t14 .

[0017] Fig.7D It is shown Figure 6 FIG. 2 is a diagram showing an equivalent circuit of a detection element in a period t14 - t15 .

[0018] Fig. 8A : is a graph showing the relationship between the detection range of the detection signal and the threshold voltage of the source follower transistor in the comparative example.

[0019] Figure 8B It is shown in Fig. 8A Graph showing the relationship between the detection range of the detection signal and the threshold voltage of the source follower transistor when the deviation term of the threshold voltage of the source follower transistor is set to 0.

[0020] Fig. 9 It is a timing waveform chart showing an operation example of the detection element according to the embodiment.

[0021] Fig. 10A It is shown Fig. 9 FIG. 2 is a diagram showing an equivalent circuit of a detection element in a period t21 - t22 .

[0022] Fig. 10B It is shown Fig. 9 FIG. 2 is a diagram showing an equivalent circuit of a detection element in a period t22 - t23 .

[0023] Fig. 10C It is shown Fig. 9 FIG. 2 is a diagram showing an equivalent circuit of a detection element in a period t23 - t24 .

[0024] Fig. 10D It is shown Fig. 9 FIG. 2 is a diagram showing an equivalent circuit of a detection element in a period t24 - t25 .

[0025] Fig.10E It is shown Fig. 9 FIG. 2 is a diagram showing an equivalent circuit of a detection element in a period t25 - t26 .

[0026] Fig.11 : is a diagram showing the relationship between the detection range of the detection signal and the threshold voltage of the source follower transistor in the embodiment. DETAILED DESCRIPTION

[0027] The mode (implementation method) for implementing the present invention is described in detail with reference to the accompanying drawings. It should be noted that the present invention is not limited to the contents described in the following implementation methods. In addition, the constituent elements described below include elements that can be easily thought of by a person skilled in the art, and substantially the same elements. Furthermore, the constituent elements described below can be appropriately combined. In addition, the disclosure is only an example, and appropriate changes that can be easily thought of by a person skilled in the art to maintain the main purpose of the invention are of course included in the scope of the present invention. In addition, in order to make the description clearer, the accompanying drawings schematically represent the width, thickness, shape, etc. of each part compared to the actual situation, but it is only an example and does not limit the interpretation of the present invention. In addition, in this specification and each figure, the same figure mark is marked on the same element as the element described previously for the figure that has appeared, and the detailed description is sometimes appropriately omitted.

[0028] In the present specification and claims, when expressing a manner of configuring another structure on a certain structure, when simply expressed as "on", unless otherwise specified, it includes both a case where the other structure is configured directly on the certain structure in a manner of being connected to the certain structure, and a case where the other structure is configured above the certain structure further separated by another structure.

[0029] Figure 1A2 is a cross-sectional view showing a schematic cross-sectional structure of a detection device with an illumination device having a detection device according to an embodiment. Figure 1A As shown, the detection device 120 with an illumination device includes a detection device 1, an illumination device 121, and a cover glass 122. In a direction perpendicular to the surface of the detection device 1, the illumination device 121, the detection device 1, and the cover glass 122 are stacked in this order.

[0030] The lighting device 121 has a light irradiation surface 121a for irradiating light, and irradiates light L1 from the light irradiation surface 121a to the detection device 1. The lighting device 121 is a backlight source. For example, the lighting device 121 may be a so-called side-light type backlight source having a light guide plate arranged at a position corresponding to the detection area AA and a plurality of light sources arranged at one end or both ends of the light guide plate. As the light source, for example, a light emitting diode (LED: Light Emitting Diode) emitting light of a specified color is used. In addition, the lighting device 121 may also be a so-called direct-down type backlight source having a light source (e.g., LED) arranged directly below the detection area AA. In addition, the lighting device 121 is not limited to a backlight source, and may be arranged on the side or above the detection device 1, or may irradiate the light L1 from the side or above the finger Fg.

[0031] The detection device 1 is disposed opposite to the light irradiation surface 121a of the lighting device 121. The light L1 irradiated from the lighting device 121 passes through the detection device 1 and the cover glass 122. The detection device 1 can detect the detection object (in Figure 1A and Figure 1B In the example shown, it is the unevenness on the surface of the finger Fg (for example, fingerprint). The color of the light L1 from the lighting device 121 may also be different depending on the detection object.

[0032] The cover glass 122 is a component for protecting the detection device 1 and the lighting device 121, and covers the detection device 1 and the lighting device 121. The cover glass 122 is, for example, a glass substrate. It should be noted that the cover glass 122 is not limited to a glass substrate, and may also be a resin substrate or the like. In addition, the cover glass 122 may not be provided. In this case, a protective layer is provided on the surface of the detection device 1, and the detection object (here, the finger Fg) is in contact with the protective layer of the detection device 1.

[0033] The detection device 120 with a lighting device may also be provided with a display panel instead of the lighting device 121. The display panel may be, for example, an organic EL display panel (OLED: Organic Light Emitting Diode), an inorganic EL display panel (micro LED, sub-millimeter LED). Alternatively, the display panel may be a liquid crystal display panel (LCD: Liquid Crystal Display) using a liquid crystal element as a display element, or an electrophoretic display panel (EPD: Electrophoretic Display) using an electrophoretic element as a display element.

[0034] Figure 1B 2 is a cross-sectional view showing a schematic cross-sectional structure of a detection device with an illumination device according to a modified example. Figure 1B As shown, the detection device 120A with an illumination device has the detection device 1, the illumination device 121, and the cover glass 122 stacked in this order in a direction perpendicular to the surface of the detection device 1. In this modification, as the illumination device 121, a display panel such as an organic EL display panel may be used.

[0035] The light L1 emitted from the lighting device 121 passes through the cover glass 122 and is reflected by the finger Fg. The light L2 reflected by the finger Fg passes through the cover glass 122 and then passes through the lighting device 121. The detection device 1 can detect information related to the biological body such as fingerprint detection by receiving the light L2 that passes through the lighting device 121.

[0036] Figure 2 is a top view showing a detection device according to an embodiment. Figure 2 As shown, the detection device 1 includes a substrate 21 , a sensor unit 10 , a scanning line driving circuit 15 , a signal line selecting circuit 16 , a detection circuit 48 , a control circuit 102 , and a power supply circuit 103 .

[0037] The control substrate 101 is electrically connected to the substrate 21 via the wiring substrate 110. The wiring substrate 110 is, for example, a flexible printed substrate or a rigid substrate. A detection circuit 48 is provided on the wiring substrate 110. A control circuit 102 and a power supply circuit 103 are provided on the control substrate 101. The control circuit 102 is, for example, an FPGA (Field Programmable Gate Array). The control circuit 102 supplies control signals to the sensor unit 10, the scan line driving circuit 15, and the signal line selecting circuit 16 to control the detection operation of the sensor unit 10. The power supply circuit 103 supplies a power supply voltage VDD, a reset voltage Vrst, and a reference voltage COM (see Figure 4) and other voltage signals.

[0038] The substrate 21 has a detection area AA and a peripheral area GA. The detection area AA is an area overlapping with the plurality of detection elements 3 of the sensor unit 10. The peripheral area GA is an area outside the detection area AA and is an area not overlapping with the detection element 3. That is, the peripheral area GA is an area between the periphery of the detection area AA and the end of the substrate 21. The scan line drive circuit 15 and the signal line selection circuit 16 are provided in the peripheral area GA.

[0039] The plurality of detection elements 3 of the sensor unit 10 are light sensors each having a photoelectric conversion element 30. The photoelectric conversion element 30 is a photodiode, and is a light detection unit that outputs an electrical signal corresponding to the irradiated light. More specifically, the photoelectric conversion element 30 is a PIN (Positive Intrinsic Negative) photodiode. The detection elements 3 are arranged in a matrix in the detection area AA. The photoelectric conversion elements 30 of the plurality of detection elements 3 perform detection according to a gate drive signal (e.g., a reset control signal RST, a readout control signal RD) supplied from the scanning line drive circuit 15. The plurality of photoelectric conversion elements 30 respectively output an electrical signal corresponding to the irradiated light as a detection signal Vdet to the signal line selection circuit 16. The detection device 1 detects information related to the biological body based on the detection signal Vdet from the plurality of photoelectric conversion elements 30.

[0040] The scan line drive circuit 15 and the signal line selection circuit 16 are provided in the peripheral area GA. Specifically, the scan line drive circuit 15 is provided in a region extending in the second direction Dy in the peripheral area GA. The signal line selection circuit 16 is provided in a region extending in the first direction Dx in the peripheral area GA and is provided between the sensor unit 10 and the detection circuit 48.

[0041] It should be noted that the first direction Dx is a direction in a plane parallel to the substrate 21. The second direction Dy is a direction in a plane parallel to the substrate 21, and is a direction orthogonal to the first direction Dx. It should be noted that the second direction Dy may not be orthogonal to the first direction Dx but may intersect with it. In addition, the third direction Dz is a direction orthogonal to the first direction Dx and the second direction Dy, and is a normal direction of the substrate 21.

[0042] Figure 3 is a block diagram showing an example of the configuration of a detection device according to an embodiment. Figure 3 As shown, the detection device 1 further includes a detection control circuit 11 and a detection unit 40. Part or all of the functions of the detection control circuit 11 may be included in the control circuit 102. In addition, part or all of the functions of the detection unit 40 other than the detection circuit 48 may also be included in the control circuit 102.

[0043] The detection control circuit 11 is a circuit that supplies control signals to the scan line driving circuit 15, the signal line selection circuit 16, and the detection unit 40 to control their operations. The detection control circuit 11 supplies various control signals such as a start signal STV and a clock signal CK to the scan line driving circuit 15. In addition, the detection control circuit 11 supplies various control signals such as a first selection signal SEL and a second selection signal xSEL to the signal line selection circuit 16.

[0044] The scanning line driving circuit 15 drives a plurality of gate lines (the readout control scanning line GLrd, the reset control scanning line GLrst (refer to Figure 4 The scanning line driving circuit 15 selects a plurality of gate lines sequentially or simultaneously, and supplies a gate driving signal (such as a reset control signal RST and a read control signal RD) to the selected gate lines. Thus, the scanning line driving circuit 15 selects a plurality of photoelectric conversion elements 30 connected to the gate lines.

[0045] The signal line selection circuit 16 selects the output signal line SL (see Figure 4 ) is connected to the detection circuit 48 of the detection unit 40 and the second reference voltage COM2 (see Figure 4 ) is a switch circuit for switching between the reference voltage supply lines GLvr of the detection control circuit 11. The signal line selection circuit 16 is, for example, a multiplexer. The signal line selection circuit 16 connects the selected output signal line SL to the detection circuit 48 based on the first selection signal SEL supplied from the detection control circuit 11 via the first selection signal supply line GLsel. Thus, the signal line selection circuit 16 outputs the detection signal Vdet of the photoelectric conversion element 30 to the detection unit 40. In addition, in the present embodiment, the signal line selection circuit 16 supplies the second reference voltage COM2 to the selected output signal line SL based on the second selection signal xSEL supplied from the detection control circuit 11 via the second selection signal supply line GLxsel. The signal line selection circuit 16 may also be included in the detection unit 40.

[0046] The detection unit 40 includes a detection circuit 48, a signal processing circuit 44, a coordinate extraction circuit 45, a storage circuit 46, and a detection timing control circuit 47. The detection timing control circuit 47 controls the detection circuit 48, the signal processing circuit 44, and the coordinate extraction circuit 45 based on a control signal supplied from the detection control circuit 11 so as to synchronize the operations.

[0047] The detection circuit 48 is, for example, an analog front end circuit (AFE). The detection circuit 48 is a signal processing circuit having at least the functions of the detection signal amplifier circuit 42 and the A / D converter circuit 43. The detection signal amplifier circuit 42 is a circuit that amplifies the detection signal Vdet, and is, for example, an integration circuit. The A / D converter circuit 43 converts the analog signal output from the detection signal amplifier circuit 42 into a digital signal.

[0048] The signal processing circuit 44 is a logic circuit that detects a predetermined physical quantity input to the sensor unit 10 based on the output signal of the detection circuit 48. When the finger Fg is in contact with or close to the detection surface, the signal processing circuit 44 can detect the concavity and convexity of the surface of the finger Fg or the palm based on the signal from the detection circuit 48. In addition, the signal processing circuit 44 can also detect information related to the living body based on the signal from the detection circuit 48. The information related to the living body is, for example, the blood vessel image, pulse wave, pulse, blood oxygen saturation, etc. of the finger Fg or the palm.

[0049] The storage circuit 46 temporarily stores the signal calculated by the signal processing circuit 44. The storage circuit 46 may be, for example, a RAM (Random Access Memory) or a register circuit.

[0050] The coordinate extraction circuit 45 is a logic circuit that obtains the detection coordinates of the concavo-convex surface of the finger Fg, etc. when the contact or approach of the finger Fg is detected in the signal processing circuit 44. In addition, the coordinate extraction circuit 45 is a logic circuit that obtains the detection coordinates of the blood vessels of the finger Fg and the palm. The coordinate extraction circuit 45 combines the detection signals Vdet output from each detection element 3 of the sensor unit 10 to generate two-dimensional information representing the shape of the concavo-convex surface of the finger Fg, etc. It should be noted that the coordinate extraction circuit 45 may output the detection signal Vdet as the sensor output Vo without calculating the detection coordinates.

[0051] Next, a circuit configuration example of the detection device 1 will be described. Figure 4 is a circuit diagram showing a detection element according to an embodiment of the present invention. Figure 4 As shown in FIG. 1 , the detection element 3 according to the present embodiment includes a photoelectric conversion element 30, a capacitor Cs, a reset transistor Mrst, a readout transistor Mrd, a source follower transistor Msf, and a switch transistor Tr. The capacitor Cp is a parasitic capacitor of the photoelectric conversion element 30. In addition, the detection element 3 is provided with a reset control scanning line GLrst and a readout control scanning line GLrd as detection drive lines, and an output signal line SL as a wiring for signal readout.

[0052] It should be noted that in Figure 4 In the example shown, the reset transistor Mrst and the read transistor Mrd are respectively two transistors connected in series to form a so-called double-gate structure, but it is not limited to this, and it can also be a so-called single-gate structure, or it can be three or more transistors connected in series. In the following, the reset transistor Mrst and the read transistor Mrd are described as single-gate structures.

[0053] It should be noted that in Figure 4 , one detection element 3 is shown, but the reset control scanning line GLrst, the readout control scanning line GLrd, and the output signal line SL are connected to a plurality of detection elements 3. Specifically, the reset control scanning line GLrst and the readout control scanning line GLrd are connected in the first direction Dx (refer to Figure 2 ) and is connected to a plurality of detection elements 3 arranged in the first direction Dx. In addition, the output signal line SL extends in the second direction Dy and is connected to a plurality of detection elements 3 arranged in the second direction Dy.

[0054] The read control scanning line GLrd is supplied with a read control signal RD from the scanning line driving circuit 15. The reset control scanning line GLrst is supplied with a reset control signal RST from the scanning line driving circuit 15.

[0055] The reset transistor Mrst, the read transistor Mrd, the source follower transistor Msf and the switch transistor Tr are provided corresponding to one photoelectric conversion element 30. The switch transistor Tr is a switch circuit composed of two transistors. The transistors included in the reset transistor Mrst, the read transistor Mrd and the source follower transistor Msf are respectively composed of n-type TFTs (Thin Film Transistor). The two transistors included in the switch transistor Tr are respectively composed of p-type TFTs. However, it is not limited to this, and the transistors included in the reset transistor Mrst, the read transistor Mrd and the source follower transistor Msf can also be respectively composed of p-type TFTs. In addition, the two transistors included in the switch transistor Tr can also be respectively composed of n-type TFTs.

[0056] A first reference voltage COM1 is applied to the anode of the photoelectric conversion element 30. The first reference voltage COM1 is, for example, 2.9 [V]. The cathode of the photoelectric conversion element 30 is connected to the gate of the source follower transistor Msf. In addition, the cathode of the photoelectric conversion element 30 is connected to the capacitor Cs, one of the source and drain of the reset transistor Mrst, and the gate of the source follower transistor Msf. One end of the capacitor Cs is connected to the cathode of the photoelectric conversion element 30, and the other end is connected to the supply terminal of the power supply voltage VDD. The power supply voltage VDD is, for example, 10 [V]. When the photoelectric conversion element 30 is irradiated with light, the signal (voltage) output from the photoelectric conversion element 30 is accumulated in the capacitor Cs and the capacitor Cp. It should be noted that in Figure 4 In FIG. 4 , the capacitor Cs is described as one element, but in reality, the capacitor Cs includes a plurality of capacitors formed between different electrodes.

[0057] The gate of the reset transistor Mrst is connected to the reset control scanning line GLrst. The power supply voltage VDD is supplied to the other of the source and the drain of the reset transistor Mrst via the switching transistor Tr.

[0058] The source follower transistor Msf is connected between the switch transistor Tr and the read transistor Mrd. The gate of the source follower transistor Msf is connected to the cathode of the photoelectric conversion element 30 .

[0059] The read transistor Mrd is connected between the source of the source follower transistor Msf and the output signal line SL. The gate of the read transistor Mrd is connected to the read control scan line GLrd. The drain of the read transistor Mrd is connected to the output signal line SL. Alternatively, the read transistor Mrd may be connected between the drain of the source follower transistor Msf and the output signal line SL, the gate of the read transistor Mrd is connected to the read control scan line GLrd, and the source of the read transistor Mrd is connected to the output signal line SL.

[0060] A switch transistor Tr, which is a switch circuit composed of two transistors, is connected between a supply terminal of a power supply voltage VDD and a drain of a source follower transistor Msf. In addition, the drain of the source follower transistor Msf is connected to the other of the source and the drain of the reset transistor Mrst.

[0061] In this embodiment, when at least one of the read control signal RD and the reset control signal RST is a low level voltage (e.g., -3 [V]), the switch transistor Tr supplies the power supply voltage VDD to the drain of the source follower transistor Msf and the other of the source and drain of the reset transistor Mrst. It should be noted that the high level voltage of the read control signal RD and the reset control signal RST is, for example, 10 [V]. It should be noted that the structure of the switch transistor Tr is not limited to the above-mentioned structure including two transistors. For example, it can also be a structure combining a NAND circuit and a transistor.

[0062] In addition, in this embodiment, the signal line selection circuit 16 (see Figure 3 ) includes a first signal line selection circuit 16a and a second signal line selection circuit 16b.

[0063] The output signal line SL is connected to the detection circuit 48 via the first signal line selection circuit 16a. In addition, the second reference voltage COM2 is supplied to the output signal line SL via the second signal line selection circuit 16b.

[0064] When the first selection signal SEL is a high-level voltage "H", the first signal line selection circuit 16a electrically connects the output signal line SL to the detection circuit 48. A constant current source for passing a bias current Ib through the read transistor Mrd is connected to the input terminal of the detection circuit 48. Thus, the detection signal Vdet applied to the output signal line SL can be detected by the detection element 3. The constant current source can be provided in the detection circuit 48 or in the substrate 21.

[0065] The second signal line selection circuit 16b electrically connects the output signal line SL to the reference voltage supply line GLvr when the second selection signal xSEL is a high-level voltage "H". Thus, the second reference voltage COM2 is supplied to the output signal line SL. The second reference voltage COM2 is, for example, 2.5 [V].

[0066] Here, in order to facilitate the subsequent description, a circuit configuration example and an operation example of a detection device according to a comparative example will be described. Figure 5 FIG. 1 is a circuit diagram showing a detection element according to a comparative example. Figure 5 As shown, the detection element 3a involved in the comparative example has a photoelectric conversion element 30, a capacitor Cs, a reset transistor Mrst, a readout transistor Mrd, and a source follower transistor Msf. The capacitor Cp is a parasitic capacitance of the photoelectric conversion element 30. In addition, the detection element 3a is provided with a reset control scanning line GLrst and a readout control scanning line GLrd as a detection drive line, and an output signal line SL as a wiring for signal readout.

[0067] It should be noted that in Figure 5 In the example shown, the reset transistor Mrst and the read transistor Mrd are respectively two transistors connected in series to form a so-called double-gate structure, but they may also be a single-gate structure like the detection element 3 involved in the embodiment, or three or more transistors may be connected in series. The following description assumes that the reset transistor Mrst and the read transistor Mrd are single-gate structures.

[0068] It should be noted that in Figure 5 , one detection element 3a is shown, but the reset control scanning line GLrst, the readout control scanning line GLrd, and the output signal line SL are connected to a plurality of detection elements 3a. Specifically, the reset control scanning line GLrst and the readout control scanning line GLrd are connected in the first direction Dx (refer to Figure 2 ) and connected to a plurality of detection elements 3a arranged in the first direction Dx. In addition, the output signal line SL extends in the second direction Dy and connected to a plurality of detection elements 3a arranged in the second direction Dy.

[0069] The read control scanning line GLrd is supplied with a read control signal RD from the scanning line driving circuit 15. The reset control scanning line GLrst is supplied with a reset control signal RST from the scanning line driving circuit 15.

[0070] The reset transistor Mrst, the read transistor Mrd, and the source follower transistor Msf are provided corresponding to one photoelectric conversion element 30. The reset transistor Mrst, the read transistor Mrd, and the source follower transistor Msf are each composed of an n-type TFT (Thin Film Transistor) or a p-type TFT.

[0071] A reference voltage COM is applied to the anode of the photoelectric conversion element 30. The reference voltage COM is, for example, 2.9 [V]. The cathode of the photoelectric conversion element 30 is connected to the gate of the source follower transistor Msf. In addition, the cathode of the photoelectric conversion element 30 is connected to the capacitor Cs, one of the source and drain of the reset transistor Mrst, and the gate of the source follower transistor Msf. One end of the capacitor Cs is connected to the cathode of the photoelectric conversion element 30, and the other end is connected to the supply terminal of the reset voltage Vrst. The reset voltage Vrst is, for example, 4.9 [V]. When the photoelectric conversion element 30 is irradiated with light, the signal (voltage) output from the photoelectric conversion element 30 is accumulated in the capacitor Cs and the capacitor Cp. It should be noted that in Figure 5 In FIG. 4 , the capacitor Cs is described as one element, but in reality, the capacitor Cs includes a plurality of capacitors formed between different electrodes.

[0072] The gate of the reset transistor Mrst is connected to the reset control scanning line GLrst, and the other of the source and the drain of the reset transistor Mrst is connected to a supply terminal of the reset voltage Vrst.

[0073] The source follower transistor Msf is connected between a supply terminal of a power supply voltage VDD and the read transistor Mrd. The power supply voltage VDD is, for example, 10 V. The gate of the source follower transistor Msf is connected to the cathode of the photoelectric conversion element 30 .

[0074] The read transistor Mrd is connected between the source of the source follower transistor Msf and the output signal line SL. The gate of the read transistor Mrd is connected to the read control scan line GLrd. The drain of the read transistor Mrd is connected to the output signal line SL. Alternatively, the read transistor Mrd may be connected between the drain of the source follower transistor Msf and the output signal line SL, the gate of the read transistor Mrd is connected to the read control scan line GLrd, and the source of the read transistor Mrd is connected to the output signal line SL.

[0075] A constant current source for passing bias current Ib through read transistor Mrd is connected to the input terminal of detection circuit 48. Thus, detection signal Vdet applied to output signal line SL can be detected by detection element 3a. The constant current source can be provided in detection circuit 48 or in substrate 21.

[0076] Figure 6 : is a timing waveform chart showing an operation example of the detection element according to the comparative example. Fig. 7A It is shown Figure 6 FIG. 2 is a diagram showing an equivalent circuit of a detection element in a period t11 - t12 . Figure 7B It is shown Figure 6 FIG. 2 is a diagram showing an equivalent circuit of a detection element in a period t12 - t13 . Figure 7C It is shown Figure 6 FIG. 2 is a diagram showing an equivalent circuit of a detection element in a period t13 - t14 . Fig.7D It is shown Figure 6 FIG. 2 is a diagram showing an equivalent circuit of a detection element in a period t14 - t15 .

[0077] The detection element 3a performs detection in the order of the reset period Prst, the accumulation period Pch, and the readout period Pdet. The power supply circuit 103 supplies the reference voltage COM to the anode of the photoelectric conversion element 30 throughout the reset period Prst, the accumulation period Pch, and the readout period Pdet. The reset period Prst is a period in which Vdet1, which is a reference value of the voltage variation of the detection signal Vdet corresponding to the light irradiated to the photoelectric conversion element 30, is set to an initial voltage.

[0078] At time t11, the scanning line driving circuit 15 sets the reset control signal RST supplied to the reset control scanning line GLrst to a high level voltage (e.g., 8 [V]), and starts the reset period Prst. At this time, the reset transistor Mrst is turned on (conducting state). As a result, as shown in the following formula (1), the cathode voltage Vpix of the photoelectric conversion element 30 becomes the reset voltage Vrst (refer to Fig. 7A ).

[0079] Vpix=Vrst…(1)

[0080] At time t12, the scanning line driving circuit 15 sets the reset control signal RST supplied to the reset control scanning line GLrst to a low level voltage (e.g., -3 [V]), and sets the readout control signal RD supplied to the readout control scanning line GLrd to a high level voltage (e.g., 10 [V]). As a result, the reset transistor Mrst is turned off (non-conducting state), and the readout transistor Mrd is turned on (conducting state).

[0081] As a result, at time t13, the cathode voltage Vpix of the photoelectric conversion element 30 is expressed as follows (2) (see Figure 7B At this time, the voltage Vsig of the output signal line SL, that is, the voltage Vdet1 of the detection signal Vdet output from the output signal line SL is expressed as follows (3) (refer to Figure 7B It should be noted that, in the following equations (2) and (3), ΔV is a signal component that varies according to the light irradiating the photoelectric conversion element 30 during the period from time t12 to time t13, and Vth is a threshold voltage of the source follower transistor Msf.

[0082] Vpix=Vrst-ΔV…(2)

[0083] Vsig=Vdet1=Vrst-ΔV-Vth...(3)

[0084] The scanning line driving circuit 15 sets the read control signal RD to a low-level voltage at time t13 , thereby turning off the read transistor Mrd (non-conductive state) and starting the accumulation period Pch (a period from time t13 to time t14 ).

[0085] In the accumulation period Pch, the cathode voltage Vpix of the photoelectric conversion element 30 is expressed as the following equation (4), and the voltage Vsig of the output signal line SL is expressed as the following equation (5) (see Figure 7C ).

[0086] Vpix<Vrst-ΔV…(4)

[0087] Vsig=0…(5)

[0088] The scanning line driving circuit 15 sets the read control signal RD to a high level voltage at time t14, thereby turning on the read transistor Mrd (conductive state), and starting the read period Pdet (a period from time t14 to time t15).

[0089] As a result, at time t15, the cathode voltage Vpix of the photoelectric conversion element 30 is expressed as follows (6) (see Fig.7D At this time, the voltage Vsig of the output signal line SL, that is, the voltage Vdet2 of the detection signal Vdet output from the output signal line SL is expressed as follows (7) (refer to Fig.7D ). It should be noted that, in the following equations (6) and (7), ΔVch is a signal component that varies according to the light irradiating the photoelectric conversion element 30 during the accumulation period Pch and the readout period Pdet (the period from time t13 to time t15).

[0090] Vpix=Vrst-ΔV-ΔVch...(6)

[0091] Vsig=Vdet2=Vrst-ΔV-ΔVch-Vth...(7)

[0092] The difference between the voltage Vdet1 of the detection signal Vdet at time t13 (expression (3) above) and the voltage Vdet2 of the detection signal Vdet at time t15 (expression (7) above) is expressed as the following expression (8). The detection unit 40 performs detection processing based on the difference ΔVch.

[0093] Vdet1-Vdet2=ΔVch…(8)

[0094] In the detection element 3 a according to the comparative example, the voltages Vdet1 and Vdet2 of the detection signal Vdet include the threshold voltage Vth of the source follower transistor Msf. The threshold voltage Vth of the source follower transistor Msf varies depending on the manufacturing process of the substrate 21 .

[0095] In addition, due to miniaturization of the manufacturing process of the substrate 21 , there is a tendency for the input value of the detection circuit 48 , that is, the detection range of the detection signal Vdet to be narrowed.

[0096] Therefore, depending on the deviation range of the threshold voltage Vth of the source follower transistor Msf, there is a case where sufficient detection sensitivity cannot be obtained.

[0097] Fig. 8A is a diagram showing the relationship between the detection range of the detection signal and the threshold voltage of the source follower transistor in the comparative example. Fig. 8A In FIG. 1 , the horizontal axis represents the threshold voltage Vth of the source follower transistor Msf, and the vertical axis represents the detection signal Vdet. Fig. 8A In , the upper limit value of the threshold voltage Vth of the source follower transistor Msf is set to VthH, and the lower limit value of the threshold voltage Vth of the source follower transistor Msf is set to VthL. Fig. 8A In the embodiment, the upper limit value of the detection range of the detection signal Vdet is set to VdetH, and the lower limit value of the detection range of the detection signal Vdet is set to VdetL. The upper limit value VdetH of the detection range of the detection signal Vdet is, for example, 2.9 [V]. The lower limit value VdetL of the detection range of the detection signal Vdet is, for example, 0.4 [V]. In addition, VmH and VmL represent voltage margins that take into account the temperature characteristics and reliability of the source follower transistor Msf. The voltage margins VmH and VmL are, for example, 0.4 [V]. That is, the detection range of the detection signal Vdet is set from VdetL+VmL (for example, 0.8 [V]) to VdetH-VmH (for example, 2.5 [V]).

[0098] like Fig. 8A As shown, when the difference ΔVth between the upper limit value VthH of the threshold voltage Vth of the source follower transistor Msf and the lower limit value VthL of the threshold voltage Vth of the source follower transistor Msf is considered, the detection sensitivity S, that is, the maximum detection range ΔVchmax of the actual detection signal Vdet is as shown in the following formula (9) (refer to Fig. 8A ).

[0099] S=ΔVchmax

[0100] =(VdetH-VmH)-(VdetL+VmL)-ΔVth...(9)

[0101] Here, for example, when VdetH=2.9 [V], VdetL=0.4 [V], voltage margin VmH=VmL=0.4 [V], ΔVth=1.3 [V], the detection sensitivity S (=ΔVchmax) is 0.4 [V].

[0102] According to the above formula (9), if ΔVth, that is, the deviation term of the threshold voltage Vth of the source follower transistor Msf, can be made zero, the detection sensitivity S, that is, the maximum detection range ΔVchmax of the actual detection signal Vdet is as shown in the following formula (10) (refer to Figure 8B ). Figure 8B It is shown in Fig. 8A Graph showing the relationship between the detection range of the detection signal and the threshold voltage of the source follower transistor when the deviation term of the threshold voltage of the source follower transistor is set to 0.

[0103] S=ΔVchmax

[0104] =(VdetH-VmH)-(VdetL+VmL)…(10)

[0105] Here, when VdetH=2.9[V], VdetL=0.4[V], and voltage margin VmH=VmL=0.4[V], the detection sensitivity S (=ΔVchmax) is 1.7[V], and the detection sensitivity S can be further increased. Figure 4 An operation example of the detection device 1 having the structure shown will be described.

[0106] Fig. 9 It is a timing waveform chart showing an operation example of the detection element according to the embodiment. Fig. 10A It is shown Fig. 9 FIG. 2 is a diagram showing an equivalent circuit of a detection element in a period t21 - t22 . Fig. 10B It is shown Fig. 9 FIG. 2 is a diagram showing an equivalent circuit of a detection element in a period t22 - t23 . Fig. 10C It is shown Fig. 9 FIG. 2 is a diagram showing an equivalent circuit of a detection element in a period t23 - t24 . Fig. 10D It is shown Fig. 9 FIG. 2 is a diagram showing an equivalent circuit of a detection element in a period t24 - t25 . Fig.10E It is shown Fig. 9 FIG. 2 is a diagram showing an equivalent circuit of a detection element in a period t25-t26. It should be noted that the same description as that of the above-mentioned comparative example will be omitted.

[0107] The detection element 3 performs detection in the order of the reset period Prst, the accumulation period Pch, and the readout period Pdet. The power supply circuit 103 supplies the first reference voltage COM1 to the anode of the photoelectric conversion element 30 throughout the reset period Prst, the accumulation period Pch, and the readout period Pdet. The reset period Prst is a period in which Vdet1, which is a reference value of the voltage variation of the detection signal Vdet corresponding to the light irradiated to the photoelectric conversion element 30, is set to an initial voltage.

[0108] At time t21, the scan line drive circuit 15 sets the reset control signal RST supplied to the reset control scan line GLrst to a high level voltage (e.g., 10 [V]), and the control circuit 102 sets the first selection signal SEL to a low level voltage [L] and the second selection signal xSEL to a high level voltage [H]. Thus, the reset period Prst begins. At this time, the reset transistor Mrst and the switch transistor Tr are turned on (conducting state). Thus, as shown in the following formula (11), the cathode voltage Vpix of the photoelectric conversion element 30 becomes the power supply voltage VDD (refer to Fig. 10A ).

[0109] Vpix=VDD…(11)

[0110] At time t22, the scanning line driving circuit 15 sets the readout control signal RD supplied to the readout control scanning line GLrd to a high level voltage (eg, 10 [V]), thereby turning on the readout transistor Mrd (conductive state) and turning off the switching transistor Tr (non-conductive state).

[0111] As a result, at time t23, the cathode voltage Vpix of the photoelectric conversion element 30 is expressed as follows (12) (see Fig. 10B ). It should be noted that, in the following formula (12), Vth is the threshold voltage of the source follower transistor Msf.

[0112] Vpix=COM2+Vth…(12)

[0113] At time t23, the scan line driving circuit 15 sets the reset control signal RST supplied to the reset control scan line GLrst to a low level voltage (e.g., -3 [V]), and the control circuit 102 sets the first selection signal SEL to a high level voltage [H] and the second selection signal xSEL to a low level voltage [L]. As a result, the reset transistor Mrst is turned off (non-conducting state), and the switching transistor Tr is turned on (conducting state).

[0114] As a result, at time t24, the cathode voltage Vpix of the photoelectric conversion element 30 is expressed as follows (13) (see Fig. 10C At this time, the voltage Vsig of the output signal line SL, that is, the voltage Vdet1 of the detection signal Vdet output from the output signal line SL is expressed as follows (14) (refer to Fig. 10C ). It should be noted that, in the following equations (13) and (14), ΔV is a signal component that varies according to the light irradiating the photoelectric conversion element 30 during the period from time t23 to time t24.

[0115] Vpix=COM2+Vth-ΔV…(13)

[0116] Vdet=Vdet1=COM2-ΔV…(14)

[0117] The scanning line driving circuit 15 sets the read control signal RD to a low-level voltage at time t24, thereby turning off the read transistor Mrd (non-conductive state) and starting the accumulation period Pch (a period from time t24 to time t25).

[0118] During the accumulation period Pch, the cathode voltage Vpix of the photoelectric conversion element 30 is expressed as the following equation (15), and the voltage Vsig of the output signal line SL is expressed as the following equation (16) (see Fig. 10D ).

[0119] Vpix<COM2+Vth-ΔV…(15)

[0120] Vsig=Vdet=0…(16)

[0121] The scanning line driving circuit 15 sets the read control signal RD to a high level voltage at time t25, thereby turning on the read transistor Mrd (conductive state), and starting the read period Pdet (a period from time t25 to time t26).

[0122] As a result, at time t26, the cathode voltage Vpix of the photoelectric conversion element 30 is expressed as follows (17) (see Fig.10E At this time, the voltage Vsig of the output signal line SL, that is, the voltage Vdet2 of the detection signal Vdet output from the output signal line SL is expressed as follows (18) (refer to Fig.10E ). It should be noted that, in the following equations (17) and (18), ΔVch is a signal component that varies according to the light irradiating the photoelectric conversion element 30 during the accumulation period Pch and the readout period Pdet (the period from time t24 to time t26).

[0123] Vpix=COM2+Vth-ΔV-ΔVch...(17)

[0124] Vdet=Vdet2=COM2-ΔV-ΔVch...(18)

[0125] The difference between the voltage Vdet1 of the detection signal Vdet at time t24 (expression (14) above) and the voltage Vdet2 of the detection signal Vdet at time t26 (expression (18) above) is expressed as the following expression (19). The detection unit 40 performs detection processing based on the difference ΔVch.

[0126] Vdet1-Vdet2=ΔVch…(19)

[0127] Fig.11 is a diagram showing the relationship between the detection range of the detection signal and the threshold voltage of the source follower transistor in the embodiment. Fig.11 In FIG. 1 , the horizontal axis represents the threshold voltage Vth of the source follower transistor Msf, and the vertical axis represents the detection signal Vdet. Fig.11 In , the upper limit value of the threshold voltage Vth of the source follower transistor Msf is set to VthH, and the lower limit value of the threshold voltage Vth of the source follower transistor Msf is set to VthL. Fig.11In the embodiment, the upper limit value of the detection range of the detection signal Vdet is set to VdetH, and the lower limit value of the detection range of the detection signal Vdet is set to VdetL. The upper limit value VdetH of the detection range of the detection signal Vdet is, for example, 2.9 [V]. The lower limit value VdetL of the detection range of the detection signal Vdet is, for example, 0.4 [V]. In addition, VmH and VmL represent voltage margins that take into account the temperature characteristics and reliability of the source follower transistor Msf. The voltage margins VmH and VmL are, for example, 0.4 [V]. That is, the detection range of the detection signal Vdet is set from VdetL+VmL (for example, 0.8 [V]) to VdetH-VmH (for example, 2.5 [V]).

[0128] In the detection element 3 according to the embodiment, the voltages Vdet1 and Vdet2 of the detection signal Vdet do not include the threshold voltage Vth of the source follower transistor Msf. Fig.11 As shown, the detection sensitivity S, that is, the maximum detection range ΔVchmax of the actual detection signal Vdet is as shown in the following formula (20) (refer to Fig.11 ).

[0129] S=ΔVchmax

[0130] =(VdetH-VmH)-(VdetL+VmL)…(20)

[0131] Here, for example, when VdetH=2.9[V], VdetL=0.4[V], and voltage margin VmH=VmL=0.4[V], the detection sensitivity S (=ΔVchmax) is 1.7[V], and the detection sensitivity S can be made wider than that in the comparative example. Thus, the detection accuracy of the detection device 1 can be improved.

[0132] Specifically, for example, the accumulation period Pch can be shortened. This can shorten the authentication time of biometric information such as fingerprints.

[0133] In addition, specifically, for example, it is possible to reduce the light emission intensity of the light source such as the lighting device 121. This can reduce power consumption.

[0134] In addition, specifically, for example, the sensor area can be reduced. Thus, the sensor unit 10 can be made more precise. Therefore, for example, more detailed biological information such as sweat glands of fingers can be used for authentication.

[0135] The above-mentioned embodiment can appropriately combine each constituent element. In addition, about other effects brought by the method described in this embodiment, the effects obvious from the record of this specification, or the effects that can be appropriately thought of by those skilled in the art, can certainly be understood as brought by the present invention.

[0136] Description of Reference Numerals

[0137] 1 Detection device 3, 3a Detection element

[0138] 10 sensor unit 15 scanning line driving circuit

[0139] 16Signal line selection circuit 16aFirst signal line selection circuit

[0140] 16b Second signal line selection circuit 21 substrate

[0141] 30 photoelectric conversion element 48 detection circuit

[0142] AA detection area GA surrounding area

[0143] GLrd readout control scan line GLrst reset control scan line

[0144] GLsel first selection signal supply line GLvr reference voltage supply line

[0145] GLxsel second selection signal supply line Mrst reset transistor

[0146] Mrd readout transistor Msf source follower transistor

[0147] Tr switching transistor RST reset control signal

[0148] RD read control signal SEL first selection signal

[0149] SL output signal line COM reference voltage

[0150] COM1 first reference voltage COM2 second reference voltage

[0151] VDD power supply voltage Vrst reset voltage

[0152] xSEL second selection signal.

Claims

1. A detection device, comprising: Multiple detection elements are arranged in a matrix in the detection area; A plurality of scanning lines are connected to the plurality of detection elements arranged in a first direction, and supply a plurality of driving signals to the detection elements; a plurality of output signal lines connected to the plurality of detection elements arranged in a second direction different from the first direction, detection signals from the detection elements being output to the output signal lines; A driving circuit for supplying a plurality of driving signals to the detection element; as well as a detection circuit, the detection signal being supplied to the detection circuit via the output signal line, The detection element has: Photoelectric conversion element; a source follower transistor that outputs a signal corresponding to the charge generated by the photoelectric conversion element; and a readout transistor for reading out the output signal of the source follower transistor and outputting the detection signal, During a reset period, an initial voltage in which a prescribed reference voltage is superimposed on a threshold voltage of the source follower transistor is applied to the photoelectric conversion element, wherein the reference voltage is a voltage input from the output signal line.

2. The detection device according to claim 1, wherein: During the reset period, the reference voltage is applied to the detection element via the read transistor and the source follower transistor, and the initial voltage is set for the photoelectric conversion element.

3. The detection device according to claim 2, wherein: The detection device includes a signal line selection circuit that switches a connection destination of the output signal line between the detection circuit and a reference voltage supply line. During the reset period, the signal line selection circuit connects the output signal line to the reference voltage supply line to supply the reference voltage, and then connects the output signal line to the detection circuit.

4. The detection device according to any one of claims 1 to 3, wherein: The detection device comprises: a switching transistor for supplying or cutting off a prescribed power supply voltage to the source follower transistor; as well as a reset transistor for supplying or cutting off the power supply voltage to the photoelectric conversion element, The plurality of driving signals include: A readout control signal controls the readout transistor and the switch transistor; and A reset control signal controls the reset transistor and the switch transistor. The plurality of scanning lines include: a readout control scanning line for supplying the readout control signal to the readout transistor and the switch transistor; and The reset control scanning line supplies the reset control signal to the reset transistor and the switch transistor.

5. The detection device according to claim 4, wherein: During the reset period, the driving circuit controls the switching transistor to be turned off and the readout transistor to be turned on after the reset transistor and the switching transistor are turned on. Furthermore, after the reset transistor is turned off and the switching transistor is turned on, the readout transistor is turned off. The drive circuit controls the readout transistor to be turned on after an accumulation period following the reset period, thereby starting a readout period.

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